1965 lines
42 KiB
C++
1965 lines
42 KiB
C++
// Copyright (c) Facebook, Inc. and its affiliates.
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// All rights reserved.
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//
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// Copyright 2019 Google LLC
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//
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// This source code is licensed under the BSD-style license found in the
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// LICENSE file in the root directory of this source tree.
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//
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// Auto-generated file. Do not edit!
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// Specification: test/f32-igemm.yaml
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// Generator: tools/generate-gemm-test.py
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#include <gtest/gtest.h>
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#include <xnnpack/allocator.h>
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#include <xnnpack/common.h>
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#include <xnnpack/isa-checks.h>
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#include <xnnpack/gemm.h>
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#include <xnnpack/igemm.h>
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#include <xnnpack/ppmm.h>
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#include "gemm-microkernel-tester.h"
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#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
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TEST(F32_IGEMM_1X8__WASMSIMD_SPLAT, k_eq_4) {
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GemmMicrokernelTester()
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.mr(1)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(1)
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.n(8)
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.k(4)
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.Test(xnn_f32_igemm_ukernel_1x8__wasmsimd_splat);
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}
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TEST(F32_IGEMM_1X8__WASMSIMD_SPLAT, strided_cn) {
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GemmMicrokernelTester()
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.mr(1)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(1)
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.n(8)
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.k(4)
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.cn_stride(11)
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.Test(xnn_f32_igemm_ukernel_1x8__wasmsimd_splat);
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}
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TEST(F32_IGEMM_1X8__WASMSIMD_SPLAT, k_eq_4_subtile) {
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for (uint32_t n = 1; n <= 8; n++) {
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for (uint32_t m = 1; m <= 1; m++) {
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GemmMicrokernelTester()
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.mr(1)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(m)
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.n(n)
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.k(4)
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.iterations(1)
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.Test(xnn_f32_igemm_ukernel_1x8__wasmsimd_splat);
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}
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}
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}
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TEST(F32_IGEMM_1X8__WASMSIMD_SPLAT, k_eq_4_subtile_m) {
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for (uint32_t m = 1; m <= 1; m++) {
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GemmMicrokernelTester()
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.mr(1)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(m)
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.n(8)
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.k(4)
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.iterations(1)
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.Test(xnn_f32_igemm_ukernel_1x8__wasmsimd_splat);
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}
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}
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TEST(F32_IGEMM_1X8__WASMSIMD_SPLAT, k_eq_4_subtile_n) {
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for (uint32_t n = 1; n <= 8; n++) {
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GemmMicrokernelTester()
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.mr(1)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(1)
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.n(n)
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.k(4)
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.iterations(1)
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.Test(xnn_f32_igemm_ukernel_1x8__wasmsimd_splat);
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}
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}
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TEST(F32_IGEMM_1X8__WASMSIMD_SPLAT, k_lt_4) {
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for (size_t k = 1; k < 4; k++) {
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GemmMicrokernelTester()
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.mr(1)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(1)
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.n(8)
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.k(k)
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.Test(xnn_f32_igemm_ukernel_1x8__wasmsimd_splat);
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}
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}
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TEST(F32_IGEMM_1X8__WASMSIMD_SPLAT, k_lt_4_subtile) {
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for (size_t k = 1; k < 4; k++) {
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for (uint32_t n = 1; n <= 8; n++) {
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for (uint32_t m = 1; m <= 1; m++) {
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GemmMicrokernelTester()
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.mr(1)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(m)
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.n(n)
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.k(k)
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.iterations(1)
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.Test(xnn_f32_igemm_ukernel_1x8__wasmsimd_splat);
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}
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}
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}
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}
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TEST(F32_IGEMM_1X8__WASMSIMD_SPLAT, k_gt_4) {
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for (size_t k = 5; k < 8; k++) {
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GemmMicrokernelTester()
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.mr(1)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(1)
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.n(8)
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.k(k)
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.Test(xnn_f32_igemm_ukernel_1x8__wasmsimd_splat);
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}
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}
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TEST(F32_IGEMM_1X8__WASMSIMD_SPLAT, k_gt_4_subtile) {
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for (size_t k = 5; k < 8; k++) {
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for (uint32_t n = 1; n <= 8; n++) {
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for (uint32_t m = 1; m <= 1; m++) {
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GemmMicrokernelTester()
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.mr(1)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(m)
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.n(n)
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.k(k)
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.iterations(1)
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.Test(xnn_f32_igemm_ukernel_1x8__wasmsimd_splat);
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}
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}
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}
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}
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TEST(F32_IGEMM_1X8__WASMSIMD_SPLAT, k_div_4) {
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for (size_t k = 8; k <= 40; k += 4) {
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GemmMicrokernelTester()
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.mr(1)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(1)
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.n(8)
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.k(k)
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.Test(xnn_f32_igemm_ukernel_1x8__wasmsimd_splat);
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}
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}
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TEST(F32_IGEMM_1X8__WASMSIMD_SPLAT, k_div_4_subtile) {
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for (size_t k = 8; k <= 40; k += 4) {
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for (uint32_t n = 1; n <= 8; n++) {
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for (uint32_t m = 1; m <= 1; m++) {
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GemmMicrokernelTester()
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.mr(1)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(m)
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.n(n)
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.k(k)
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.iterations(1)
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.Test(xnn_f32_igemm_ukernel_1x8__wasmsimd_splat);
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}
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}
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}
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}
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TEST(F32_IGEMM_1X8__WASMSIMD_SPLAT, n_gt_8) {
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for (uint32_t n = 9; n < 16; n++) {
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for (size_t k = 1; k <= 20; k += 5) {
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GemmMicrokernelTester()
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.mr(1)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(1)
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.n(n)
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.k(k)
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.Test(xnn_f32_igemm_ukernel_1x8__wasmsimd_splat);
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}
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}
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}
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TEST(F32_IGEMM_1X8__WASMSIMD_SPLAT, n_gt_8_strided_cn) {
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for (uint32_t n = 9; n < 16; n++) {
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for (size_t k = 1; k <= 20; k += 5) {
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GemmMicrokernelTester()
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.mr(1)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(1)
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.n(n)
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.k(k)
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.cn_stride(11)
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.Test(xnn_f32_igemm_ukernel_1x8__wasmsimd_splat);
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}
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}
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}
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TEST(F32_IGEMM_1X8__WASMSIMD_SPLAT, n_gt_8_subtile) {
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for (uint32_t n = 9; n < 16; n++) {
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for (size_t k = 1; k <= 20; k += 5) {
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for (uint32_t m = 1; m <= 1; m++) {
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GemmMicrokernelTester()
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.mr(1)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(m)
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.n(n)
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.k(k)
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.iterations(1)
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.Test(xnn_f32_igemm_ukernel_1x8__wasmsimd_splat);
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}
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}
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}
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}
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TEST(F32_IGEMM_1X8__WASMSIMD_SPLAT, n_div_8) {
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for (uint32_t n = 16; n <= 24; n += 8) {
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for (size_t k = 1; k <= 20; k += 5) {
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GemmMicrokernelTester()
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.mr(1)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(1)
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.n(n)
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.k(k)
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.Test(xnn_f32_igemm_ukernel_1x8__wasmsimd_splat);
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}
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}
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}
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TEST(F32_IGEMM_1X8__WASMSIMD_SPLAT, n_div_8_strided_cn) {
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for (uint32_t n = 16; n <= 24; n += 8) {
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for (size_t k = 1; k <= 20; k += 5) {
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GemmMicrokernelTester()
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.mr(1)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(1)
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.n(n)
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.k(k)
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.cn_stride(11)
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.Test(xnn_f32_igemm_ukernel_1x8__wasmsimd_splat);
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}
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}
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}
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TEST(F32_IGEMM_1X8__WASMSIMD_SPLAT, n_div_8_subtile) {
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for (uint32_t n = 16; n <= 24; n += 8) {
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for (size_t k = 1; k <= 20; k += 5) {
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for (uint32_t m = 1; m <= 1; m++) {
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GemmMicrokernelTester()
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.mr(1)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(m)
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.n(n)
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.k(k)
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.iterations(1)
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.Test(xnn_f32_igemm_ukernel_1x8__wasmsimd_splat);
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}
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}
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}
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}
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TEST(F32_IGEMM_1X8__WASMSIMD_SPLAT, small_kernel) {
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for (size_t k = 1; k <= 20; k += 5) {
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GemmMicrokernelTester()
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.mr(1)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(1)
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.n(8)
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.k(k)
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.ks(3)
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.Test(xnn_f32_igemm_ukernel_1x8__wasmsimd_splat);
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}
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}
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TEST(F32_IGEMM_1X8__WASMSIMD_SPLAT, small_kernel_subtile) {
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for (size_t k = 1; k <= 20; k += 5) {
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for (uint32_t n = 1; n <= 8; n++) {
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for (uint32_t m = 1; m <= 1; m++) {
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GemmMicrokernelTester()
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.mr(1)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(m)
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.n(n)
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.k(k)
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.ks(3)
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.iterations(1)
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.Test(xnn_f32_igemm_ukernel_1x8__wasmsimd_splat);
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}
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}
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}
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}
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TEST(F32_IGEMM_1X8__WASMSIMD_SPLAT, n_gt_8_small_kernel) {
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for (uint32_t n = 9; n < 16; n++) {
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for (size_t k = 1; k <= 20; k += 5) {
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GemmMicrokernelTester()
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.mr(1)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(1)
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.n(n)
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.k(k)
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.ks(3)
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.Test(xnn_f32_igemm_ukernel_1x8__wasmsimd_splat);
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}
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}
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}
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TEST(F32_IGEMM_1X8__WASMSIMD_SPLAT, n_div_8_small_kernel) {
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for (uint32_t n = 16; n <= 24; n += 8) {
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for (size_t k = 1; k <= 20; k += 5) {
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GemmMicrokernelTester()
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.mr(1)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(1)
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.n(n)
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.k(k)
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.ks(3)
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.Test(xnn_f32_igemm_ukernel_1x8__wasmsimd_splat);
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}
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}
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}
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TEST(F32_IGEMM_1X8__WASMSIMD_SPLAT, strided_cm_subtile) {
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for (size_t k = 1; k <= 20; k += 5) {
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for (uint32_t n = 1; n <= 8; n++) {
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for (uint32_t m = 1; m <= 1; m++) {
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GemmMicrokernelTester()
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.mr(1)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(m)
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.n(n)
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.k(k)
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.cm_stride(11)
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.iterations(1)
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.Test(xnn_f32_igemm_ukernel_1x8__wasmsimd_splat);
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}
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}
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}
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}
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TEST(F32_IGEMM_1X8__WASMSIMD_SPLAT, a_offset) {
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for (size_t k = 1; k <= 20; k += 5) {
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GemmMicrokernelTester()
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.mr(1)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(1)
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.n(8)
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.k(k)
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.ks(3)
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.a_offset(23)
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.Test(xnn_f32_igemm_ukernel_1x8__wasmsimd_splat);
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}
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}
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TEST(F32_IGEMM_1X8__WASMSIMD_SPLAT, zero) {
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for (size_t k = 1; k <= 20; k += 5) {
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for (uint32_t mz = 0; mz < 1; mz++) {
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GemmMicrokernelTester()
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.mr(1)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(1)
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.n(8)
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.k(k)
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.ks(3)
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.a_offset(23)
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.zero_index(mz)
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.Test(xnn_f32_igemm_ukernel_1x8__wasmsimd_splat);
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}
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}
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}
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TEST(F32_IGEMM_1X8__WASMSIMD_SPLAT, strided_cm) {
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GemmMicrokernelTester()
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.mr(1)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(1)
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.n(8)
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.k(4)
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.cm_stride(11)
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.Test(xnn_f32_igemm_ukernel_1x8__wasmsimd_splat);
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}
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#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
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#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
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TEST(F32_IGEMM_4X8__WASMSIMD_SPLAT, k_eq_4) {
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GemmMicrokernelTester()
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.mr(4)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(4)
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.n(8)
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.k(4)
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.Test(xnn_f32_igemm_ukernel_4x8__wasmsimd_splat);
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}
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TEST(F32_IGEMM_4X8__WASMSIMD_SPLAT, strided_cn) {
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GemmMicrokernelTester()
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.mr(4)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(4)
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.n(8)
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.k(4)
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.cn_stride(11)
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.Test(xnn_f32_igemm_ukernel_4x8__wasmsimd_splat);
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}
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TEST(F32_IGEMM_4X8__WASMSIMD_SPLAT, k_eq_4_subtile) {
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for (uint32_t n = 1; n <= 8; n++) {
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for (uint32_t m = 1; m <= 4; m++) {
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GemmMicrokernelTester()
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.mr(4)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(m)
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.n(n)
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.k(4)
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.iterations(1)
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.Test(xnn_f32_igemm_ukernel_4x8__wasmsimd_splat);
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}
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}
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}
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TEST(F32_IGEMM_4X8__WASMSIMD_SPLAT, k_eq_4_subtile_m) {
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for (uint32_t m = 1; m <= 4; m++) {
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GemmMicrokernelTester()
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.mr(4)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(m)
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.n(8)
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.k(4)
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.iterations(1)
|
|
.Test(xnn_f32_igemm_ukernel_4x8__wasmsimd_splat);
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_4X8__WASMSIMD_SPLAT, k_eq_4_subtile_n) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(4)
|
|
.iterations(1)
|
|
.Test(xnn_f32_igemm_ukernel_4x8__wasmsimd_splat);
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_4X8__WASMSIMD_SPLAT, k_lt_4) {
|
|
for (size_t k = 1; k < 4; k++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(k)
|
|
.Test(xnn_f32_igemm_ukernel_4x8__wasmsimd_splat);
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_4X8__WASMSIMD_SPLAT, k_lt_4_subtile) {
|
|
for (size_t k = 1; k < 4; k++) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_f32_igemm_ukernel_4x8__wasmsimd_splat);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_4X8__WASMSIMD_SPLAT, k_gt_4) {
|
|
for (size_t k = 5; k < 8; k++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(k)
|
|
.Test(xnn_f32_igemm_ukernel_4x8__wasmsimd_splat);
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_4X8__WASMSIMD_SPLAT, k_gt_4_subtile) {
|
|
for (size_t k = 5; k < 8; k++) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_f32_igemm_ukernel_4x8__wasmsimd_splat);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_4X8__WASMSIMD_SPLAT, k_div_4) {
|
|
for (size_t k = 8; k <= 40; k += 4) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(k)
|
|
.Test(xnn_f32_igemm_ukernel_4x8__wasmsimd_splat);
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_4X8__WASMSIMD_SPLAT, k_div_4_subtile) {
|
|
for (size_t k = 8; k <= 40; k += 4) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_f32_igemm_ukernel_4x8__wasmsimd_splat);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_4X8__WASMSIMD_SPLAT, n_gt_8) {
|
|
for (uint32_t n = 9; n < 16; n++) {
|
|
for (size_t k = 1; k <= 20; k += 5) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.Test(xnn_f32_igemm_ukernel_4x8__wasmsimd_splat);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_4X8__WASMSIMD_SPLAT, n_gt_8_strided_cn) {
|
|
for (uint32_t n = 9; n < 16; n++) {
|
|
for (size_t k = 1; k <= 20; k += 5) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.cn_stride(11)
|
|
.Test(xnn_f32_igemm_ukernel_4x8__wasmsimd_splat);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_4X8__WASMSIMD_SPLAT, n_gt_8_subtile) {
|
|
for (uint32_t n = 9; n < 16; n++) {
|
|
for (size_t k = 1; k <= 20; k += 5) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_f32_igemm_ukernel_4x8__wasmsimd_splat);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_4X8__WASMSIMD_SPLAT, n_div_8) {
|
|
for (uint32_t n = 16; n <= 24; n += 8) {
|
|
for (size_t k = 1; k <= 20; k += 5) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.Test(xnn_f32_igemm_ukernel_4x8__wasmsimd_splat);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_4X8__WASMSIMD_SPLAT, n_div_8_strided_cn) {
|
|
for (uint32_t n = 16; n <= 24; n += 8) {
|
|
for (size_t k = 1; k <= 20; k += 5) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.cn_stride(11)
|
|
.Test(xnn_f32_igemm_ukernel_4x8__wasmsimd_splat);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_4X8__WASMSIMD_SPLAT, n_div_8_subtile) {
|
|
for (uint32_t n = 16; n <= 24; n += 8) {
|
|
for (size_t k = 1; k <= 20; k += 5) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_f32_igemm_ukernel_4x8__wasmsimd_splat);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_4X8__WASMSIMD_SPLAT, small_kernel) {
|
|
for (size_t k = 1; k <= 20; k += 5) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_f32_igemm_ukernel_4x8__wasmsimd_splat);
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_4X8__WASMSIMD_SPLAT, small_kernel_subtile) {
|
|
for (size_t k = 1; k <= 20; k += 5) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.iterations(1)
|
|
.Test(xnn_f32_igemm_ukernel_4x8__wasmsimd_splat);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_4X8__WASMSIMD_SPLAT, n_gt_8_small_kernel) {
|
|
for (uint32_t n = 9; n < 16; n++) {
|
|
for (size_t k = 1; k <= 20; k += 5) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_f32_igemm_ukernel_4x8__wasmsimd_splat);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_4X8__WASMSIMD_SPLAT, n_div_8_small_kernel) {
|
|
for (uint32_t n = 16; n <= 24; n += 8) {
|
|
for (size_t k = 1; k <= 20; k += 5) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_f32_igemm_ukernel_4x8__wasmsimd_splat);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_4X8__WASMSIMD_SPLAT, strided_cm_subtile) {
|
|
for (size_t k = 1; k <= 20; k += 5) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.cm_stride(11)
|
|
.iterations(1)
|
|
.Test(xnn_f32_igemm_ukernel_4x8__wasmsimd_splat);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_4X8__WASMSIMD_SPLAT, a_offset) {
|
|
for (size_t k = 1; k <= 20; k += 5) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(k)
|
|
.ks(3)
|
|
.a_offset(83)
|
|
.Test(xnn_f32_igemm_ukernel_4x8__wasmsimd_splat);
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_4X8__WASMSIMD_SPLAT, zero) {
|
|
for (size_t k = 1; k <= 20; k += 5) {
|
|
for (uint32_t mz = 0; mz < 4; mz++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(k)
|
|
.ks(3)
|
|
.a_offset(83)
|
|
.zero_index(mz)
|
|
.Test(xnn_f32_igemm_ukernel_4x8__wasmsimd_splat);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_4X8__WASMSIMD_SPLAT, strided_cm) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(4)
|
|
.cm_stride(11)
|
|
.Test(xnn_f32_igemm_ukernel_4x8__wasmsimd_splat);
|
|
}
|
|
#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
|
|
|
|
|
|
#if XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
|
|
TEST(F32_IGEMM_5X8__WASMSIMD_SPLAT, k_eq_4) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(5)
|
|
.n(8)
|
|
.k(4)
|
|
.Test(xnn_f32_igemm_ukernel_5x8__wasmsimd_splat);
|
|
}
|
|
|
|
TEST(F32_IGEMM_5X8__WASMSIMD_SPLAT, strided_cn) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(5)
|
|
.n(8)
|
|
.k(4)
|
|
.cn_stride(11)
|
|
.Test(xnn_f32_igemm_ukernel_5x8__wasmsimd_splat);
|
|
}
|
|
|
|
TEST(F32_IGEMM_5X8__WASMSIMD_SPLAT, k_eq_4_subtile) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 5; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(4)
|
|
.iterations(1)
|
|
.Test(xnn_f32_igemm_ukernel_5x8__wasmsimd_splat);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_5X8__WASMSIMD_SPLAT, k_eq_4_subtile_m) {
|
|
for (uint32_t m = 1; m <= 5; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(8)
|
|
.k(4)
|
|
.iterations(1)
|
|
.Test(xnn_f32_igemm_ukernel_5x8__wasmsimd_splat);
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_5X8__WASMSIMD_SPLAT, k_eq_4_subtile_n) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(5)
|
|
.n(n)
|
|
.k(4)
|
|
.iterations(1)
|
|
.Test(xnn_f32_igemm_ukernel_5x8__wasmsimd_splat);
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_5X8__WASMSIMD_SPLAT, k_lt_4) {
|
|
for (size_t k = 1; k < 4; k++) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(5)
|
|
.n(8)
|
|
.k(k)
|
|
.Test(xnn_f32_igemm_ukernel_5x8__wasmsimd_splat);
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_5X8__WASMSIMD_SPLAT, k_lt_4_subtile) {
|
|
for (size_t k = 1; k < 4; k++) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 5; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_f32_igemm_ukernel_5x8__wasmsimd_splat);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_5X8__WASMSIMD_SPLAT, k_gt_4) {
|
|
for (size_t k = 5; k < 8; k++) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(5)
|
|
.n(8)
|
|
.k(k)
|
|
.Test(xnn_f32_igemm_ukernel_5x8__wasmsimd_splat);
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_5X8__WASMSIMD_SPLAT, k_gt_4_subtile) {
|
|
for (size_t k = 5; k < 8; k++) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 5; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_f32_igemm_ukernel_5x8__wasmsimd_splat);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_5X8__WASMSIMD_SPLAT, k_div_4) {
|
|
for (size_t k = 8; k <= 40; k += 4) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(5)
|
|
.n(8)
|
|
.k(k)
|
|
.Test(xnn_f32_igemm_ukernel_5x8__wasmsimd_splat);
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_5X8__WASMSIMD_SPLAT, k_div_4_subtile) {
|
|
for (size_t k = 8; k <= 40; k += 4) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 5; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_f32_igemm_ukernel_5x8__wasmsimd_splat);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_5X8__WASMSIMD_SPLAT, n_gt_8) {
|
|
for (uint32_t n = 9; n < 16; n++) {
|
|
for (size_t k = 1; k <= 20; k += 5) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(5)
|
|
.n(n)
|
|
.k(k)
|
|
.Test(xnn_f32_igemm_ukernel_5x8__wasmsimd_splat);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_5X8__WASMSIMD_SPLAT, n_gt_8_strided_cn) {
|
|
for (uint32_t n = 9; n < 16; n++) {
|
|
for (size_t k = 1; k <= 20; k += 5) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(5)
|
|
.n(n)
|
|
.k(k)
|
|
.cn_stride(11)
|
|
.Test(xnn_f32_igemm_ukernel_5x8__wasmsimd_splat);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_5X8__WASMSIMD_SPLAT, n_gt_8_subtile) {
|
|
for (uint32_t n = 9; n < 16; n++) {
|
|
for (size_t k = 1; k <= 20; k += 5) {
|
|
for (uint32_t m = 1; m <= 5; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_f32_igemm_ukernel_5x8__wasmsimd_splat);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_5X8__WASMSIMD_SPLAT, n_div_8) {
|
|
for (uint32_t n = 16; n <= 24; n += 8) {
|
|
for (size_t k = 1; k <= 20; k += 5) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(5)
|
|
.n(n)
|
|
.k(k)
|
|
.Test(xnn_f32_igemm_ukernel_5x8__wasmsimd_splat);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_5X8__WASMSIMD_SPLAT, n_div_8_strided_cn) {
|
|
for (uint32_t n = 16; n <= 24; n += 8) {
|
|
for (size_t k = 1; k <= 20; k += 5) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(5)
|
|
.n(n)
|
|
.k(k)
|
|
.cn_stride(11)
|
|
.Test(xnn_f32_igemm_ukernel_5x8__wasmsimd_splat);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_5X8__WASMSIMD_SPLAT, n_div_8_subtile) {
|
|
for (uint32_t n = 16; n <= 24; n += 8) {
|
|
for (size_t k = 1; k <= 20; k += 5) {
|
|
for (uint32_t m = 1; m <= 5; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_f32_igemm_ukernel_5x8__wasmsimd_splat);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_5X8__WASMSIMD_SPLAT, small_kernel) {
|
|
for (size_t k = 1; k <= 20; k += 5) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(5)
|
|
.n(8)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_f32_igemm_ukernel_5x8__wasmsimd_splat);
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_5X8__WASMSIMD_SPLAT, small_kernel_subtile) {
|
|
for (size_t k = 1; k <= 20; k += 5) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 5; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.iterations(1)
|
|
.Test(xnn_f32_igemm_ukernel_5x8__wasmsimd_splat);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_5X8__WASMSIMD_SPLAT, n_gt_8_small_kernel) {
|
|
for (uint32_t n = 9; n < 16; n++) {
|
|
for (size_t k = 1; k <= 20; k += 5) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(5)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_f32_igemm_ukernel_5x8__wasmsimd_splat);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_5X8__WASMSIMD_SPLAT, n_div_8_small_kernel) {
|
|
for (uint32_t n = 16; n <= 24; n += 8) {
|
|
for (size_t k = 1; k <= 20; k += 5) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(5)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_f32_igemm_ukernel_5x8__wasmsimd_splat);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_5X8__WASMSIMD_SPLAT, strided_cm_subtile) {
|
|
for (size_t k = 1; k <= 20; k += 5) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 5; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.cm_stride(11)
|
|
.iterations(1)
|
|
.Test(xnn_f32_igemm_ukernel_5x8__wasmsimd_splat);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_5X8__WASMSIMD_SPLAT, a_offset) {
|
|
for (size_t k = 1; k <= 20; k += 5) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(5)
|
|
.n(8)
|
|
.k(k)
|
|
.ks(3)
|
|
.a_offset(103)
|
|
.Test(xnn_f32_igemm_ukernel_5x8__wasmsimd_splat);
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_5X8__WASMSIMD_SPLAT, zero) {
|
|
for (size_t k = 1; k <= 20; k += 5) {
|
|
for (uint32_t mz = 0; mz < 5; mz++) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(5)
|
|
.n(8)
|
|
.k(k)
|
|
.ks(3)
|
|
.a_offset(103)
|
|
.zero_index(mz)
|
|
.Test(xnn_f32_igemm_ukernel_5x8__wasmsimd_splat);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_5X8__WASMSIMD_SPLAT, strided_cm) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(5)
|
|
.n(8)
|
|
.k(4)
|
|
.cm_stride(11)
|
|
.Test(xnn_f32_igemm_ukernel_5x8__wasmsimd_splat);
|
|
}
|
|
#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
|
|
|
|
|
|
#if XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
|
|
TEST(F32_IGEMM_1X4__WASM, k_eq_1) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(4)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(4)
|
|
.k(1)
|
|
.Test(xnn_f32_igemm_ukernel_1x4__wasm);
|
|
}
|
|
|
|
TEST(F32_IGEMM_1X4__WASM, strided_cn) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(4)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(4)
|
|
.k(1)
|
|
.cn_stride(7)
|
|
.Test(xnn_f32_igemm_ukernel_1x4__wasm);
|
|
}
|
|
|
|
TEST(F32_IGEMM_1X4__WASM, k_eq_1_subtile) {
|
|
for (uint32_t n = 1; n <= 4; n++) {
|
|
for (uint32_t m = 1; m <= 1; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(4)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(1)
|
|
.iterations(1)
|
|
.Test(xnn_f32_igemm_ukernel_1x4__wasm);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_1X4__WASM, k_eq_1_subtile_m) {
|
|
for (uint32_t m = 1; m <= 1; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(4)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(4)
|
|
.k(1)
|
|
.iterations(1)
|
|
.Test(xnn_f32_igemm_ukernel_1x4__wasm);
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_1X4__WASM, k_eq_1_subtile_n) {
|
|
for (uint32_t n = 1; n <= 4; n++) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(4)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(n)
|
|
.k(1)
|
|
.iterations(1)
|
|
.Test(xnn_f32_igemm_ukernel_1x4__wasm);
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_1X4__WASM, k_gt_1) {
|
|
for (size_t k = 2; k < 10; k++) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(4)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(4)
|
|
.k(k)
|
|
.Test(xnn_f32_igemm_ukernel_1x4__wasm);
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_1X4__WASM, k_gt_1_subtile) {
|
|
for (size_t k = 2; k < 10; k++) {
|
|
for (uint32_t n = 1; n <= 4; n++) {
|
|
for (uint32_t m = 1; m <= 1; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(4)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_f32_igemm_ukernel_1x4__wasm);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_1X4__WASM, n_gt_4) {
|
|
for (uint32_t n = 5; n < 8; n++) {
|
|
for (size_t k = 1; k <= 5; k += 2) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(4)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(n)
|
|
.k(k)
|
|
.Test(xnn_f32_igemm_ukernel_1x4__wasm);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_1X4__WASM, n_gt_4_strided_cn) {
|
|
for (uint32_t n = 5; n < 8; n++) {
|
|
for (size_t k = 1; k <= 5; k += 2) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(4)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(n)
|
|
.k(k)
|
|
.cn_stride(7)
|
|
.Test(xnn_f32_igemm_ukernel_1x4__wasm);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_1X4__WASM, n_gt_4_subtile) {
|
|
for (uint32_t n = 5; n < 8; n++) {
|
|
for (size_t k = 1; k <= 5; k += 2) {
|
|
for (uint32_t m = 1; m <= 1; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(4)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_f32_igemm_ukernel_1x4__wasm);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_1X4__WASM, n_div_4) {
|
|
for (uint32_t n = 8; n <= 12; n += 4) {
|
|
for (size_t k = 1; k <= 5; k += 2) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(4)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(n)
|
|
.k(k)
|
|
.Test(xnn_f32_igemm_ukernel_1x4__wasm);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_1X4__WASM, n_div_4_strided_cn) {
|
|
for (uint32_t n = 8; n <= 12; n += 4) {
|
|
for (size_t k = 1; k <= 5; k += 2) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(4)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(n)
|
|
.k(k)
|
|
.cn_stride(7)
|
|
.Test(xnn_f32_igemm_ukernel_1x4__wasm);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_1X4__WASM, n_div_4_subtile) {
|
|
for (uint32_t n = 8; n <= 12; n += 4) {
|
|
for (size_t k = 1; k <= 5; k += 2) {
|
|
for (uint32_t m = 1; m <= 1; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(4)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_f32_igemm_ukernel_1x4__wasm);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_1X4__WASM, small_kernel) {
|
|
for (size_t k = 1; k <= 5; k += 2) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(4)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(4)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_f32_igemm_ukernel_1x4__wasm);
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_1X4__WASM, small_kernel_subtile) {
|
|
for (size_t k = 1; k <= 5; k += 2) {
|
|
for (uint32_t n = 1; n <= 4; n++) {
|
|
for (uint32_t m = 1; m <= 1; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(4)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.iterations(1)
|
|
.Test(xnn_f32_igemm_ukernel_1x4__wasm);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_1X4__WASM, n_gt_4_small_kernel) {
|
|
for (uint32_t n = 5; n < 8; n++) {
|
|
for (size_t k = 1; k <= 5; k += 2) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(4)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_f32_igemm_ukernel_1x4__wasm);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_1X4__WASM, n_div_4_small_kernel) {
|
|
for (uint32_t n = 8; n <= 12; n += 4) {
|
|
for (size_t k = 1; k <= 5; k += 2) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(4)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_f32_igemm_ukernel_1x4__wasm);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_1X4__WASM, strided_cm_subtile) {
|
|
for (size_t k = 1; k <= 5; k += 2) {
|
|
for (uint32_t n = 1; n <= 4; n++) {
|
|
for (uint32_t m = 1; m <= 1; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(4)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.cm_stride(7)
|
|
.iterations(1)
|
|
.Test(xnn_f32_igemm_ukernel_1x4__wasm);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_1X4__WASM, a_offset) {
|
|
for (size_t k = 1; k <= 5; k += 2) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(4)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(4)
|
|
.k(k)
|
|
.ks(3)
|
|
.a_offset(7)
|
|
.Test(xnn_f32_igemm_ukernel_1x4__wasm);
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_1X4__WASM, zero) {
|
|
for (size_t k = 1; k <= 5; k += 2) {
|
|
for (uint32_t mz = 0; mz < 1; mz++) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(4)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(4)
|
|
.k(k)
|
|
.ks(3)
|
|
.a_offset(7)
|
|
.zero_index(mz)
|
|
.Test(xnn_f32_igemm_ukernel_1x4__wasm);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_1X4__WASM, strided_cm) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(4)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(4)
|
|
.k(1)
|
|
.cm_stride(7)
|
|
.Test(xnn_f32_igemm_ukernel_1x4__wasm);
|
|
}
|
|
#endif // XNN_ARCH_WASM || XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
|
|
|
|
|
|
TEST(F32_IGEMM_2X4__SCALAR, k_eq_1) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(4)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(4)
|
|
.k(1)
|
|
.Test(xnn_f32_igemm_ukernel_2x4__scalar);
|
|
}
|
|
|
|
TEST(F32_IGEMM_2X4__SCALAR, strided_cn) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(4)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(4)
|
|
.k(1)
|
|
.cn_stride(7)
|
|
.Test(xnn_f32_igemm_ukernel_2x4__scalar);
|
|
}
|
|
|
|
TEST(F32_IGEMM_2X4__SCALAR, k_eq_1_subtile) {
|
|
for (uint32_t n = 1; n <= 4; n++) {
|
|
for (uint32_t m = 1; m <= 2; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(4)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(1)
|
|
.iterations(1)
|
|
.Test(xnn_f32_igemm_ukernel_2x4__scalar);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_2X4__SCALAR, k_eq_1_subtile_m) {
|
|
for (uint32_t m = 1; m <= 2; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(4)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(4)
|
|
.k(1)
|
|
.iterations(1)
|
|
.Test(xnn_f32_igemm_ukernel_2x4__scalar);
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_2X4__SCALAR, k_eq_1_subtile_n) {
|
|
for (uint32_t n = 1; n <= 4; n++) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(4)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(n)
|
|
.k(1)
|
|
.iterations(1)
|
|
.Test(xnn_f32_igemm_ukernel_2x4__scalar);
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_2X4__SCALAR, k_gt_1) {
|
|
for (size_t k = 2; k < 10; k++) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(4)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(4)
|
|
.k(k)
|
|
.Test(xnn_f32_igemm_ukernel_2x4__scalar);
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_2X4__SCALAR, k_gt_1_subtile) {
|
|
for (size_t k = 2; k < 10; k++) {
|
|
for (uint32_t n = 1; n <= 4; n++) {
|
|
for (uint32_t m = 1; m <= 2; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(4)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_f32_igemm_ukernel_2x4__scalar);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_2X4__SCALAR, n_gt_4) {
|
|
for (uint32_t n = 5; n < 8; n++) {
|
|
for (size_t k = 1; k <= 5; k += 2) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(4)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(n)
|
|
.k(k)
|
|
.Test(xnn_f32_igemm_ukernel_2x4__scalar);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_2X4__SCALAR, n_gt_4_strided_cn) {
|
|
for (uint32_t n = 5; n < 8; n++) {
|
|
for (size_t k = 1; k <= 5; k += 2) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(4)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(n)
|
|
.k(k)
|
|
.cn_stride(7)
|
|
.Test(xnn_f32_igemm_ukernel_2x4__scalar);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_2X4__SCALAR, n_gt_4_subtile) {
|
|
for (uint32_t n = 5; n < 8; n++) {
|
|
for (size_t k = 1; k <= 5; k += 2) {
|
|
for (uint32_t m = 1; m <= 2; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(4)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_f32_igemm_ukernel_2x4__scalar);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_2X4__SCALAR, n_div_4) {
|
|
for (uint32_t n = 8; n <= 12; n += 4) {
|
|
for (size_t k = 1; k <= 5; k += 2) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(4)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(n)
|
|
.k(k)
|
|
.Test(xnn_f32_igemm_ukernel_2x4__scalar);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_2X4__SCALAR, n_div_4_strided_cn) {
|
|
for (uint32_t n = 8; n <= 12; n += 4) {
|
|
for (size_t k = 1; k <= 5; k += 2) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(4)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(n)
|
|
.k(k)
|
|
.cn_stride(7)
|
|
.Test(xnn_f32_igemm_ukernel_2x4__scalar);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_2X4__SCALAR, n_div_4_subtile) {
|
|
for (uint32_t n = 8; n <= 12; n += 4) {
|
|
for (size_t k = 1; k <= 5; k += 2) {
|
|
for (uint32_t m = 1; m <= 2; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(4)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_f32_igemm_ukernel_2x4__scalar);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_2X4__SCALAR, small_kernel) {
|
|
for (size_t k = 1; k <= 5; k += 2) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(4)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(4)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_f32_igemm_ukernel_2x4__scalar);
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_2X4__SCALAR, small_kernel_subtile) {
|
|
for (size_t k = 1; k <= 5; k += 2) {
|
|
for (uint32_t n = 1; n <= 4; n++) {
|
|
for (uint32_t m = 1; m <= 2; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(4)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.iterations(1)
|
|
.Test(xnn_f32_igemm_ukernel_2x4__scalar);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_2X4__SCALAR, n_gt_4_small_kernel) {
|
|
for (uint32_t n = 5; n < 8; n++) {
|
|
for (size_t k = 1; k <= 5; k += 2) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(4)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_f32_igemm_ukernel_2x4__scalar);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_2X4__SCALAR, n_div_4_small_kernel) {
|
|
for (uint32_t n = 8; n <= 12; n += 4) {
|
|
for (size_t k = 1; k <= 5; k += 2) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(4)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_f32_igemm_ukernel_2x4__scalar);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_2X4__SCALAR, strided_cm_subtile) {
|
|
for (size_t k = 1; k <= 5; k += 2) {
|
|
for (uint32_t n = 1; n <= 4; n++) {
|
|
for (uint32_t m = 1; m <= 2; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(4)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.cm_stride(7)
|
|
.iterations(1)
|
|
.Test(xnn_f32_igemm_ukernel_2x4__scalar);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_2X4__SCALAR, a_offset) {
|
|
for (size_t k = 1; k <= 5; k += 2) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(4)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(4)
|
|
.k(k)
|
|
.ks(3)
|
|
.a_offset(13)
|
|
.Test(xnn_f32_igemm_ukernel_2x4__scalar);
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_2X4__SCALAR, zero) {
|
|
for (size_t k = 1; k <= 5; k += 2) {
|
|
for (uint32_t mz = 0; mz < 2; mz++) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(4)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(4)
|
|
.k(k)
|
|
.ks(3)
|
|
.a_offset(13)
|
|
.zero_index(mz)
|
|
.Test(xnn_f32_igemm_ukernel_2x4__scalar);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(F32_IGEMM_2X4__SCALAR, strided_cm) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(4)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(4)
|
|
.k(1)
|
|
.cm_stride(7)
|
|
.Test(xnn_f32_igemm_ukernel_2x4__scalar);
|
|
}
|