10364 lines
294 KiB
C++
10364 lines
294 KiB
C++
// Copyright (c) Facebook, Inc. and its affiliates.
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// All rights reserved.
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//
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// Copyright 2019 Google LLC
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//
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// This source code is licensed under the BSD-style license found in the
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// LICENSE file in the root directory of this source tree.
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//
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// Auto-generated file. Do not edit!
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// Specification: test/qu8-igemm-minmax-rndnu.yaml
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// Generator: tools/generate-gemm-test.py
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#include <gtest/gtest.h>
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#include <xnnpack/allocator.h>
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#include <xnnpack/common.h>
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#include <xnnpack/isa-checks.h>
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#include <xnnpack/gemm.h>
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#include <xnnpack/igemm.h>
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#include <xnnpack/ppmm.h>
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#include "gemm-microkernel-tester.h"
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#if XNN_ARCH_ARM && XNN_ENABLE_ASSEMBLY
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TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_PRFM_LD64, k_eq_8) {
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TEST_REQUIRES_ARM_NEON;
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GemmMicrokernelTester()
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.mr(4)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(4)
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.n(8)
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.k(8)
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.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
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}
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TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_PRFM_LD64, strided_cn) {
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TEST_REQUIRES_ARM_NEON;
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GemmMicrokernelTester()
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.mr(4)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(4)
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.n(8)
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.k(8)
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.cn_stride(11)
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.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
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}
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TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_PRFM_LD64, k_eq_8_subtile) {
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TEST_REQUIRES_ARM_NEON;
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for (uint32_t n = 1; n <= 8; n++) {
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for (uint32_t m = 1; m <= 4; m++) {
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GemmMicrokernelTester()
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.mr(4)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(m)
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.n(n)
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.k(8)
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.iterations(1)
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.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
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}
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}
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}
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TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_PRFM_LD64, k_eq_8_subtile_m) {
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TEST_REQUIRES_ARM_NEON;
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for (uint32_t m = 1; m <= 4; m++) {
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GemmMicrokernelTester()
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.mr(4)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(m)
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.n(8)
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.k(8)
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.iterations(1)
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.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
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}
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}
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TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_PRFM_LD64, k_eq_8_subtile_n) {
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TEST_REQUIRES_ARM_NEON;
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for (uint32_t n = 1; n <= 8; n++) {
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GemmMicrokernelTester()
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.mr(4)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(4)
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.n(n)
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.k(8)
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.iterations(1)
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.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
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}
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}
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TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_PRFM_LD64, k_lt_8) {
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TEST_REQUIRES_ARM_NEON;
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for (size_t k = 1; k < 8; k++) {
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GemmMicrokernelTester()
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.mr(4)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(4)
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.n(8)
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.k(k)
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.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
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}
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}
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TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_PRFM_LD64, k_lt_8_subtile) {
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TEST_REQUIRES_ARM_NEON;
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for (size_t k = 1; k < 8; k++) {
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for (uint32_t n = 1; n <= 8; n++) {
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for (uint32_t m = 1; m <= 4; m++) {
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GemmMicrokernelTester()
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.mr(4)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(m)
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.n(n)
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.k(k)
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.iterations(1)
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.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
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}
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}
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}
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}
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TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_PRFM_LD64, k_gt_8) {
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TEST_REQUIRES_ARM_NEON;
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for (size_t k = 9; k < 16; k++) {
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GemmMicrokernelTester()
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.mr(4)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(4)
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.n(8)
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.k(k)
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.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
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}
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}
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TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_PRFM_LD64, k_gt_8_subtile) {
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TEST_REQUIRES_ARM_NEON;
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for (size_t k = 9; k < 16; k++) {
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for (uint32_t n = 1; n <= 8; n++) {
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for (uint32_t m = 1; m <= 4; m++) {
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GemmMicrokernelTester()
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.mr(4)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(m)
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.n(n)
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.k(k)
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.iterations(1)
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.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
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}
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}
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}
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}
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TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_PRFM_LD64, k_div_8) {
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TEST_REQUIRES_ARM_NEON;
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for (size_t k = 16; k <= 80; k += 8) {
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GemmMicrokernelTester()
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.mr(4)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(4)
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.n(8)
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.k(k)
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.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
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}
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}
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TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_PRFM_LD64, k_div_8_subtile) {
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TEST_REQUIRES_ARM_NEON;
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for (size_t k = 16; k <= 80; k += 8) {
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for (uint32_t n = 1; n <= 8; n++) {
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for (uint32_t m = 1; m <= 4; m++) {
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GemmMicrokernelTester()
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.mr(4)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(m)
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.n(n)
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.k(k)
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.iterations(1)
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.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
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}
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}
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}
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}
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TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_PRFM_LD64, n_gt_8) {
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TEST_REQUIRES_ARM_NEON;
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for (uint32_t n = 9; n < 16; n++) {
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for (size_t k = 1; k <= 40; k += 9) {
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GemmMicrokernelTester()
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.mr(4)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(4)
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.n(n)
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.k(k)
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.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
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}
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}
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}
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TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_PRFM_LD64, n_gt_8_strided_cn) {
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TEST_REQUIRES_ARM_NEON;
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for (uint32_t n = 9; n < 16; n++) {
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for (size_t k = 1; k <= 40; k += 9) {
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GemmMicrokernelTester()
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.mr(4)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(4)
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.n(n)
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.k(k)
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.cn_stride(11)
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.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
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}
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}
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}
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TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_PRFM_LD64, n_gt_8_subtile) {
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TEST_REQUIRES_ARM_NEON;
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for (uint32_t n = 9; n < 16; n++) {
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for (size_t k = 1; k <= 40; k += 9) {
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for (uint32_t m = 1; m <= 4; m++) {
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GemmMicrokernelTester()
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.mr(4)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(m)
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.n(n)
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.k(k)
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.iterations(1)
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.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
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}
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}
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}
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}
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TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_PRFM_LD64, n_div_8) {
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TEST_REQUIRES_ARM_NEON;
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for (uint32_t n = 16; n <= 24; n += 8) {
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for (size_t k = 1; k <= 40; k += 9) {
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GemmMicrokernelTester()
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.mr(4)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(4)
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.n(n)
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.k(k)
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.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
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}
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}
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}
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TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_PRFM_LD64, n_div_8_strided_cn) {
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TEST_REQUIRES_ARM_NEON;
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for (uint32_t n = 16; n <= 24; n += 8) {
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for (size_t k = 1; k <= 40; k += 9) {
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GemmMicrokernelTester()
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.mr(4)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(4)
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.n(n)
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.k(k)
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.cn_stride(11)
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.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
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}
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}
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}
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TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_PRFM_LD64, n_div_8_subtile) {
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TEST_REQUIRES_ARM_NEON;
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for (uint32_t n = 16; n <= 24; n += 8) {
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for (size_t k = 1; k <= 40; k += 9) {
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for (uint32_t m = 1; m <= 4; m++) {
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GemmMicrokernelTester()
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.mr(4)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(m)
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.n(n)
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.k(k)
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.iterations(1)
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.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
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}
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}
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}
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}
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TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_PRFM_LD64, small_kernel) {
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TEST_REQUIRES_ARM_NEON;
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for (size_t k = 1; k <= 40; k += 9) {
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GemmMicrokernelTester()
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.mr(4)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(4)
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.n(8)
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.k(k)
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.ks(3)
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.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
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}
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}
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TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_PRFM_LD64, small_kernel_subtile) {
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TEST_REQUIRES_ARM_NEON;
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for (size_t k = 1; k <= 40; k += 9) {
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for (uint32_t n = 1; n <= 8; n++) {
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for (uint32_t m = 1; m <= 4; m++) {
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GemmMicrokernelTester()
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.mr(4)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(m)
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.n(n)
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.k(k)
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.ks(3)
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.iterations(1)
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.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
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}
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}
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}
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}
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TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_PRFM_LD64, n_gt_8_small_kernel) {
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TEST_REQUIRES_ARM_NEON;
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for (uint32_t n = 9; n < 16; n++) {
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for (size_t k = 1; k <= 40; k += 9) {
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GemmMicrokernelTester()
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.mr(4)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(4)
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.n(n)
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.k(k)
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.ks(3)
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.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
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}
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}
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}
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TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_PRFM_LD64, n_div_8_small_kernel) {
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TEST_REQUIRES_ARM_NEON;
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for (uint32_t n = 16; n <= 24; n += 8) {
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for (size_t k = 1; k <= 40; k += 9) {
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GemmMicrokernelTester()
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.mr(4)
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.nr(8)
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.kr(1)
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.sr(1)
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.m(4)
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.n(n)
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.k(k)
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.ks(3)
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.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
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}
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}
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}
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TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_PRFM_LD64, strided_cm_subtile) {
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TEST_REQUIRES_ARM_NEON;
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for (size_t k = 1; k <= 40; k += 9) {
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for (uint32_t n = 1; n <= 8; n++) {
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for (uint32_t m = 1; m <= 4; m++) {
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GemmMicrokernelTester()
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.mr(4)
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.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.cm_stride(11)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_PRFM_LD64, a_offset) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(k)
|
|
.ks(3)
|
|
.a_offset(163)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_PRFM_LD64, zero) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t mz = 0; mz < 4; mz++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(k)
|
|
.ks(3)
|
|
.a_offset(163)
|
|
.zero_index(mz)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_PRFM_LD64, qmin) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(8)
|
|
.qmin(128)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_PRFM_LD64, qmax) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(8)
|
|
.qmax(128)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_PRFM_LD64, strided_cm) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(8)
|
|
.cm_stride(11)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_PRFM_LD64, no_a_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(k)
|
|
.a_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_PRFM_LD64, no_b_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(k)
|
|
.b_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_PRFM_LD64, no_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(k)
|
|
.a_zero_point(0)
|
|
.b_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
#endif // XNN_ARCH_ARM && XNN_ENABLE_ASSEMBLY
|
|
|
|
|
|
#if XNN_ARCH_ARM && XNN_ENABLE_ASSEMBLY
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_LD64, k_eq_8) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(8)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_LD64, strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(8)
|
|
.cn_stride(11)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_LD64, k_eq_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_LD64, k_eq_8_subtile_m) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(8)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_LD64, k_eq_8_subtile_n) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_LD64, k_lt_8) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k < 8; k++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_LD64, k_lt_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k < 8; k++) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_LD64, k_gt_8) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 9; k < 16; k++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_LD64, k_gt_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 9; k < 16; k++) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_LD64, k_div_8) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 16; k <= 80; k += 8) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_LD64, k_div_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 16; k <= 80; k += 8) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_LD64, n_gt_8) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 9; n < 16; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_LD64, n_gt_8_strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 9; n < 16; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.cn_stride(11)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_LD64, n_gt_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 9; n < 16; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_LD64, n_div_8) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 16; n <= 24; n += 8) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_LD64, n_div_8_strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 16; n <= 24; n += 8) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.cn_stride(11)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_LD64, n_div_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 16; n <= 24; n += 8) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_LD64, small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_LD64, small_kernel_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_LD64, n_gt_8_small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 9; n < 16; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_LD64, n_div_8_small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 16; n <= 24; n += 8) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_LD64, strided_cm_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.cm_stride(11)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_LD64, a_offset) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(k)
|
|
.ks(3)
|
|
.a_offset(163)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_LD64, zero) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t mz = 0; mz < 4; mz++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(k)
|
|
.ks(3)
|
|
.a_offset(163)
|
|
.zero_index(mz)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_LD64, qmin) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(8)
|
|
.qmin(128)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_LD64, qmax) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(8)
|
|
.qmax(128)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_LD64, strided_cm) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(8)
|
|
.cm_stride(11)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_LD64, no_a_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(k)
|
|
.a_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_LD64, no_b_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(k)
|
|
.b_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8__AARCH32_NEON_MLAL_LANE_LD64, no_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(k)
|
|
.a_zero_point(0)
|
|
.b_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8__aarch32_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
#endif // XNN_ARCH_ARM && XNN_ENABLE_ASSEMBLY
|
|
|
|
|
|
#if XNN_ARCH_ARM || XNN_ARCH_ARM64
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8__NEON_MLAL_LANE, k_eq_8) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(8)
|
|
.k(8)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8__NEON_MLAL_LANE, strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(8)
|
|
.k(8)
|
|
.cn_stride(11)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8__NEON_MLAL_LANE, k_eq_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 2; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8__NEON_MLAL_LANE, k_eq_8_subtile_m) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t m = 1; m <= 2; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(8)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8__NEON_MLAL_LANE, k_eq_8_subtile_n) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(n)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8__NEON_MLAL_LANE, k_lt_8) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k < 8; k++) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(8)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8__NEON_MLAL_LANE, k_lt_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k < 8; k++) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 2; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8__NEON_MLAL_LANE, k_gt_8) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 9; k < 16; k++) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(8)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8__NEON_MLAL_LANE, k_gt_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 9; k < 16; k++) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 2; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8__NEON_MLAL_LANE, k_div_8) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 16; k <= 80; k += 8) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(8)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8__NEON_MLAL_LANE, k_div_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 16; k <= 80; k += 8) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 2; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8__NEON_MLAL_LANE, n_gt_8) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 9; n < 16; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(n)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8__NEON_MLAL_LANE, n_gt_8_strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 9; n < 16; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(n)
|
|
.k(k)
|
|
.cn_stride(11)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8__NEON_MLAL_LANE, n_gt_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 9; n < 16; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t m = 1; m <= 2; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8__NEON_MLAL_LANE, n_div_8) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 16; n <= 24; n += 8) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(n)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8__NEON_MLAL_LANE, n_div_8_strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 16; n <= 24; n += 8) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(n)
|
|
.k(k)
|
|
.cn_stride(11)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8__NEON_MLAL_LANE, n_div_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 16; n <= 24; n += 8) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t m = 1; m <= 2; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8__NEON_MLAL_LANE, small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(8)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8__NEON_MLAL_LANE, small_kernel_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 2; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8__NEON_MLAL_LANE, n_gt_8_small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 9; n < 16; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8__NEON_MLAL_LANE, n_div_8_small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 16; n <= 24; n += 8) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8__NEON_MLAL_LANE, strided_cm_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 2; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.cm_stride(11)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8__NEON_MLAL_LANE, a_offset) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(8)
|
|
.k(k)
|
|
.ks(3)
|
|
.a_offset(83)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8__NEON_MLAL_LANE, zero) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t mz = 0; mz < 2; mz++) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(8)
|
|
.k(k)
|
|
.ks(3)
|
|
.a_offset(83)
|
|
.zero_index(mz)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8__NEON_MLAL_LANE, qmin) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(8)
|
|
.k(8)
|
|
.qmin(128)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8__NEON_MLAL_LANE, qmax) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(8)
|
|
.k(8)
|
|
.qmax(128)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8__NEON_MLAL_LANE, strided_cm) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(8)
|
|
.k(8)
|
|
.cm_stride(11)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8__NEON_MLAL_LANE, no_a_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(8)
|
|
.k(k)
|
|
.a_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8__NEON_MLAL_LANE, no_b_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(8)
|
|
.k(k)
|
|
.b_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8__NEON_MLAL_LANE, no_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(8)
|
|
.k(k)
|
|
.a_zero_point(0)
|
|
.b_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
#endif // XNN_ARCH_ARM || XNN_ARCH_ARM64
|
|
|
|
|
|
#if XNN_ARCH_ARM || XNN_ARCH_ARM64
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8__NEON_MLAL_LANE, k_eq_8) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(3)
|
|
.n(8)
|
|
.k(8)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8__NEON_MLAL_LANE, strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(3)
|
|
.n(8)
|
|
.k(8)
|
|
.cn_stride(11)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8__NEON_MLAL_LANE, k_eq_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 3; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8__NEON_MLAL_LANE, k_eq_8_subtile_m) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t m = 1; m <= 3; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(8)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8__NEON_MLAL_LANE, k_eq_8_subtile_n) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(3)
|
|
.n(n)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8__NEON_MLAL_LANE, k_lt_8) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k < 8; k++) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(3)
|
|
.n(8)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8__NEON_MLAL_LANE, k_lt_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k < 8; k++) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 3; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8__NEON_MLAL_LANE, k_gt_8) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 9; k < 16; k++) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(3)
|
|
.n(8)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8__NEON_MLAL_LANE, k_gt_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 9; k < 16; k++) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 3; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8__NEON_MLAL_LANE, k_div_8) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 16; k <= 80; k += 8) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(3)
|
|
.n(8)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8__NEON_MLAL_LANE, k_div_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 16; k <= 80; k += 8) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 3; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8__NEON_MLAL_LANE, n_gt_8) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 9; n < 16; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(3)
|
|
.n(n)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8__NEON_MLAL_LANE, n_gt_8_strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 9; n < 16; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(3)
|
|
.n(n)
|
|
.k(k)
|
|
.cn_stride(11)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8__NEON_MLAL_LANE, n_gt_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 9; n < 16; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t m = 1; m <= 3; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8__NEON_MLAL_LANE, n_div_8) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 16; n <= 24; n += 8) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(3)
|
|
.n(n)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8__NEON_MLAL_LANE, n_div_8_strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 16; n <= 24; n += 8) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(3)
|
|
.n(n)
|
|
.k(k)
|
|
.cn_stride(11)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8__NEON_MLAL_LANE, n_div_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 16; n <= 24; n += 8) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t m = 1; m <= 3; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8__NEON_MLAL_LANE, small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(3)
|
|
.n(8)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8__NEON_MLAL_LANE, small_kernel_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 3; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8__NEON_MLAL_LANE, n_gt_8_small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 9; n < 16; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(3)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8__NEON_MLAL_LANE, n_div_8_small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 16; n <= 24; n += 8) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(3)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8__NEON_MLAL_LANE, strided_cm_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 3; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.cm_stride(11)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8__NEON_MLAL_LANE, a_offset) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(3)
|
|
.n(8)
|
|
.k(k)
|
|
.ks(3)
|
|
.a_offset(127)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8__NEON_MLAL_LANE, zero) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t mz = 0; mz < 3; mz++) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(3)
|
|
.n(8)
|
|
.k(k)
|
|
.ks(3)
|
|
.a_offset(127)
|
|
.zero_index(mz)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8__NEON_MLAL_LANE, qmin) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(3)
|
|
.n(8)
|
|
.k(8)
|
|
.qmin(128)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8__NEON_MLAL_LANE, qmax) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(3)
|
|
.n(8)
|
|
.k(8)
|
|
.qmax(128)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8__NEON_MLAL_LANE, strided_cm) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(3)
|
|
.n(8)
|
|
.k(8)
|
|
.cm_stride(11)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8__NEON_MLAL_LANE, no_a_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(3)
|
|
.n(8)
|
|
.k(k)
|
|
.a_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8__NEON_MLAL_LANE, no_b_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(3)
|
|
.n(8)
|
|
.k(k)
|
|
.b_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8__NEON_MLAL_LANE, no_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(3)
|
|
.n(8)
|
|
.k(k)
|
|
.a_zero_point(0)
|
|
.b_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
#endif // XNN_ARCH_ARM || XNN_ARCH_ARM64
|
|
|
|
|
|
#if XNN_ARCH_ARM || XNN_ARCH_ARM64
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X8__NEON_MLAL_LANE, k_eq_8) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(8)
|
|
.k(8)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X8__NEON_MLAL_LANE, strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(8)
|
|
.k(8)
|
|
.cn_stride(11)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X8__NEON_MLAL_LANE, k_eq_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 6; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X8__NEON_MLAL_LANE, k_eq_8_subtile_m) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t m = 1; m <= 6; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(8)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X8__NEON_MLAL_LANE, k_eq_8_subtile_n) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(n)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X8__NEON_MLAL_LANE, k_lt_8) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k < 8; k++) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(8)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X8__NEON_MLAL_LANE, k_lt_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k < 8; k++) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 6; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X8__NEON_MLAL_LANE, k_gt_8) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 9; k < 16; k++) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(8)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X8__NEON_MLAL_LANE, k_gt_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 9; k < 16; k++) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 6; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X8__NEON_MLAL_LANE, k_div_8) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 16; k <= 80; k += 8) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(8)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X8__NEON_MLAL_LANE, k_div_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 16; k <= 80; k += 8) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 6; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X8__NEON_MLAL_LANE, n_gt_8) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 9; n < 16; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(n)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X8__NEON_MLAL_LANE, n_gt_8_strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 9; n < 16; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(n)
|
|
.k(k)
|
|
.cn_stride(11)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X8__NEON_MLAL_LANE, n_gt_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 9; n < 16; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t m = 1; m <= 6; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X8__NEON_MLAL_LANE, n_div_8) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 16; n <= 24; n += 8) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(n)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X8__NEON_MLAL_LANE, n_div_8_strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 16; n <= 24; n += 8) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(n)
|
|
.k(k)
|
|
.cn_stride(11)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X8__NEON_MLAL_LANE, n_div_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 16; n <= 24; n += 8) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t m = 1; m <= 6; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X8__NEON_MLAL_LANE, small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(8)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X8__NEON_MLAL_LANE, small_kernel_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 6; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X8__NEON_MLAL_LANE, n_gt_8_small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 9; n < 16; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X8__NEON_MLAL_LANE, n_div_8_small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 16; n <= 24; n += 8) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X8__NEON_MLAL_LANE, strided_cm_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 6; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.cm_stride(11)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X8__NEON_MLAL_LANE, a_offset) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(8)
|
|
.k(k)
|
|
.ks(3)
|
|
.a_offset(251)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X8__NEON_MLAL_LANE, zero) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t mz = 0; mz < 6; mz++) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(8)
|
|
.k(k)
|
|
.ks(3)
|
|
.a_offset(251)
|
|
.zero_index(mz)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X8__NEON_MLAL_LANE, qmin) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(8)
|
|
.k(8)
|
|
.qmin(128)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X8__NEON_MLAL_LANE, qmax) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(8)
|
|
.k(8)
|
|
.qmax(128)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X8__NEON_MLAL_LANE, strided_cm) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(8)
|
|
.k(8)
|
|
.cm_stride(11)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X8__NEON_MLAL_LANE, no_a_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(8)
|
|
.k(k)
|
|
.a_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X8__NEON_MLAL_LANE, no_b_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(8)
|
|
.k(k)
|
|
.b_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X8__NEON_MLAL_LANE, no_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(8)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(8)
|
|
.k(k)
|
|
.a_zero_point(0)
|
|
.b_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x8__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
#endif // XNN_ARCH_ARM || XNN_ARCH_ARM64
|
|
|
|
|
|
#if XNN_ARCH_ARM || XNN_ARCH_ARM64
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__NEON_MLAL_LANE, k_eq_8) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(8)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__NEON_MLAL_LANE, strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(8)
|
|
.cn_stride(19)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__NEON_MLAL_LANE, k_eq_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__NEON_MLAL_LANE, k_eq_8_subtile_m) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(16)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__NEON_MLAL_LANE, k_eq_8_subtile_n) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__NEON_MLAL_LANE, k_lt_8) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k < 8; k++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__NEON_MLAL_LANE, k_lt_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k < 8; k++) {
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__NEON_MLAL_LANE, k_gt_8) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 9; k < 16; k++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__NEON_MLAL_LANE, k_gt_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 9; k < 16; k++) {
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__NEON_MLAL_LANE, k_div_8) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 16; k <= 80; k += 8) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__NEON_MLAL_LANE, k_div_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 16; k <= 80; k += 8) {
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__NEON_MLAL_LANE, n_gt_16) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 17; n < 32; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__NEON_MLAL_LANE, n_gt_16_strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 17; n < 32; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.cn_stride(19)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__NEON_MLAL_LANE, n_gt_16_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 17; n < 32; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__NEON_MLAL_LANE, n_div_16) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 32; n <= 48; n += 16) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__NEON_MLAL_LANE, n_div_16_strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 32; n <= 48; n += 16) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.cn_stride(19)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__NEON_MLAL_LANE, n_div_16_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 32; n <= 48; n += 16) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__NEON_MLAL_LANE, small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__NEON_MLAL_LANE, small_kernel_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__NEON_MLAL_LANE, n_gt_16_small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 17; n < 32; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__NEON_MLAL_LANE, n_div_16_small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 32; n <= 48; n += 16) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__NEON_MLAL_LANE, strided_cm_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.cm_stride(19)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__NEON_MLAL_LANE, a_offset) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(k)
|
|
.ks(3)
|
|
.a_offset(163)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__NEON_MLAL_LANE, zero) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t mz = 0; mz < 4; mz++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(k)
|
|
.ks(3)
|
|
.a_offset(163)
|
|
.zero_index(mz)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__NEON_MLAL_LANE, qmin) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(8)
|
|
.qmin(128)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__NEON_MLAL_LANE, qmax) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(8)
|
|
.qmax(128)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__NEON_MLAL_LANE, strided_cm) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(8)
|
|
.cm_stride(19)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__NEON_MLAL_LANE, no_a_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(k)
|
|
.a_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__NEON_MLAL_LANE, no_b_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(k)
|
|
.b_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__NEON_MLAL_LANE, no_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(k)
|
|
.a_zero_point(0)
|
|
.b_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
#endif // XNN_ARCH_ARM || XNN_ARCH_ARM64
|
|
|
|
|
|
#if XNN_ARCH_ARM || XNN_ARCH_ARM64
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16__NEON_MLAL_LANE, k_eq_8) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(16)
|
|
.k(8)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16__NEON_MLAL_LANE, strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(16)
|
|
.k(8)
|
|
.cn_stride(19)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16__NEON_MLAL_LANE, k_eq_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
for (uint32_t m = 1; m <= 6; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16__NEON_MLAL_LANE, k_eq_8_subtile_m) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t m = 1; m <= 6; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(16)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16__NEON_MLAL_LANE, k_eq_8_subtile_n) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(n)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16__NEON_MLAL_LANE, k_lt_8) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k < 8; k++) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(16)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16__NEON_MLAL_LANE, k_lt_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k < 8; k++) {
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
for (uint32_t m = 1; m <= 6; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16__NEON_MLAL_LANE, k_gt_8) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 9; k < 16; k++) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(16)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16__NEON_MLAL_LANE, k_gt_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 9; k < 16; k++) {
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
for (uint32_t m = 1; m <= 6; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16__NEON_MLAL_LANE, k_div_8) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 16; k <= 80; k += 8) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(16)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16__NEON_MLAL_LANE, k_div_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 16; k <= 80; k += 8) {
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
for (uint32_t m = 1; m <= 6; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16__NEON_MLAL_LANE, n_gt_16) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 17; n < 32; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(n)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16__NEON_MLAL_LANE, n_gt_16_strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 17; n < 32; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(n)
|
|
.k(k)
|
|
.cn_stride(19)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16__NEON_MLAL_LANE, n_gt_16_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 17; n < 32; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t m = 1; m <= 6; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16__NEON_MLAL_LANE, n_div_16) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 32; n <= 48; n += 16) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(n)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16__NEON_MLAL_LANE, n_div_16_strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 32; n <= 48; n += 16) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(n)
|
|
.k(k)
|
|
.cn_stride(19)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16__NEON_MLAL_LANE, n_div_16_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 32; n <= 48; n += 16) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t m = 1; m <= 6; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16__NEON_MLAL_LANE, small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(16)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16__NEON_MLAL_LANE, small_kernel_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
for (uint32_t m = 1; m <= 6; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16__NEON_MLAL_LANE, n_gt_16_small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 17; n < 32; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16__NEON_MLAL_LANE, n_div_16_small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 32; n <= 48; n += 16) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16__NEON_MLAL_LANE, strided_cm_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
for (uint32_t m = 1; m <= 6; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.cm_stride(19)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16__NEON_MLAL_LANE, a_offset) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(16)
|
|
.k(k)
|
|
.ks(3)
|
|
.a_offset(251)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16__NEON_MLAL_LANE, zero) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t mz = 0; mz < 6; mz++) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(16)
|
|
.k(k)
|
|
.ks(3)
|
|
.a_offset(251)
|
|
.zero_index(mz)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16__NEON_MLAL_LANE, qmin) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(16)
|
|
.k(8)
|
|
.qmin(128)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16__NEON_MLAL_LANE, qmax) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(16)
|
|
.k(8)
|
|
.qmax(128)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16__NEON_MLAL_LANE, strided_cm) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(16)
|
|
.k(8)
|
|
.cm_stride(19)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16__NEON_MLAL_LANE, no_a_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(16)
|
|
.k(k)
|
|
.a_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16__NEON_MLAL_LANE, no_b_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(16)
|
|
.k(k)
|
|
.b_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16__NEON_MLAL_LANE, no_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(16)
|
|
.k(k)
|
|
.a_zero_point(0)
|
|
.b_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16__neon_mlal_lane, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
#endif // XNN_ARCH_ARM || XNN_ARCH_ARM64
|
|
|
|
|
|
#if XNN_ARCH_ARM64 && XNN_ENABLE_ASSEMBLY
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_CORTEX_A55, k_eq_8) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(8)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_cortex_a55, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_CORTEX_A55, strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(8)
|
|
.cn_stride(11)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_cortex_a55, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_CORTEX_A55, k_eq_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_cortex_a55, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_CORTEX_A55, k_eq_8_subtile_m) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(8)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_cortex_a55, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_CORTEX_A55, k_eq_8_subtile_n) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_cortex_a55, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_CORTEX_A55, k_lt_8) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k < 8; k++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_cortex_a55, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_CORTEX_A55, k_lt_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k < 8; k++) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_cortex_a55, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_CORTEX_A55, k_gt_8) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 9; k < 16; k++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_cortex_a55, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_CORTEX_A55, k_gt_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 9; k < 16; k++) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_cortex_a55, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_CORTEX_A55, k_div_8) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 16; k <= 80; k += 8) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_cortex_a55, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_CORTEX_A55, k_div_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 16; k <= 80; k += 8) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_cortex_a55, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_CORTEX_A55, n_gt_8) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 9; n < 16; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_cortex_a55, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_CORTEX_A55, n_gt_8_strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 9; n < 16; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.cn_stride(11)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_cortex_a55, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_CORTEX_A55, n_gt_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 9; n < 16; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_cortex_a55, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_CORTEX_A55, n_div_8) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 16; n <= 24; n += 8) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_cortex_a55, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_CORTEX_A55, n_div_8_strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 16; n <= 24; n += 8) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.cn_stride(11)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_cortex_a55, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_CORTEX_A55, n_div_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 16; n <= 24; n += 8) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_cortex_a55, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_CORTEX_A55, small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_cortex_a55, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_CORTEX_A55, small_kernel_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_cortex_a55, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_CORTEX_A55, n_gt_8_small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 9; n < 16; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_cortex_a55, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_CORTEX_A55, n_div_8_small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 16; n <= 24; n += 8) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_cortex_a55, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_CORTEX_A55, strided_cm_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.cm_stride(11)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_cortex_a55, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_CORTEX_A55, a_offset) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(k)
|
|
.ks(3)
|
|
.a_offset(163)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_cortex_a55, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_CORTEX_A55, zero) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t mz = 0; mz < 4; mz++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(k)
|
|
.ks(3)
|
|
.a_offset(163)
|
|
.zero_index(mz)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_cortex_a55, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_CORTEX_A55, qmin) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(8)
|
|
.qmin(128)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_cortex_a55, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_CORTEX_A55, qmax) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(8)
|
|
.qmax(128)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_cortex_a55, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_CORTEX_A55, strided_cm) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(8)
|
|
.cm_stride(11)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_cortex_a55, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_CORTEX_A55, no_a_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(k)
|
|
.a_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_cortex_a55, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_CORTEX_A55, no_b_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(k)
|
|
.b_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_cortex_a55, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_CORTEX_A55, no_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(k)
|
|
.a_zero_point(0)
|
|
.b_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_cortex_a55, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
#endif // XNN_ARCH_ARM64 && XNN_ENABLE_ASSEMBLY
|
|
|
|
|
|
#if XNN_ARCH_ARM64 && XNN_ENABLE_ASSEMBLY
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_LD128, k_eq_16) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(16)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_ld128, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_LD128, strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(16)
|
|
.cn_stride(11)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_ld128, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_LD128, k_eq_16_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(16)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_ld128, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_LD128, k_eq_16_subtile_m) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(8)
|
|
.k(16)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_ld128, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_LD128, k_eq_16_subtile_n) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(16)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_ld128, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_LD128, k_lt_16) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k < 16; k++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_ld128, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_LD128, k_lt_16_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k < 16; k++) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_ld128, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_LD128, k_gt_16) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 17; k < 32; k++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_ld128, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_LD128, k_gt_16_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 17; k < 32; k++) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_ld128, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_LD128, k_div_16) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 32; k <= 160; k += 16) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_ld128, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_LD128, k_div_16_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 32; k <= 160; k += 16) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_ld128, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_LD128, n_gt_8) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 9; n < 16; n++) {
|
|
for (size_t k = 1; k <= 80; k += 17) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_ld128, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_LD128, n_gt_8_strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 9; n < 16; n++) {
|
|
for (size_t k = 1; k <= 80; k += 17) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.cn_stride(11)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_ld128, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_LD128, n_gt_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 9; n < 16; n++) {
|
|
for (size_t k = 1; k <= 80; k += 17) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_ld128, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_LD128, n_div_8) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 16; n <= 24; n += 8) {
|
|
for (size_t k = 1; k <= 80; k += 17) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_ld128, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_LD128, n_div_8_strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 16; n <= 24; n += 8) {
|
|
for (size_t k = 1; k <= 80; k += 17) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.cn_stride(11)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_ld128, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_LD128, n_div_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 16; n <= 24; n += 8) {
|
|
for (size_t k = 1; k <= 80; k += 17) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_ld128, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_LD128, small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 80; k += 17) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_ld128, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_LD128, small_kernel_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 80; k += 17) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_ld128, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_LD128, n_gt_8_small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 9; n < 16; n++) {
|
|
for (size_t k = 1; k <= 80; k += 17) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_ld128, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_LD128, n_div_8_small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 16; n <= 24; n += 8) {
|
|
for (size_t k = 1; k <= 80; k += 17) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_ld128, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_LD128, strided_cm_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 80; k += 17) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.cm_stride(11)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_ld128, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_LD128, a_offset) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 80; k += 17) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(k)
|
|
.ks(3)
|
|
.a_offset(331)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_ld128, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_LD128, zero) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 80; k += 17) {
|
|
for (uint32_t mz = 0; mz < 4; mz++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(k)
|
|
.ks(3)
|
|
.a_offset(331)
|
|
.zero_index(mz)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_ld128, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_LD128, qmin) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(16)
|
|
.qmin(128)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_ld128, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_LD128, qmax) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(16)
|
|
.qmax(128)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_ld128, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_LD128, strided_cm) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(16)
|
|
.cm_stride(11)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_ld128, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_LD128, no_a_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 80; k += 17) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(k)
|
|
.a_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_ld128, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_LD128, no_b_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 80; k += 17) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(k)
|
|
.b_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_ld128, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__AARCH64_NEONDOT_LD128, no_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 80; k += 17) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(k)
|
|
.a_zero_point(0)
|
|
.b_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__aarch64_neondot_ld128, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
#endif // XNN_ARCH_ARM64 && XNN_ENABLE_ASSEMBLY
|
|
|
|
|
|
#if XNN_ARCH_ARM && !XNN_PLATFORM_IOS || XNN_ARCH_ARM64
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8C4__NEONDOT, k_eq_8) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(8)
|
|
.k(8)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8C4__NEONDOT, strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(8)
|
|
.k(8)
|
|
.cn_stride(11)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8C4__NEONDOT, k_eq_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 2; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8C4__NEONDOT, k_eq_8_subtile_m) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t m = 1; m <= 2; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(8)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8C4__NEONDOT, k_eq_8_subtile_n) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(n)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8C4__NEONDOT, k_lt_8) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k < 8; k++) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(8)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8C4__NEONDOT, k_lt_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k < 8; k++) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 2; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8C4__NEONDOT, k_gt_8) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 9; k < 16; k++) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(8)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8C4__NEONDOT, k_gt_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 9; k < 16; k++) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 2; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8C4__NEONDOT, k_div_8) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 16; k <= 80; k += 8) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(8)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8C4__NEONDOT, k_div_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 16; k <= 80; k += 8) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 2; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8C4__NEONDOT, n_gt_8) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 9; n < 16; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(n)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8C4__NEONDOT, n_gt_8_strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 9; n < 16; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(n)
|
|
.k(k)
|
|
.cn_stride(11)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8C4__NEONDOT, n_gt_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 9; n < 16; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t m = 1; m <= 2; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8C4__NEONDOT, n_div_8) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 16; n <= 24; n += 8) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(n)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8C4__NEONDOT, n_div_8_strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 16; n <= 24; n += 8) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(n)
|
|
.k(k)
|
|
.cn_stride(11)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8C4__NEONDOT, n_div_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 16; n <= 24; n += 8) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t m = 1; m <= 2; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8C4__NEONDOT, small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(8)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8C4__NEONDOT, small_kernel_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 2; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8C4__NEONDOT, n_gt_8_small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 9; n < 16; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8C4__NEONDOT, n_div_8_small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 16; n <= 24; n += 8) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8C4__NEONDOT, strided_cm_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 2; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.cm_stride(11)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8C4__NEONDOT, a_offset) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(8)
|
|
.k(k)
|
|
.ks(3)
|
|
.a_offset(83)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8C4__NEONDOT, zero) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t mz = 0; mz < 2; mz++) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(8)
|
|
.k(k)
|
|
.ks(3)
|
|
.a_offset(83)
|
|
.zero_index(mz)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8C4__NEONDOT, qmin) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(8)
|
|
.k(8)
|
|
.qmin(128)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8C4__NEONDOT, qmax) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(8)
|
|
.k(8)
|
|
.qmax(128)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8C4__NEONDOT, strided_cm) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(8)
|
|
.k(8)
|
|
.cm_stride(11)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8C4__NEONDOT, no_a_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(8)
|
|
.k(k)
|
|
.a_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8C4__NEONDOT, no_b_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(8)
|
|
.k(k)
|
|
.b_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_2X8C4__NEONDOT, no_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(2)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(2)
|
|
.n(8)
|
|
.k(k)
|
|
.a_zero_point(0)
|
|
.b_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_2x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
#endif // XNN_ARCH_ARM && !XNN_PLATFORM_IOS || XNN_ARCH_ARM64
|
|
|
|
|
|
#if XNN_ARCH_ARM && !XNN_PLATFORM_IOS || XNN_ARCH_ARM64
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8C4__NEONDOT, k_eq_8) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(3)
|
|
.n(8)
|
|
.k(8)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8C4__NEONDOT, strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(3)
|
|
.n(8)
|
|
.k(8)
|
|
.cn_stride(11)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8C4__NEONDOT, k_eq_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 3; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8C4__NEONDOT, k_eq_8_subtile_m) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t m = 1; m <= 3; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(8)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8C4__NEONDOT, k_eq_8_subtile_n) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(3)
|
|
.n(n)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8C4__NEONDOT, k_lt_8) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k < 8; k++) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(3)
|
|
.n(8)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8C4__NEONDOT, k_lt_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k < 8; k++) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 3; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8C4__NEONDOT, k_gt_8) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 9; k < 16; k++) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(3)
|
|
.n(8)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8C4__NEONDOT, k_gt_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 9; k < 16; k++) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 3; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8C4__NEONDOT, k_div_8) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 16; k <= 80; k += 8) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(3)
|
|
.n(8)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8C4__NEONDOT, k_div_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 16; k <= 80; k += 8) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 3; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8C4__NEONDOT, n_gt_8) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 9; n < 16; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(3)
|
|
.n(n)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8C4__NEONDOT, n_gt_8_strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 9; n < 16; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(3)
|
|
.n(n)
|
|
.k(k)
|
|
.cn_stride(11)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8C4__NEONDOT, n_gt_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 9; n < 16; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t m = 1; m <= 3; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8C4__NEONDOT, n_div_8) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 16; n <= 24; n += 8) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(3)
|
|
.n(n)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8C4__NEONDOT, n_div_8_strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 16; n <= 24; n += 8) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(3)
|
|
.n(n)
|
|
.k(k)
|
|
.cn_stride(11)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8C4__NEONDOT, n_div_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 16; n <= 24; n += 8) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t m = 1; m <= 3; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8C4__NEONDOT, small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(3)
|
|
.n(8)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8C4__NEONDOT, small_kernel_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 3; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8C4__NEONDOT, n_gt_8_small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 9; n < 16; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(3)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8C4__NEONDOT, n_div_8_small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 16; n <= 24; n += 8) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(3)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8C4__NEONDOT, strided_cm_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 3; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.cm_stride(11)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8C4__NEONDOT, a_offset) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(3)
|
|
.n(8)
|
|
.k(k)
|
|
.ks(3)
|
|
.a_offset(127)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8C4__NEONDOT, zero) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t mz = 0; mz < 3; mz++) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(3)
|
|
.n(8)
|
|
.k(k)
|
|
.ks(3)
|
|
.a_offset(127)
|
|
.zero_index(mz)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8C4__NEONDOT, qmin) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(3)
|
|
.n(8)
|
|
.k(8)
|
|
.qmin(128)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8C4__NEONDOT, qmax) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(3)
|
|
.n(8)
|
|
.k(8)
|
|
.qmax(128)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8C4__NEONDOT, strided_cm) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(3)
|
|
.n(8)
|
|
.k(8)
|
|
.cm_stride(11)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8C4__NEONDOT, no_a_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(3)
|
|
.n(8)
|
|
.k(k)
|
|
.a_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8C4__NEONDOT, no_b_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(3)
|
|
.n(8)
|
|
.k(k)
|
|
.b_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_3X8C4__NEONDOT, no_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(3)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(3)
|
|
.n(8)
|
|
.k(k)
|
|
.a_zero_point(0)
|
|
.b_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_3x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
#endif // XNN_ARCH_ARM && !XNN_PLATFORM_IOS || XNN_ARCH_ARM64
|
|
|
|
|
|
#if XNN_ARCH_ARM && !XNN_PLATFORM_IOS || XNN_ARCH_ARM64
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__NEONDOT, k_eq_8) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(8)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__NEONDOT, strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(8)
|
|
.cn_stride(11)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__NEONDOT, k_eq_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__NEONDOT, k_eq_8_subtile_m) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(8)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__NEONDOT, k_eq_8_subtile_n) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__NEONDOT, k_lt_8) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k < 8; k++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__NEONDOT, k_lt_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k < 8; k++) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__NEONDOT, k_gt_8) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 9; k < 16; k++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__NEONDOT, k_gt_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 9; k < 16; k++) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__NEONDOT, k_div_8) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 16; k <= 80; k += 8) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__NEONDOT, k_div_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 16; k <= 80; k += 8) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__NEONDOT, n_gt_8) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 9; n < 16; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__NEONDOT, n_gt_8_strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 9; n < 16; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.cn_stride(11)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__NEONDOT, n_gt_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 9; n < 16; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__NEONDOT, n_div_8) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 16; n <= 24; n += 8) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__NEONDOT, n_div_8_strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 16; n <= 24; n += 8) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.cn_stride(11)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__NEONDOT, n_div_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 16; n <= 24; n += 8) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__NEONDOT, small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__NEONDOT, small_kernel_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__NEONDOT, n_gt_8_small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 9; n < 16; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__NEONDOT, n_div_8_small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 16; n <= 24; n += 8) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__NEONDOT, strided_cm_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.cm_stride(11)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__NEONDOT, a_offset) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(k)
|
|
.ks(3)
|
|
.a_offset(163)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__NEONDOT, zero) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t mz = 0; mz < 4; mz++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(k)
|
|
.ks(3)
|
|
.a_offset(163)
|
|
.zero_index(mz)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__NEONDOT, qmin) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(8)
|
|
.qmin(128)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__NEONDOT, qmax) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(8)
|
|
.qmax(128)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__NEONDOT, strided_cm) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(8)
|
|
.cm_stride(11)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__NEONDOT, no_a_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(k)
|
|
.a_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__NEONDOT, no_b_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(k)
|
|
.b_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X8C4__NEONDOT, no_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(8)
|
|
.k(k)
|
|
.a_zero_point(0)
|
|
.b_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
#endif // XNN_ARCH_ARM && !XNN_PLATFORM_IOS || XNN_ARCH_ARM64
|
|
|
|
|
|
#if XNN_ARCH_ARM && !XNN_PLATFORM_IOS || XNN_ARCH_ARM64
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_5X8C4__NEONDOT, k_eq_8) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(5)
|
|
.n(8)
|
|
.k(8)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_5x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_5X8C4__NEONDOT, strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(5)
|
|
.n(8)
|
|
.k(8)
|
|
.cn_stride(11)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_5x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_5X8C4__NEONDOT, k_eq_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 5; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_5x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_5X8C4__NEONDOT, k_eq_8_subtile_m) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t m = 1; m <= 5; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(8)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_5x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_5X8C4__NEONDOT, k_eq_8_subtile_n) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(5)
|
|
.n(n)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_5x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_5X8C4__NEONDOT, k_lt_8) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k < 8; k++) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(5)
|
|
.n(8)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_5x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_5X8C4__NEONDOT, k_lt_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k < 8; k++) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 5; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_5x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_5X8C4__NEONDOT, k_gt_8) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 9; k < 16; k++) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(5)
|
|
.n(8)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_5x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_5X8C4__NEONDOT, k_gt_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 9; k < 16; k++) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 5; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_5x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_5X8C4__NEONDOT, k_div_8) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 16; k <= 80; k += 8) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(5)
|
|
.n(8)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_5x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_5X8C4__NEONDOT, k_div_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 16; k <= 80; k += 8) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 5; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_5x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_5X8C4__NEONDOT, n_gt_8) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 9; n < 16; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(5)
|
|
.n(n)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_5x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_5X8C4__NEONDOT, n_gt_8_strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 9; n < 16; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(5)
|
|
.n(n)
|
|
.k(k)
|
|
.cn_stride(11)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_5x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_5X8C4__NEONDOT, n_gt_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 9; n < 16; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t m = 1; m <= 5; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_5x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_5X8C4__NEONDOT, n_div_8) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 16; n <= 24; n += 8) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(5)
|
|
.n(n)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_5x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_5X8C4__NEONDOT, n_div_8_strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 16; n <= 24; n += 8) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(5)
|
|
.n(n)
|
|
.k(k)
|
|
.cn_stride(11)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_5x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_5X8C4__NEONDOT, n_div_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 16; n <= 24; n += 8) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t m = 1; m <= 5; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_5x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_5X8C4__NEONDOT, small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(5)
|
|
.n(8)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_5x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_5X8C4__NEONDOT, small_kernel_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 5; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_5x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_5X8C4__NEONDOT, n_gt_8_small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 9; n < 16; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(5)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_5x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_5X8C4__NEONDOT, n_div_8_small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 16; n <= 24; n += 8) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(5)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_5x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_5X8C4__NEONDOT, strided_cm_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t n = 1; n <= 8; n++) {
|
|
for (uint32_t m = 1; m <= 5; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.cm_stride(11)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_5x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_5X8C4__NEONDOT, a_offset) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(5)
|
|
.n(8)
|
|
.k(k)
|
|
.ks(3)
|
|
.a_offset(211)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_5x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_5X8C4__NEONDOT, zero) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t mz = 0; mz < 5; mz++) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(5)
|
|
.n(8)
|
|
.k(k)
|
|
.ks(3)
|
|
.a_offset(211)
|
|
.zero_index(mz)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_5x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_5X8C4__NEONDOT, qmin) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(5)
|
|
.n(8)
|
|
.k(8)
|
|
.qmin(128)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_5x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_5X8C4__NEONDOT, qmax) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(5)
|
|
.n(8)
|
|
.k(8)
|
|
.qmax(128)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_5x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_5X8C4__NEONDOT, strided_cm) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(5)
|
|
.n(8)
|
|
.k(8)
|
|
.cm_stride(11)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_5x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_5X8C4__NEONDOT, no_a_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(5)
|
|
.n(8)
|
|
.k(k)
|
|
.a_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_5x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_5X8C4__NEONDOT, no_b_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(5)
|
|
.n(8)
|
|
.k(k)
|
|
.b_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_5x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_5X8C4__NEONDOT, no_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(5)
|
|
.nr(8)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(5)
|
|
.n(8)
|
|
.k(k)
|
|
.a_zero_point(0)
|
|
.b_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_5x8c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
#endif // XNN_ARCH_ARM && !XNN_PLATFORM_IOS || XNN_ARCH_ARM64
|
|
|
|
|
|
#if XNN_ARCH_ARM && !XNN_PLATFORM_IOS || XNN_ARCH_ARM64
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X16C4__NEONDOT, k_eq_8) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(16)
|
|
.k(8)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X16C4__NEONDOT, strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(16)
|
|
.k(8)
|
|
.cn_stride(19)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X16C4__NEONDOT, k_eq_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
for (uint32_t m = 1; m <= 1; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X16C4__NEONDOT, k_eq_8_subtile_m) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t m = 1; m <= 1; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(16)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X16C4__NEONDOT, k_eq_8_subtile_n) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(n)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X16C4__NEONDOT, k_lt_8) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k < 8; k++) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(16)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X16C4__NEONDOT, k_lt_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k < 8; k++) {
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
for (uint32_t m = 1; m <= 1; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X16C4__NEONDOT, k_gt_8) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 9; k < 16; k++) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(16)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X16C4__NEONDOT, k_gt_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 9; k < 16; k++) {
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
for (uint32_t m = 1; m <= 1; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X16C4__NEONDOT, k_div_8) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 16; k <= 80; k += 8) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(16)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X16C4__NEONDOT, k_div_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 16; k <= 80; k += 8) {
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
for (uint32_t m = 1; m <= 1; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X16C4__NEONDOT, n_gt_16) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 17; n < 32; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(n)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X16C4__NEONDOT, n_gt_16_strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 17; n < 32; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(n)
|
|
.k(k)
|
|
.cn_stride(19)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X16C4__NEONDOT, n_gt_16_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 17; n < 32; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t m = 1; m <= 1; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X16C4__NEONDOT, n_div_16) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 32; n <= 48; n += 16) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(n)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X16C4__NEONDOT, n_div_16_strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 32; n <= 48; n += 16) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(n)
|
|
.k(k)
|
|
.cn_stride(19)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X16C4__NEONDOT, n_div_16_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 32; n <= 48; n += 16) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t m = 1; m <= 1; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X16C4__NEONDOT, small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(16)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X16C4__NEONDOT, small_kernel_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
for (uint32_t m = 1; m <= 1; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X16C4__NEONDOT, n_gt_16_small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 17; n < 32; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X16C4__NEONDOT, n_div_16_small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 32; n <= 48; n += 16) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X16C4__NEONDOT, strided_cm_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
for (uint32_t m = 1; m <= 1; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.cm_stride(19)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X16C4__NEONDOT, a_offset) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(16)
|
|
.k(k)
|
|
.ks(3)
|
|
.a_offset(43)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X16C4__NEONDOT, zero) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t mz = 0; mz < 1; mz++) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(16)
|
|
.k(k)
|
|
.ks(3)
|
|
.a_offset(43)
|
|
.zero_index(mz)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X16C4__NEONDOT, qmin) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(16)
|
|
.k(8)
|
|
.qmin(128)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X16C4__NEONDOT, qmax) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(16)
|
|
.k(8)
|
|
.qmax(128)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X16C4__NEONDOT, strided_cm) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(16)
|
|
.k(8)
|
|
.cm_stride(19)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X16C4__NEONDOT, no_a_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(16)
|
|
.k(k)
|
|
.a_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X16C4__NEONDOT, no_b_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(16)
|
|
.k(k)
|
|
.b_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X16C4__NEONDOT, no_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(16)
|
|
.k(k)
|
|
.a_zero_point(0)
|
|
.b_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
#endif // XNN_ARCH_ARM && !XNN_PLATFORM_IOS || XNN_ARCH_ARM64
|
|
|
|
|
|
#if XNN_ARCH_ARM && !XNN_PLATFORM_IOS || XNN_ARCH_ARM64
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16C4__NEONDOT, k_eq_8) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(16)
|
|
.k(8)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16C4__NEONDOT, strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(16)
|
|
.k(8)
|
|
.cn_stride(19)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16C4__NEONDOT, k_eq_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
for (uint32_t m = 1; m <= 6; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16C4__NEONDOT, k_eq_8_subtile_m) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t m = 1; m <= 6; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(16)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16C4__NEONDOT, k_eq_8_subtile_n) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(n)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16C4__NEONDOT, k_lt_8) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k < 8; k++) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(16)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16C4__NEONDOT, k_lt_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k < 8; k++) {
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
for (uint32_t m = 1; m <= 6; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16C4__NEONDOT, k_gt_8) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 9; k < 16; k++) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(16)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16C4__NEONDOT, k_gt_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 9; k < 16; k++) {
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
for (uint32_t m = 1; m <= 6; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16C4__NEONDOT, k_div_8) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 16; k <= 80; k += 8) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(16)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16C4__NEONDOT, k_div_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 16; k <= 80; k += 8) {
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
for (uint32_t m = 1; m <= 6; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16C4__NEONDOT, n_gt_16) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 17; n < 32; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(n)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16C4__NEONDOT, n_gt_16_strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 17; n < 32; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(n)
|
|
.k(k)
|
|
.cn_stride(19)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16C4__NEONDOT, n_gt_16_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 17; n < 32; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t m = 1; m <= 6; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16C4__NEONDOT, n_div_16) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 32; n <= 48; n += 16) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(n)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16C4__NEONDOT, n_div_16_strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 32; n <= 48; n += 16) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(n)
|
|
.k(k)
|
|
.cn_stride(19)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16C4__NEONDOT, n_div_16_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 32; n <= 48; n += 16) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t m = 1; m <= 6; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16C4__NEONDOT, small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(16)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16C4__NEONDOT, small_kernel_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
for (uint32_t m = 1; m <= 6; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16C4__NEONDOT, n_gt_16_small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 17; n < 32; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16C4__NEONDOT, n_div_16_small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 32; n <= 48; n += 16) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16C4__NEONDOT, strided_cm_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
for (uint32_t m = 1; m <= 6; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.cm_stride(19)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16C4__NEONDOT, a_offset) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(16)
|
|
.k(k)
|
|
.ks(3)
|
|
.a_offset(251)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16C4__NEONDOT, zero) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t mz = 0; mz < 6; mz++) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(16)
|
|
.k(k)
|
|
.ks(3)
|
|
.a_offset(251)
|
|
.zero_index(mz)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16C4__NEONDOT, qmin) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(16)
|
|
.k(8)
|
|
.qmin(128)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16C4__NEONDOT, qmax) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(16)
|
|
.k(8)
|
|
.qmax(128)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16C4__NEONDOT, strided_cm) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(16)
|
|
.k(8)
|
|
.cm_stride(19)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16C4__NEONDOT, no_a_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(16)
|
|
.k(k)
|
|
.a_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16C4__NEONDOT, no_b_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(16)
|
|
.k(k)
|
|
.b_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_6X16C4__NEONDOT, no_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(6)
|
|
.nr(16)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(6)
|
|
.n(16)
|
|
.k(k)
|
|
.a_zero_point(0)
|
|
.b_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_6x16c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
#endif // XNN_ARCH_ARM && !XNN_PLATFORM_IOS || XNN_ARCH_ARM64
|
|
|
|
|
|
#if XNN_ARCH_ARM && !XNN_PLATFORM_IOS || XNN_ARCH_ARM64
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X32C4__NEONDOT, k_eq_8) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(32)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(32)
|
|
.k(8)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x32c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X32C4__NEONDOT, strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(32)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(32)
|
|
.k(8)
|
|
.cn_stride(37)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x32c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X32C4__NEONDOT, k_eq_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 1; n <= 32; n++) {
|
|
for (uint32_t m = 1; m <= 1; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(32)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x32c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X32C4__NEONDOT, k_eq_8_subtile_m) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t m = 1; m <= 1; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(32)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(32)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x32c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X32C4__NEONDOT, k_eq_8_subtile_n) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 1; n <= 32; n++) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(32)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(n)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x32c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X32C4__NEONDOT, k_lt_8) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k < 8; k++) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(32)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(32)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x32c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X32C4__NEONDOT, k_lt_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k < 8; k++) {
|
|
for (uint32_t n = 1; n <= 32; n++) {
|
|
for (uint32_t m = 1; m <= 1; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(32)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x32c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X32C4__NEONDOT, k_gt_8) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 9; k < 16; k++) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(32)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(32)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x32c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X32C4__NEONDOT, k_gt_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 9; k < 16; k++) {
|
|
for (uint32_t n = 1; n <= 32; n++) {
|
|
for (uint32_t m = 1; m <= 1; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(32)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x32c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X32C4__NEONDOT, k_div_8) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 16; k <= 80; k += 8) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(32)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(32)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x32c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X32C4__NEONDOT, k_div_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 16; k <= 80; k += 8) {
|
|
for (uint32_t n = 1; n <= 32; n++) {
|
|
for (uint32_t m = 1; m <= 1; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(32)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x32c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X32C4__NEONDOT, n_gt_32) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 33; n < 64; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(32)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(n)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x32c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X32C4__NEONDOT, n_gt_32_strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 33; n < 64; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(32)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(n)
|
|
.k(k)
|
|
.cn_stride(37)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x32c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X32C4__NEONDOT, n_gt_32_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 33; n < 64; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t m = 1; m <= 1; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(32)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x32c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X32C4__NEONDOT, n_div_32) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 64; n <= 96; n += 32) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(32)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(n)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x32c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X32C4__NEONDOT, n_div_32_strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 64; n <= 96; n += 32) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(32)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(n)
|
|
.k(k)
|
|
.cn_stride(37)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x32c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X32C4__NEONDOT, n_div_32_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 64; n <= 96; n += 32) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t m = 1; m <= 1; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(32)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x32c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X32C4__NEONDOT, small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(32)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(32)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x32c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X32C4__NEONDOT, small_kernel_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t n = 1; n <= 32; n++) {
|
|
for (uint32_t m = 1; m <= 1; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(32)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x32c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X32C4__NEONDOT, n_gt_32_small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 33; n < 64; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(32)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x32c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X32C4__NEONDOT, n_div_32_small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (uint32_t n = 64; n <= 96; n += 32) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(32)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x32c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X32C4__NEONDOT, strided_cm_subtile) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t n = 1; n <= 32; n++) {
|
|
for (uint32_t m = 1; m <= 1; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(32)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.cm_stride(37)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x32c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X32C4__NEONDOT, a_offset) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(32)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(32)
|
|
.k(k)
|
|
.ks(3)
|
|
.a_offset(43)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x32c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X32C4__NEONDOT, zero) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t mz = 0; mz < 1; mz++) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(32)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(32)
|
|
.k(k)
|
|
.ks(3)
|
|
.a_offset(43)
|
|
.zero_index(mz)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x32c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X32C4__NEONDOT, qmin) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(32)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(32)
|
|
.k(8)
|
|
.qmin(128)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x32c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X32C4__NEONDOT, qmax) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(32)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(32)
|
|
.k(8)
|
|
.qmax(128)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x32c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X32C4__NEONDOT, strided_cm) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(32)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(32)
|
|
.k(8)
|
|
.cm_stride(37)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x32c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X32C4__NEONDOT, no_a_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(32)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(32)
|
|
.k(k)
|
|
.a_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x32c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X32C4__NEONDOT, no_b_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(32)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(32)
|
|
.k(k)
|
|
.b_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x32c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_1X32C4__NEONDOT, no_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON_DOT;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(1)
|
|
.nr(32)
|
|
.kr(4)
|
|
.sr(1)
|
|
.m(1)
|
|
.n(32)
|
|
.k(k)
|
|
.a_zero_point(0)
|
|
.b_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_1x32c4__neondot, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
#endif // XNN_ARCH_ARM && !XNN_PLATFORM_IOS || XNN_ARCH_ARM64
|
|
|
|
|
|
#if XNN_ARCH_ARM64 && XNN_ENABLE_ASSEMBLY
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_CORTEX_A75, k_eq_8) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(8)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_cortex_a75, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_CORTEX_A75, strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(8)
|
|
.cn_stride(19)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_cortex_a75, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_CORTEX_A75, k_eq_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_cortex_a75, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_CORTEX_A75, k_eq_8_subtile_m) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(16)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_cortex_a75, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_CORTEX_A75, k_eq_8_subtile_n) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_cortex_a75, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_CORTEX_A75, k_lt_8) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k < 8; k++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_cortex_a75, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_CORTEX_A75, k_lt_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k < 8; k++) {
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_cortex_a75, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_CORTEX_A75, k_gt_8) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 9; k < 16; k++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_cortex_a75, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_CORTEX_A75, k_gt_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 9; k < 16; k++) {
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_cortex_a75, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_CORTEX_A75, k_div_8) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 16; k <= 80; k += 8) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_cortex_a75, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_CORTEX_A75, k_div_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 16; k <= 80; k += 8) {
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_cortex_a75, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_CORTEX_A75, n_gt_16) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 17; n < 32; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_cortex_a75, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_CORTEX_A75, n_gt_16_strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 17; n < 32; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.cn_stride(19)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_cortex_a75, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_CORTEX_A75, n_gt_16_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 17; n < 32; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_cortex_a75, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_CORTEX_A75, n_div_16) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 32; n <= 48; n += 16) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_cortex_a75, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_CORTEX_A75, n_div_16_strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 32; n <= 48; n += 16) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.cn_stride(19)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_cortex_a75, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_CORTEX_A75, n_div_16_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 32; n <= 48; n += 16) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_cortex_a75, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_CORTEX_A75, small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_cortex_a75, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_CORTEX_A75, small_kernel_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_cortex_a75, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_CORTEX_A75, n_gt_16_small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 17; n < 32; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_cortex_a75, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_CORTEX_A75, n_div_16_small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 32; n <= 48; n += 16) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_cortex_a75, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_CORTEX_A75, strided_cm_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.cm_stride(19)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_cortex_a75, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_CORTEX_A75, a_offset) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(k)
|
|
.ks(3)
|
|
.a_offset(163)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_cortex_a75, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_CORTEX_A75, zero) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t mz = 0; mz < 4; mz++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(k)
|
|
.ks(3)
|
|
.a_offset(163)
|
|
.zero_index(mz)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_cortex_a75, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_CORTEX_A75, qmin) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(8)
|
|
.qmin(128)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_cortex_a75, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_CORTEX_A75, qmax) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(8)
|
|
.qmax(128)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_cortex_a75, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_CORTEX_A75, strided_cm) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(8)
|
|
.cm_stride(19)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_cortex_a75, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_CORTEX_A75, no_a_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(k)
|
|
.a_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_cortex_a75, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_CORTEX_A75, no_b_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(k)
|
|
.b_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_cortex_a75, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_CORTEX_A75, no_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(k)
|
|
.a_zero_point(0)
|
|
.b_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_cortex_a75, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
#endif // XNN_ARCH_ARM64 && XNN_ENABLE_ASSEMBLY
|
|
|
|
|
|
#if XNN_ARCH_ARM64 && XNN_ENABLE_ASSEMBLY
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_CORTEX_A53, k_eq_8) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(8)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_cortex_a53, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_CORTEX_A53, strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(8)
|
|
.cn_stride(19)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_cortex_a53, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_CORTEX_A53, k_eq_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_cortex_a53, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_CORTEX_A53, k_eq_8_subtile_m) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(16)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_cortex_a53, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_CORTEX_A53, k_eq_8_subtile_n) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_cortex_a53, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_CORTEX_A53, k_lt_8) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k < 8; k++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_cortex_a53, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_CORTEX_A53, k_lt_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k < 8; k++) {
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_cortex_a53, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_CORTEX_A53, k_gt_8) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 9; k < 16; k++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_cortex_a53, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_CORTEX_A53, k_gt_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 9; k < 16; k++) {
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_cortex_a53, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_CORTEX_A53, k_div_8) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 16; k <= 80; k += 8) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_cortex_a53, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_CORTEX_A53, k_div_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 16; k <= 80; k += 8) {
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_cortex_a53, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_CORTEX_A53, n_gt_16) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 17; n < 32; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_cortex_a53, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_CORTEX_A53, n_gt_16_strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 17; n < 32; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.cn_stride(19)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_cortex_a53, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_CORTEX_A53, n_gt_16_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 17; n < 32; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_cortex_a53, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_CORTEX_A53, n_div_16) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 32; n <= 48; n += 16) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_cortex_a53, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_CORTEX_A53, n_div_16_strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 32; n <= 48; n += 16) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.cn_stride(19)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_cortex_a53, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_CORTEX_A53, n_div_16_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 32; n <= 48; n += 16) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_cortex_a53, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_CORTEX_A53, small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_cortex_a53, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_CORTEX_A53, small_kernel_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_cortex_a53, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_CORTEX_A53, n_gt_16_small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 17; n < 32; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_cortex_a53, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_CORTEX_A53, n_div_16_small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 32; n <= 48; n += 16) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_cortex_a53, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_CORTEX_A53, strided_cm_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.cm_stride(19)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_cortex_a53, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_CORTEX_A53, a_offset) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(k)
|
|
.ks(3)
|
|
.a_offset(163)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_cortex_a53, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_CORTEX_A53, zero) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t mz = 0; mz < 4; mz++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(k)
|
|
.ks(3)
|
|
.a_offset(163)
|
|
.zero_index(mz)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_cortex_a53, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_CORTEX_A53, qmin) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(8)
|
|
.qmin(128)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_cortex_a53, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_CORTEX_A53, qmax) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(8)
|
|
.qmax(128)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_cortex_a53, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_CORTEX_A53, strided_cm) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(8)
|
|
.cm_stride(19)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_cortex_a53, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_CORTEX_A53, no_a_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(k)
|
|
.a_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_cortex_a53, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_CORTEX_A53, no_b_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(k)
|
|
.b_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_cortex_a53, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_CORTEX_A53, no_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(k)
|
|
.a_zero_point(0)
|
|
.b_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_cortex_a53, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
#endif // XNN_ARCH_ARM64 && XNN_ENABLE_ASSEMBLY
|
|
|
|
|
|
#if XNN_ARCH_ARM64 && XNN_ENABLE_ASSEMBLY
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_LD64, k_eq_8) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(8)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_LD64, strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(8)
|
|
.cn_stride(19)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_LD64, k_eq_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_LD64, k_eq_8_subtile_m) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(16)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_LD64, k_eq_8_subtile_n) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_LD64, k_lt_8) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k < 8; k++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_LD64, k_lt_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k < 8; k++) {
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_LD64, k_gt_8) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 9; k < 16; k++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_LD64, k_gt_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 9; k < 16; k++) {
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_LD64, k_div_8) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 16; k <= 80; k += 8) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_LD64, k_div_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 16; k <= 80; k += 8) {
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_LD64, n_gt_16) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 17; n < 32; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_LD64, n_gt_16_strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 17; n < 32; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.cn_stride(19)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_LD64, n_gt_16_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 17; n < 32; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_LD64, n_div_16) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 32; n <= 48; n += 16) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_LD64, n_div_16_strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 32; n <= 48; n += 16) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.cn_stride(19)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_LD64, n_div_16_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 32; n <= 48; n += 16) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_LD64, small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_LD64, small_kernel_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_LD64, n_gt_16_small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 17; n < 32; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_LD64, n_div_16_small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 32; n <= 48; n += 16) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_LD64, strided_cm_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.cm_stride(19)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_LD64, a_offset) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(k)
|
|
.ks(3)
|
|
.a_offset(163)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_LD64, zero) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t mz = 0; mz < 4; mz++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(k)
|
|
.ks(3)
|
|
.a_offset(163)
|
|
.zero_index(mz)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_LD64, qmin) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(8)
|
|
.qmin(128)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_LD64, qmax) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(8)
|
|
.qmax(128)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_LD64, strided_cm) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(8)
|
|
.cm_stride(19)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_LD64, no_a_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(k)
|
|
.a_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_LD64, no_b_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(k)
|
|
.b_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_PRFM_LD64, no_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(k)
|
|
.a_zero_point(0)
|
|
.b_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_prfm_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
#endif // XNN_ARCH_ARM64 && XNN_ENABLE_ASSEMBLY
|
|
|
|
|
|
#if XNN_ARCH_ARM64 && XNN_ENABLE_ASSEMBLY
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_LD64, k_eq_8) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(8)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_LD64, strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(8)
|
|
.cn_stride(19)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_LD64, k_eq_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_LD64, k_eq_8_subtile_m) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(16)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_LD64, k_eq_8_subtile_n) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(8)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_LD64, k_lt_8) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k < 8; k++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_LD64, k_lt_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k < 8; k++) {
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_LD64, k_gt_8) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 9; k < 16; k++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_LD64, k_gt_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 9; k < 16; k++) {
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_LD64, k_div_8) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 16; k <= 80; k += 8) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_LD64, k_div_8_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 16; k <= 80; k += 8) {
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_LD64, n_gt_16) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 17; n < 32; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_LD64, n_gt_16_strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 17; n < 32; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.cn_stride(19)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_LD64, n_gt_16_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 17; n < 32; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_LD64, n_div_16) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 32; n <= 48; n += 16) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_LD64, n_div_16_strided_cn) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 32; n <= 48; n += 16) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.cn_stride(19)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_LD64, n_div_16_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 32; n <= 48; n += 16) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_LD64, small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_LD64, small_kernel_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_LD64, n_gt_16_small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 17; n < 32; n++) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_LD64, n_div_16_small_kernel) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (uint32_t n = 32; n <= 48; n += 16) {
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(n)
|
|
.k(k)
|
|
.ks(3)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_LD64, strided_cm_subtile) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t n = 1; n <= 16; n++) {
|
|
for (uint32_t m = 1; m <= 4; m++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(m)
|
|
.n(n)
|
|
.k(k)
|
|
.cm_stride(19)
|
|
.iterations(1)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_LD64, a_offset) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(k)
|
|
.ks(3)
|
|
.a_offset(163)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_LD64, zero) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
for (uint32_t mz = 0; mz < 4; mz++) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(k)
|
|
.ks(3)
|
|
.a_offset(163)
|
|
.zero_index(mz)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_LD64, qmin) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(8)
|
|
.qmin(128)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_LD64, qmax) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(8)
|
|
.qmax(128)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_LD64, strided_cm) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(8)
|
|
.cm_stride(19)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_LD64, no_a_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(k)
|
|
.a_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_LD64, no_b_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(k)
|
|
.b_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
|
|
TEST(QU8_IGEMM_MINMAX_RNDNU_4X16__AARCH64_NEON_MLAL_LANE_LD64, no_zero_point) {
|
|
TEST_REQUIRES_ARM_NEON;
|
|
for (size_t k = 1; k <= 40; k += 9) {
|
|
GemmMicrokernelTester()
|
|
.mr(4)
|
|
.nr(16)
|
|
.kr(1)
|
|
.sr(1)
|
|
.m(4)
|
|
.n(16)
|
|
.k(k)
|
|
.a_zero_point(0)
|
|
.b_zero_point(0)
|
|
.Test(xnn_qu8_igemm_minmax_rndnu_ukernel_4x16__aarch64_neon_mlal_lane_ld64, xnn_init_qu8_conv_minmax_rndnu_neon_params, xnn_qu8_requantize_rndnu);
|
|
}
|
|
}
|
|
#endif // XNN_ARCH_ARM64 && XNN_ENABLE_ASSEMBLY
|