108 lines
		
	
	
		
			2.4 KiB
		
	
	
	
		
			ArmAsm
		
	
	
	
			
		
		
	
	
			108 lines
		
	
	
		
			2.4 KiB
		
	
	
	
		
			ArmAsm
		
	
	
	
| @/******************************************************************************
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| @ *
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| @ * Copyright (C) 2018 The Android Open Source Project
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| @ *
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| @ * Licensed under the Apache License, Version 2.0 (the "License");
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| @ * you may not use this file except in compliance with the License.
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| @ * You may obtain a copy of the License at:
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| @ *
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| @ * http:@www.apache.org/licenses/LICENSE-2.0
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| @ *
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| @ * Unless required by applicable law or agreed to in writing, software
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| @ * distributed under the License is distributed on an "AS IS" BASIS,
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| @ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| @ * See the License for the specific language governing permissions and
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| @ * limitations under the License.
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| @ *
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| @ *****************************************************************************
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| @ * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore
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| @*/
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| 
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| 
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| .text
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| .p2align 2
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| 
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|     .global ixheaacd_calc_pre_twid_armv7
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| ixheaacd_calc_pre_twid_armv7:
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| 
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|     STMFD           sp!, {r4-r12, r14}
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|     VPUSH           {D8-D15}
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|     LDR             R4, [SP, #104]
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|     LDR             R5, [SP, #108]
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|     ADD             R6, R0, R3, LSL #3
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|     SUB             R6, R6, #12
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|     MOV             R7, #-16
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| 
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| LOOP1:
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|     VLD1.32         {D0, D1}, [R4]!
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|     VLD1.32         {D2, D3}, [R5]!
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|     VLD2.32         {D4, D5}, [R0]!
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|     VLD2.32         {D6, D7}, [R0]!
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|     VLD2.32         {D8, D9}, [R6], R7
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|     VLD2.32         {D10, D11}, [R6], R7
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| 
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|     VREV64.32       D8, D8
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|     VREV64.32       D9, D10
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|     VNEG.S32        D5, D4
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|     VNEG.S32        D7, D6
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| 
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|     VMULL.S32       Q6, D0, D5
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|     VMULL.S32       Q7, D2, D8
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|     VMULL.S32       Q8, D0, D8
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|     VMULL.S32       Q9, D2, D4
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|     VMULL.S32       Q10, D1, D7
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|     VMULL.S32       Q11, D9, D3
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|     VMULL.S32       Q12, D1, D9
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|     VMULL.S32       Q13, D3, D6
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| 
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| 
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|     VSHRN.S64       D12, Q6, #32
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|     VSHRN.S64       D14, Q7, #32
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|     VSHRN.S64       D16, Q8, #32
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|     VSHRN.S64       D18, Q9, #32
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|     VSHRN.S64       D20, Q10, #32
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|     VSHRN.S64       D22, Q11, #32
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|     VSHRN.S64       D24, Q12, #32
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|     VSHRN.S64       D26, Q13, #32
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| 
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|     VSUB.I32        D0, D12, D14
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|     VSUB.I32        D2, D16, D18
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|     VSUB.I32        D1, D20, D22
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|     VSUB.I32        D3, D24, D26
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| 
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|     SUBS            R3, R3, #4
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|     VST1.32         {D0, D1}, [R1]!
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|     VST1.32         {D2, D3}, [R2]!
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| 
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|     BGT             LOOP1
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|     VPOP            {D8-D15}
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|     LDMFD           sp!, {r4-r12, r15}
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