267 lines
5.7 KiB
ArmAsm
267 lines
5.7 KiB
ArmAsm
@/******************************************************************************
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@ *
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@ * Copyright (C) 2018 The Android Open Source Project
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@ *
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@ * Licensed under the Apache License, Version 2.0 (the "License");
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@ * you may not use this file except in compliance with the License.
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@ * You may obtain a copy of the License at:
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@ *
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@ * http://www.apache.org/licenses/LICENSE-2.0
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@ *
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@ * Unless required by applicable law or agreed to in writing, software
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@ * distributed under the License is distributed on an "AS IS" BASIS,
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@ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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@ * See the License for the specific language governing permissions and
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@ * limitations under the License.
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@ *
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@ *****************************************************************************
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@ * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore
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@*/
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.text
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.p2align 2
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.global ixheaacd_sbr_qmfanal32_winadds
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.type ixheaacd_sbr_qmfanal32_winadds, %function
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ixheaacd_sbr_qmfanal32_winadds:
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STMFD sp!, {R4-R12, R14}
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VPUSH {D8 - D15}
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LDR R5, [SP, #108]
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LDR R6, [SP, #112]
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LDR R7, [SP, #116]
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MOV R9, R7, LSL #1
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ADD r5, r5, #64
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MOV r10, #3
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LOOP:
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LDRSH r4 , [R6], r9
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LDRSH r8 , [R6], r9
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LDRSH r11 , [R6], r9
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LDRSH r12 , [R6], r9
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STRH r4 , [r5 , #-2]!
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STRH r8 , [r5 , #-2]!
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STRH r11 , [r5 , #-2]!
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STRH r12 , [r5 , #-2]!
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LDRSH r4 , [R6], r9
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LDRSH r8 , [R6], r9
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LDRSH r11 , [R6], r9
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LDRSH r12 , [R6], r9
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STRH r4 , [r5 , #-2]!
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STRH r8 , [r5 , #-2]!
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STRH r11 , [r5 , #-2]!
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STRH r12 , [r5 , #-2]!
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SUBS r10, r10, #1
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BPL LOOP
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LDR R4, [SP, #104]
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MOV R5, #8
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VLD1.16 D0, [R0]!
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MOV R6, #64
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MOV R6, R6, LSL #1
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VLD2.16 {D1, D2}, [R2]!
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MOV R7, #244
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MOV R9, R0
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ADD R0, R0, #120
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MOV R11, R4
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VLD1.16 D2, [R0], R6
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ADD R11, R11, #128
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MOV R10, R2
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ADD R2, R2, #240
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VMULL.S16 Q15, D0, D1
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VLD2.16 {D3, D4}, [R2]!
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ADD R2, R2, #240
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VLD1.16 D4, [R0], R6
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VMLAL.S16 Q15, D2, D3
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VLD2.16 {D5, D6}, [R2]!
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ADD R2, R2, #240
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VLD1.16 D6, [R0], R6
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VMLAL.S16 Q15, D4, D5
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VLD2.16 {D7, D8}, [R2]!
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ADD R2, R2, #240
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VLD1.16 D8, [R0], R6
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VMLAL.S16 Q15, D6, D7
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MOV R0, R9
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VLD2.16 {D9, D10}, [R2]!
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ADD R2, R2, #240
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VLD1.16 D10, [R1]!
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VMLAL.S16 Q15, D8, D9
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MOV R9, R1
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VLD2.16 {D11, D12}, [R3]!
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ADD R1, R1, #120
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MOV R2, R10
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VLD1.16 D12, [R1], R6
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MOV R10, R3
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ADD R3, R3, #240
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VLD2.16 {D13, D14}, [R3]!
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ADD R3, R3, #240
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VLD2.16 {D15, D16}, [R3]!
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VLD1.16 D14, [R1], R6
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ADD R3, R3, #240
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VLD1.16 D16, [R1], R6
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SUB R5, R5, #1
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VLD2.16 {D17, D18}, [R3]!
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ADD R3, R3, #240
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VLD1.16 D18, [R1], R6
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MOV R1, R9
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VLD2.16 {D19, D20}, [R3]!
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ADD R3, R3, #240
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MOV R3, R10
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LOOP_1:
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VLD1.16 D0, [R0]!
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MOV R9, R0
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VLD2.16 {D1, D2}, [R2]!
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ADD R0, R0, #120
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MOV R10, R2
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VST1.32 {Q15}, [R4]!
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ADD R2, R2, #240
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VMULL.S16 Q15, D10, D11
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VLD1.16 D2, [R0], R6
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VMLAL.S16 Q15, D12, D13
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VMLAL.S16 Q15, D14, D15
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VLD2.16 {D3, D4}, [R2]!
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VMLAL.S16 Q15, D16, D17
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VMLAL.S16 Q15, D18, D19
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VLD1.16 D4, [R0], R6
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ADD R2, R2, #240
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VST1.32 {Q15}, [R11]!
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VMULL.S16 Q15, D0, D1
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VLD2.16 {D5, D6}, [R2]!
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VMLAL.S16 Q15, D2, D3
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ADD R2, R2, #240
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VLD1.16 D6, [R0], R6
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VMLAL.S16 Q15, D4, D5
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VLD2.16 {D7, D8}, [R2]!
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ADD R2, R2, #240
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VLD1.16 D8, [R0], R6
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VMLAL.S16 Q15, D6, D7
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MOV R0, R9
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VLD2.16 {D9, D10}, [R2]!
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ADD R2, R2, #240
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VLD1.16 D10, [R1]!
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MOV R2, R10
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MOV R9, R1
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VLD2.16 {D11, D12}, [R3]!
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ADD R1, R1, #120
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VMLAL.S16 Q15, D8, D9
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VLD1.16 D12, [R1], R6
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MOV R10, R3
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ADD R3, R3, #240
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VLD2.16 {D13, D14}, [R3]!
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ADD R3, R3, #240
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VLD1.16 D14, [R1], R6
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VLD2.16 {D15, D16}, [R3]!
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ADD R3, R3, #240
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VLD1.16 D16, [R1], R6
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VLD2.16 {D17, D18}, [R3]!
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ADD R3, R3, #240
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VLD1.16 D18, [R1], R6
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SUBS R5, R5, #1
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MOV R1, R9
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VLD2.16 {D19, D20}, [R3]!
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ADD R3, R3, #240
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MOV R3, R10
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BGT LOOP_1
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VST1.32 {Q15}, [R4]!
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VMULL.S16 Q15, D10, D11
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VMLAL.S16 Q15, D12, D13
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VMLAL.S16 Q15, D14, D15
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VMLAL.S16 Q15, D16, D17
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VMLAL.S16 Q15, D18, D19
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VST1.32 {Q15}, [R11]!
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VPOP {D8 - D15}
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LDMFD sp!, {R4-R12, R15}
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