306 lines
9.8 KiB
ArmAsm
306 lines
9.8 KiB
ArmAsm
///******************************************************************************
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// *
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// * Copyright (C) 2018 The Android Open Source Project
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// *
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// * Licensed under the Apache License, Version 2.0 (the "License");
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// * you may not use this file except in compliance with the License.
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// * You may obtain a copy of the License at:
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// *
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// * http://www.apache.org/licenses/LICENSE-2.0
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// *
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// * Unless required by applicable law or agreed to in writing, software
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// * distributed under the License is distributed on an "AS IS" BASIS,
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// * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// * See the License for the specific language governing permissions and
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// * limitations under the License.
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// *
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// *****************************************************************************
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// * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore
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//*/
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.macro push_v_regs
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stp q8, q9, [sp, #-32]!
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stp q10, q11, [sp, #-32]!
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stp q12, q13, [sp, #-32]!
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stp q14, q15, [sp, #-32]!
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stp X8, X9, [sp, #-16]!
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stp X10, X11, [sp, #-16]!
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stp X12, X13, [sp, #-16]!
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stp X14, X15, [sp, #-16]!
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stp X16, X17, [sp, #-16]!
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stp X29, X30, [sp, #-16]!
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.endm
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.macro pop_v_regs
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ldp X29, X30, [sp], #16
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ldp X16, X17, [sp], #16
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ldp X14, X15, [sp], #16
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ldp X12, X13, [sp], #16
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ldp X10, X11, [sp], #16
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ldp X8, X9, [sp], #16
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ldp q14, q15, [sp], #32
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ldp q12, q13, [sp], #32
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ldp q10, q11, [sp], #32
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ldp q8, q9, [sp], #32
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.endm
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.text
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.global ixheaacd_over_lap_add2_armv8
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ixheaacd_over_lap_add2_armv8:
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push_v_regs
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MOV X8, X5
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SUB X12, X5, #1
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LSL X9, X5, #2
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LSL X12, X12, #2
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ADD X10, X0, X9
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ADD X7, X1, X12
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ADD X4, X4, #1
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LD2 {V0.4H, V1.4H}, [X10], #16
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LSL X11, X6, #2
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SUB X7, X7, #12
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SUB X4, X4, #16
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MOV X12, #-16
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MOV X13, #1
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ADD X14, X4, #1
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NEG X14, X14
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DUP V21.4S, W4
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LD2 {V6.4H, V7.4H}, [X7], X12
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LSL X4, X13, X14
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REV64 V4.4H, V6.4H
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DUP V20.4S, W4
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REV64 V5.4H, V7.4H
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MOV X4, X3
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MOV X9, X2
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LD2 {V2.4H, V3.4H}, [X3], #16
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UMULL V23.4S, V0.4H, V2.4H
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UMLSL V23.4S, V4.4H, V3.4H
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LD2 {V8.4H, V9.4H}, [X10], #16
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SSHR V23.4S, V23.4S, #16
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LD2 {V10.4H, V11.4H}, [X3], #16
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SMLAL V23.4S, V1.4H, V2.4H
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SMLSL V23.4S, V5.4H, V3.4H
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LD2 {V14.4H, V15.4H}, [X7], X12
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REV64 V12.4H, V14.4H
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REV64 V13.4H, V15.4H
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SQADD V22.4S, V23.4S, V20.4S
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SSHL V22.4S, V22.4S, V21.4S
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MOV V24.16B, V22.16B
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SUB X8, X8, #8
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LOOP_1:
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LD2 {V0.4H, V1.4H}, [X10], #16
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UMULL V19.4S, V8.4H, V10.4H
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LD2 {V2.4H, V3.4H}, [X3], #16
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UMLSL V19.4S, V12.4H, V11.4H
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LD2 {V6.4H, V7.4H}, [X7], X12
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UMULL V23.4S, V0.4H, V2.4H
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REV64 V4.4H, V6.4H
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UMLSL V23.4S, V4.4H, V3.4H
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REV64 V5.4H, V7.4H
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SSHR V19.4S, V19.4S, #16
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ST1 {V24.S}[0], [X2], X11
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SMLAL V19.4S, V9.4H, V10.4H
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ST1 {V24.S}[1], [X2], X11
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SSHR V23.4S, V23.4S, #16
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ST1 {V24.S}[2], [X2], X11
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SMLAL V23.4S, V1.4H, V2.4H
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ST1 {V24.S}[3], [X2], X11
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SMLSL V19.4S, V13.4H, V11.4H
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SMLSL V23.4S, V5.4H, V3.4H
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LD2 {V8.4H, V9.4H}, [X10], #16
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LD2 {V10.4H, V11.4H}, [X3], #16
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LD2 {V14.4H, V15.4H}, [X7], X12
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SQADD V18.4S, V19.4S, V20.4S
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REV64 V12.4H, V14.4H
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REV64 V13.4H, V15.4H
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SQADD V22.4S, V23.4S, V20.4S
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SSHL V18.4S, V18.4S, V21.4S
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MOV V16.16B, V18.16B
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ST1 {V16.S}[0], [X2], X11
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SSHL V22.4S, V22.4S, V21.4S
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MOV V24.16B, V22.16B
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SUBS X8, X8, #8
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ST1 {V16.S}[1], [X2], X11
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ST1 {V16.S}[2], [X2], X11
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ST1 {V16.S}[3], [X2], X11
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BGT LOOP_1
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ST1 {V24.S}[0], [X2], X11
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UMULL V19.4S, V8.4H, V10.4H
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UMLSL V19.4S, V12.4H, V11.4H
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ST1 {V24.S}[1], [X2], X11
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ST1 {V24.S}[2], [X2], X11
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SSHR V19.4S, V19.4S, #16
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ST1 {V24.S}[3], [X2], X11
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SMLAL V19.4S, V9.4H, V10.4H
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SMLSL V19.4S, V13.4H, V11.4H
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MOV X12, #12
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MOV V30.S[0], W5
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MOV V31.S[0], W6
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SMULL V29.4S, V30.4H, V31.4H
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MOV W7, V29.S[0]
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LSL W10, W5, #1
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SQADD V18.4S, V19.4S, V20.4S
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SSHL V18.4S, V18.4S, V21.4S
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MOV V16.16B, V18.16B
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ST1 {V16.S}[0], [X2], X11
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LSL X7, X7, #2
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ST1 {V16.S}[1], [X2], X11
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ADD X7, X7, X9
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ST1 {V16.S}[2], [X2], X11
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ST1 {V16.S}[3], [X2], X11
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SUB X11, X10, #1
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LSL X10, X11, #2
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ADD X10, X0, X10
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LSL X11, X11, #1
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SUB X10, X10, X12
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LSL X8, X6, #2
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MOV X12, #-16
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ADD X11, X11, X4
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LD1 {V6.4S}, [X10], X12
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SUB X11, X11, #14
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REV64 V0.4S, V6.4S
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SQNEG V0.4S, V0.4S
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UZP1 V1.8H, V0.8H, V0.8H
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UZP2 V0.8H, V0.8H, V0.8H
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REV64 V1.4S, V1.4S
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REV64 V0.4S, V0.4S
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LD2 {V2.4H, V3.4H}, [X11], X12
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REV64 V2.4H, V2.4H
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REV64 V3.4H, V3.4H
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LD2 {V4.4H, V5.4H}, [X1], #16
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UMULL V23.4S, V1.4H, V3.4H
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UMLSL V23.4S, V4.4H, V2.4H
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SSHR V23.4S, V23.4S, #16
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SMLAL V23.4S, V0.4H, V3.4H
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SMLSL V23.4S, V5.4H, V2.4H
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SQADD V22.4S, V23.4S, V20.4S
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SSHL V22.4S, V22.4S, V21.4S
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MOV V24.16B, V22.16B
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LD1 {V14.4S}, [X10], X12
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UMULL V23.4S, V1.4H, V3.4H
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UMLSL V23.4S, V4.4H, V2.4H
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REV64 V8.4S, V14.4S
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SQNEG V8.4S, V8.4S
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LD2 {V10.4H, V11.4H}, [X11], X12
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SSHR V23.4S, V23.4S, #16
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LD2 {V12.4H, V13.4H}, [X1], #16
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SMLAL V23.4S, V0.4H, V3.4H
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SMLSL V23.4S, V5.4H, V2.4H
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UZP1 V9.8H, V8.8H, V8.8H
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UZP2 V8.8H, V8.8H, V8.8H
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rev64 v9.4s, v9.4s
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rev64 v8.4s, v8.4s
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REV64 V10.4H, V10.4H
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REV64 V11.4H, V11.4H
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SQADD V22.4S, V23.4S, V20.4S
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SUB X5, X5, #8
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SSHL V22.4S, V22.4S, V21.4S
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MOV V24.16B, V22.16B
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LOOP_2:
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LD1 {V6.4S}, [X10], X12
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UMULL V19.4S, V9.4H, V11.4H
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REV64 V0.4S, V6.4S
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SQNEG V0.4S, V0.4S
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UZP1 V1.8H, V0.8H, V0.8H
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UZP2 V0.8H, V0.8H, V0.8H
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REV64 V1.4S, V1.4S
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REV64 V0.4S, V0.4S
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LD2 {V2.4H, V3.4H}, [X11], X12
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REV64 V2.8H, V2.8H
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REV64 V3.8H, V3.8H
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LD2 {V4.4H, V5.4H}, [X1], #16
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UMLSL V19.4S, V12.4H, V10.4H
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ST1 {V24.S}[0], [X7], X8
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UMULL V23.4S, V1.4H, V3.4H
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ST1 {V24.S}[1], [X7], X8
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SSHR V19.4S, V19.4S, #16
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ST1 {V24.S}[2], [X7], X8
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UMLSL V23.4S, V4.4H, V2.4H
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ST1 {V24.S}[3], [X7], X8
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SMLAL V19.4S, V8.4H, V11.4H
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LD1 {V14.4S}, [X10], X12
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SSHR V23.4S, V23.4S, #16
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SMLSL V19.4S, V13.4H, V10.4H
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LD2 {V10.4H, V11.4H}, [X11], X12
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SMLAL V23.4S, V0.4H, V3.4H
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SMLSL V23.4S, V5.4H, V2.4H
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REV64 V8.4S, V14.4S
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LD2 {V12.4H, V13.4H}, [X1], #16
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SQNEG V8.4S, V8.4S
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REV64 V11.4H, V11.4h
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REV64 V10.4H, V10.4H
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SQADD V18.4S, V19.4S, V20.4S
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UZP1 V9.8H, V8.8H, V8.8H
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UZP2 V8.8H, V8.8H, V8.8H
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rev64 v9.4s, v9.4s
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rev64 v8.4s, v8.4s
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SQADD V22.4S, V23.4S, V20.4S
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SSHL V18.4S, V18.4S, V21.4S
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SUBS X5, X5, #8
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MOV V16.16B, V18.16B
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ST1 {V16.S}[0], [X7], X8
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SSHL V22.4S, V22.4S, V21.4S
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ST1 {V16.S}[1], [X7], X8
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MOV V24.16B, V22.16B
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ST1 {V16.S}[2], [X7], X8
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ST1 {V16.S}[3], [X7], X8
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BGT LOOP_2
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ST1 {V24.S}[0], [X7], X8
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UMULL V19.4S, V9.4H, V11.4H
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UMLSL V19.4S, V12.4H, V10.4H
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ST1 {V24.S}[1], [X7], X8
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ST1 {V24.S}[2], [X7], X8
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SSHR V19.4S, V19.4S, #16
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ST1 {V24.S}[3], [X7], X8
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SMLAL V19.4S, V8.4H, V11.4H
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SMLSL V19.4S, V13.4H, V10.4H
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SQADD V18.4S, V19.4S, V20.4S
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SSHL V18.4S, V18.4S, V21.4S
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MOV V16.16B, V18.16B
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ST1 {V16.S}[0], [X7], X8
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ST1 {V16.S}[1], [X7], X8
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ST1 {V16.S}[2], [X7], X8
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ST1 {V16.S}[3], [X7], X8
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pop_v_regs
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RET
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