70 lines
2.1 KiB
LLVM
70 lines
2.1 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx -x86-experimental-vector-widening-legalization | FileCheck %s
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; Check that we perform a scalar XOR on i32.
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; CHECK: pull_bitcast
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; CHECK: xorl
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; CHECK: ret
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define void @pull_bitcast (<4 x i8>* %pA, <4 x i8>* %pB) {
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%A = load <4 x i8>, <4 x i8>* %pA
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%B = load <4 x i8>, <4 x i8>* %pB
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%C = xor <4 x i8> %A, %B
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store <4 x i8> %C, <4 x i8>* %pA
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ret void
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}
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; CHECK: multi_use_swizzle
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; CHECK: pshufd
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; CHECK-NEXT: pshufd
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; CHECK-NEXT: pblendw
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; CHECK-NEXT: pshufd
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; CHECK-NEXT: pshufd
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; CHECK-NEXT: pxor
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; CHECK-NEXT: ret
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define <4 x i32> @multi_use_swizzle (<4 x i32>* %pA, <4 x i32>* %pB) {
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%A = load <4 x i32>, <4 x i32>* %pA
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%B = load <4 x i32>, <4 x i32>* %pB
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%S = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 1, i32 5, i32 6>
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%S1 = shufflevector <4 x i32> %S, <4 x i32> undef, <4 x i32> <i32 1, i32 3, i32 2, i32 2>
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%S2 = shufflevector <4 x i32> %S, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 2>
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%R = xor <4 x i32> %S1, %S2
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ret <4 x i32> %R
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}
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; CHECK: pull_bitcast2
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; CHECK: xorl
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; CHECK: ret
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define <4 x i8> @pull_bitcast2 (<4 x i8>* %pA, <4 x i8>* %pB, <4 x i8>* %pC) {
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%A = load <4 x i8>, <4 x i8>* %pA
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store <4 x i8> %A, <4 x i8>* %pC
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%B = load <4 x i8>, <4 x i8>* %pB
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%C = xor <4 x i8> %A, %B
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store <4 x i8> %C, <4 x i8>* %pA
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ret <4 x i8> %C
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}
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; CHECK: reverse_1
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; CHECK-NOT: pshufd
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; CHECK: ret
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define <4 x i32> @reverse_1 (<4 x i32>* %pA, <4 x i32>* %pB) {
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%A = load <4 x i32>, <4 x i32>* %pA
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%B = load <4 x i32>, <4 x i32>* %pB
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%S = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
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%S1 = shufflevector <4 x i32> %S, <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
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ret <4 x i32> %S1
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}
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; CHECK: no_reverse_shuff
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; CHECK: pshufd
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; CHECK: ret
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define <4 x i32> @no_reverse_shuff (<4 x i32>* %pA, <4 x i32>* %pB) {
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%A = load <4 x i32>, <4 x i32>* %pA
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%B = load <4 x i32>, <4 x i32>* %pB
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%S = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
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%S1 = shufflevector <4 x i32> %S, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 3, i32 2>
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ret <4 x i32> %S1
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}
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