217 lines
5.4 KiB
LLVM
217 lines
5.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -fast-isel -mtriple=i686-unknown-unknown -mattr=+tbm | FileCheck %s --check-prefix=X32
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; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+tbm | FileCheck %s --check-prefix=X64
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; NOTE: This should use IR equivalent to what is generated by clang/test/CodeGen/tbm-builtins.c
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define i32 @test__bextri_u32(i32 %a0) {
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; X32-LABEL: test__bextri_u32:
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; X32: # BB#0:
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; X32-NEXT: bextr $1, {{[0-9]+}}(%esp), %eax
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; X32-NEXT: retl
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;
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; X64-LABEL: test__bextri_u32:
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; X64: # BB#0:
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; X64-NEXT: bextr $1, %edi, %eax
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; X64-NEXT: retq
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%1 = call i32 @llvm.x86.tbm.bextri.u32(i32 %a0, i32 1)
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ret i32 %1
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}
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define i32 @test__blcfill_u32(i32 %a0) {
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; X32-LABEL: test__blcfill_u32:
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; X32: # BB#0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: leal 1(%ecx), %eax
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; X32-NEXT: andl %ecx, %eax
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; X32-NEXT: retl
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;
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; X64-LABEL: test__blcfill_u32:
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; X64: # BB#0:
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; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
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; X64-NEXT: leal 1(%rdi), %eax
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; X64-NEXT: andl %edi, %eax
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; X64-NEXT: retq
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%1 = add i32 %a0, 1
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%2 = and i32 %a0, %1
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ret i32 %2
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}
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define i32 @test__blci_u32(i32 %a0) {
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; X32-LABEL: test__blci_u32:
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; X32: # BB#0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: leal 1(%ecx), %eax
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; X32-NEXT: xorl $-1, %eax
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; X32-NEXT: orl %ecx, %eax
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; X32-NEXT: retl
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;
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; X64-LABEL: test__blci_u32:
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; X64: # BB#0:
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; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
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; X64-NEXT: leal 1(%rdi), %eax
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; X64-NEXT: xorl $-1, %eax
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; X64-NEXT: orl %edi, %eax
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; X64-NEXT: retq
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%1 = add i32 %a0, 1
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%2 = xor i32 %1, -1
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%3 = or i32 %a0, %2
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ret i32 %3
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}
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define i32 @test__blcic_u32(i32 %a0) {
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; X32-LABEL: test__blcic_u32:
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; X32: # BB#0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movl %eax, %ecx
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; X32-NEXT: xorl $-1, %ecx
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; X32-NEXT: addl $1, %eax
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; X32-NEXT: andl %ecx, %eax
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; X32-NEXT: retl
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;
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; X64-LABEL: test__blcic_u32:
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; X64: # BB#0:
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: xorl $-1, %eax
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; X64-NEXT: addl $1, %edi
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; X64-NEXT: andl %eax, %edi
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: retq
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%1 = xor i32 %a0, -1
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%2 = add i32 %a0, 1
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%3 = and i32 %1, %2
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ret i32 %3
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}
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define i32 @test__blcmsk_u32(i32 %a0) {
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; X32-LABEL: test__blcmsk_u32:
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; X32: # BB#0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: leal 1(%ecx), %eax
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; X32-NEXT: xorl %ecx, %eax
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; X32-NEXT: retl
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;
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; X64-LABEL: test__blcmsk_u32:
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; X64: # BB#0:
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; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
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; X64-NEXT: leal 1(%rdi), %eax
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; X64-NEXT: xorl %edi, %eax
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; X64-NEXT: retq
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%1 = add i32 %a0, 1
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%2 = xor i32 %a0, %1
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ret i32 %2
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}
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define i32 @test__blcs_u32(i32 %a0) {
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; X32-LABEL: test__blcs_u32:
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; X32: # BB#0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: leal 1(%ecx), %eax
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; X32-NEXT: orl %ecx, %eax
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; X32-NEXT: retl
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;
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; X64-LABEL: test__blcs_u32:
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; X64: # BB#0:
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; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
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; X64-NEXT: leal 1(%rdi), %eax
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; X64-NEXT: orl %edi, %eax
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; X64-NEXT: retq
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%1 = add i32 %a0, 1
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%2 = or i32 %a0, %1
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ret i32 %2
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}
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define i32 @test__blsfill_u32(i32 %a0) {
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; X32-LABEL: test__blsfill_u32:
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; X32: # BB#0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: movl %ecx, %eax
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; X32-NEXT: subl $1, %eax
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; X32-NEXT: orl %ecx, %eax
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; X32-NEXT: retl
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;
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; X64-LABEL: test__blsfill_u32:
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; X64: # BB#0:
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: subl $1, %eax
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; X64-NEXT: orl %edi, %eax
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; X64-NEXT: retq
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%1 = sub i32 %a0, 1
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%2 = or i32 %a0, %1
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ret i32 %2
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}
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define i32 @test__blsic_u32(i32 %a0) {
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; X32-LABEL: test__blsic_u32:
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; X32: # BB#0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movl %eax, %ecx
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; X32-NEXT: xorl $-1, %ecx
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; X32-NEXT: subl $1, %eax
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; X32-NEXT: orl %ecx, %eax
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; X32-NEXT: retl
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;
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; X64-LABEL: test__blsic_u32:
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; X64: # BB#0:
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: xorl $-1, %eax
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; X64-NEXT: subl $1, %edi
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; X64-NEXT: orl %eax, %edi
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: retq
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%1 = xor i32 %a0, -1
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%2 = sub i32 %a0, 1
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%3 = or i32 %1, %2
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ret i32 %3
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}
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define i32 @test__t1mskc_u32(i32 %a0) {
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; X32-LABEL: test__t1mskc_u32:
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; X32: # BB#0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movl %eax, %ecx
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; X32-NEXT: xorl $-1, %ecx
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; X32-NEXT: addl $1, %eax
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; X32-NEXT: orl %ecx, %eax
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; X32-NEXT: retl
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;
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; X64-LABEL: test__t1mskc_u32:
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; X64: # BB#0:
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: xorl $-1, %eax
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; X64-NEXT: addl $1, %edi
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; X64-NEXT: orl %eax, %edi
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: retq
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%1 = xor i32 %a0, -1
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%2 = add i32 %a0, 1
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%3 = or i32 %1, %2
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ret i32 %3
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}
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define i32 @test__tzmsk_u32(i32 %a0) {
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; X32-LABEL: test__tzmsk_u32:
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; X32: # BB#0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movl %eax, %ecx
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; X32-NEXT: xorl $-1, %ecx
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; X32-NEXT: subl $1, %eax
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; X32-NEXT: andl %ecx, %eax
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; X32-NEXT: retl
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;
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; X64-LABEL: test__tzmsk_u32:
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; X64: # BB#0:
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: xorl $-1, %eax
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; X64-NEXT: subl $1, %edi
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; X64-NEXT: andl %eax, %edi
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: retq
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%1 = xor i32 %a0, -1
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%2 = sub i32 %a0, 1
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%3 = and i32 %1, %2
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ret i32 %3
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}
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declare i32 @llvm.x86.tbm.bextri.u32(i32, i32)
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