393 lines
7.3 KiB
Plaintext
393 lines
7.3 KiB
Plaintext
/*
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* Device Tree file for the Turris Omnia
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*
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* Copyright (C) 2016 Uwe Kleine-König <uwe@kleine-koenig.org>
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* Copyright (C) 2016 Tomas Hlavacek <tmshlvkc@gmail.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without
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* any warranty of any kind, whether express or implied.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/*
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* Schematic available at https://www.turris.cz/doc/_media/rtrom01-schema.pdf
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include "armada-385.dtsi"
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/ {
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model = "Turris Omnia";
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compatible = "cznic,turris-omnia", "marvell,armada385", "marvell,armada380";
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chosen {
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stdout-path = &uart0;
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x40000000>; /* 1024 MB */
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};
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
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MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
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MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
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MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
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internal-regs {
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/* USB part of the PCIe2/USB 2.0 port */
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usb@58000 {
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status = "okay";
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};
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sata@a8000 {
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status = "okay";
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};
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sdhci@d8000 {
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pinctrl-names = "default";
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pinctrl-0 = <&sdhci_pins>;
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status = "okay";
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bus-width = <8>;
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no-1-8-v;
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non-removable;
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};
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usb3@f0000 {
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status = "okay";
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};
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usb3@f8000 {
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status = "okay";
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};
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};
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pcie-controller {
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status = "okay";
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pcie@1,0 {
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/* Port 0, Lane 0 */
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status = "okay";
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};
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pcie@2,0 {
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/* Port 1, Lane 0 */
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status = "okay";
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};
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pcie@3,0 {
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/* Port 2, Lane 0 */
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status = "okay";
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};
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};
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};
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};
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/* Connected to 88E6176 switch, port 6 */
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ð0 {
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pinctrl-names = "default";
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pinctrl-0 = <&ge0_rgmii_pins>;
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status = "okay";
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phy-mode = "rgmii";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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/* Connected to 88E6176 switch, port 5 */
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ð1 {
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pinctrl-names = "default";
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pinctrl-0 = <&ge1_rgmii_pins>;
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status = "okay";
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phy-mode = "rgmii";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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/* WAN port */
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ð2 {
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status = "okay";
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phy-mode = "sgmii";
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phy = <&phy1>;
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};
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&i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_pins>;
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status = "okay";
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i2cmux@70 {
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compatible = "nxp,pca9547";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x70>;
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status = "okay";
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i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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/* STM32F0 command interface at address 0x2a */
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/* leds device (in STM32F0) at address 0x2b */
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eeprom@54 {
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compatible = "at,24c64";
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reg = <0x54>;
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/* The EEPROM contains data for bootloader.
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* Contents:
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* struct omnia_eeprom {
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* u32 magic; (=0x0341a034 in LE)
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* u32 ramsize; (in GiB)
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* char regdomain[4];
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* u32 crc32;
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* };
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*/
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};
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};
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i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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/* routed to PCIe0/mSATA connector (CN7A) */
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};
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i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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/* routed to PCIe1/USB2 connector (CN61A) */
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};
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i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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/* routed to PCIe2 connector (CN62A) */
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};
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i2c@4 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <4>;
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/* routed to SFP+ */
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};
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i2c@5 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <5>;
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/* ATSHA204A at address 0x64 */
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};
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i2c@6 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <6>;
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/* exposed on pin header */
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};
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i2c@7 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <7>;
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pcawan: gpio@71 {
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/*
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* GPIO expander for SFP+ signals and
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* and phy irq
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*/
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compatible = "nxp,pca9538";
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reg = <0x71>;
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pinctrl-names = "default";
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pinctrl-0 = <&pcawan_pins>;
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interrupt-parent = <&gpio1>;
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interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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};
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};
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&mdio {
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pinctrl-names = "default";
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pinctrl-0 = <&mdio_pins>;
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status = "okay";
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phy1: phy@1 {
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status = "okay";
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compatible = "ethernet-phy-id0141.0DD1", "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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/* irq is connected to &pcawan pin 7 */
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};
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/* Switch MV88E6176 at address 0x10 */
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switch@10 {
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compatible = "marvell,mv88e6085";
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#address-cells = <1>;
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#size-cells = <0>;
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dsa,member = <0 0>;
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reg = <0x10>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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ports@0 {
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reg = <0>;
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label = "lan0";
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};
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ports@1 {
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reg = <1>;
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label = "lan1";
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};
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ports@2 {
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reg = <2>;
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label = "lan2";
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};
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ports@3 {
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reg = <3>;
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label = "lan3";
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};
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ports@4 {
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reg = <4>;
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label = "lan4";
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};
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ports@5 {
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reg = <5>;
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label = "cpu";
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ethernet = <ð1>;
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phy-mode = "rgmii-id";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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/* port 6 is connected to eth0 */
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};
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};
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};
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&pinctrl {
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pcawan_pins: pcawan-pins {
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marvell,pins = "mpp46";
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marvell,function = "gpio";
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};
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spi0cs0_pins: spi0cs0-pins {
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marvell,pins = "mpp25";
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marvell,function = "spi0";
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};
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spi0cs1_pins: spi0cs1-pins {
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marvell,pins = "mpp26";
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marvell,function = "spi0";
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};
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};
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&spi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&spi0_pins &spi0cs0_pins>;
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status = "okay";
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spi-nor@0 {
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compatible = "spansion,s25fl164k", "jedec,spi-nor";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0>;
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spi-max-frequency = <40000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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reg = <0x0 0x00100000>;
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label = "U-Boot";
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};
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partition@100000 {
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reg = <0x00100000 0x00700000>;
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label = "Rescue system";
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};
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};
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};
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/* MISO, MOSI, SCLK and CS1 are routed to pin header CN11 */
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};
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&uart0 {
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/* Pin header CN10 */
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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status = "okay";
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};
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&uart1 {
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/* Pin header CN11 */
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_pins>;
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status = "okay";
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};
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