216 lines
3.5 KiB
Plaintext
216 lines
3.5 KiB
Plaintext
/*
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* Freescale ls1021a QDS board common device tree source
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*
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* Copyright 2013-2015 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include "ls1021a.dtsi"
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/ {
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model = "LS1021A QDS Board";
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aliases {
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enet0_rgmii_phy = &rgmii_phy1;
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enet1_rgmii_phy = &rgmii_phy2;
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enet2_rgmii_phy = &rgmii_phy3;
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enet0_sgmii_phy = &sgmii_phy1c;
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enet1_sgmii_phy = &sgmii_phy1d;
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spi0 = &qspi;
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spi1 = &dspi0;
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};
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};
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&dspi0 {
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bus-num = <0>;
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status = "okay";
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dspiflash: at45db021d@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "atmel,dataflash";
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spi-max-frequency = <16000000>;
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spi-cpol;
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spi-cpha;
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reg = <0>;
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};
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};
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&qspi {
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bus-num = <0>;
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status = "okay";
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qflash0: s25fl128s@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "spi-flash";
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spi-max-frequency = <20000000>;
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reg = <0>;
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};
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};
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&i2c0 {
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status = "okay";
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pca9547: mux@77 {
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reg = <0x77>;
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#address-cells = <1>;
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#size-cells = <0>;
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i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0>;
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ds3232: rtc@68 {
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compatible = "dallas,ds3232";
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reg = <0x68>;
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interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x2>;
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ina220@40 {
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compatible = "ti,ina220";
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reg = <0x40>;
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shunt-resistor = <1000>;
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};
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ina220@41 {
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compatible = "ti,ina220";
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reg = <0x41>;
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shunt-resistor = <1000>;
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};
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};
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i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x3>;
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eeprom@56 {
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compatible = "atmel,24c512";
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reg = <0x56>;
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};
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eeprom@57 {
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compatible = "atmel,24c512";
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reg = <0x57>;
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};
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adt7461a@4c {
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compatible = "adi,adt7461a";
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reg = <0x4c>;
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};
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};
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};
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};
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&ifc {
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#address-cells = <2>;
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#size-cells = <1>;
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/* NOR, NAND Flashes and FPGA on board */
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ranges = <0x0 0x0 0x60000000 0x08000000
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0x2 0x0 0x7e800000 0x00010000
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0x3 0x0 0x7fb00000 0x00000100>;
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status = "okay";
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nor@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x0 0x0 0x8000000>;
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bank-width = <2>;
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device-width = <1>;
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};
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fpga: board-control@3,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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reg = <0x3 0x0 0x0000100>;
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bank-width = <1>;
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device-width = <1>;
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ranges = <0 3 0 0x100>;
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mdio-mux-emi1 {
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compatible = "mdio-mux-mmioreg";
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mdio-parent-bus = <&mdio0>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x54 1>; /* BRDCFG4 */
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mux-mask = <0xe0>; /* EMI1[2:0] */
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/* Onboard PHYs */
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ls1021amdio0: mdio@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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rgmii_phy1: ethernet-phy@1 {
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reg = <0x1>;
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};
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};
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ls1021amdio1: mdio@20 {
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reg = <0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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rgmii_phy2: ethernet-phy@2 {
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reg = <0x2>;
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};
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};
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ls1021amdio2: mdio@40 {
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reg = <0x40>;
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#address-cells = <1>;
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#size-cells = <0>;
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rgmii_phy3: ethernet-phy@3 {
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reg = <0x3>;
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};
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};
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ls1021amdio3: mdio@60 {
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reg = <0x60>;
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#address-cells = <1>;
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#size-cells = <0>;
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sgmii_phy1c: ethernet-phy@1c {
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reg = <0x1c>;
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};
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};
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ls1021amdio4: mdio@80 {
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reg = <0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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sgmii_phy1d: ethernet-phy@1d {
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reg = <0x1d>;
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};
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};
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};
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};
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};
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&lpuart0 {
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status = "okay";
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};
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&mdio0 {
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tbi0: tbi-phy@8 {
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reg = <0x8>;
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device_type = "tbi-phy";
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};
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};
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&uart0 {
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status = "okay";
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};
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&uart1 {
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status = "okay";
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};
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