1873 lines
35 KiB
Plaintext
1873 lines
35 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
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*/
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#include <dt-bindings/pinctrl/rockchip.h>
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#include "rockchip-pinconf.dtsi"
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/*
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* This file is auto generated by pin2dts tool, please keep these code
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* by adding changes at end of this file.
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*/
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&pinctrl {
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cam {
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camm0_pins: camm0-pins {
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rockchip,pins =
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/* cam_clk0_out_m0 */
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<3 RK_PB2 2 &pcfg_pull_none>,
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/* cam_clk1_out_m0 */
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<3 RK_PB3 2 &pcfg_pull_none>;
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};
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camm1_pins: camm1-pins {
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rockchip,pins =
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/* cam_clk0_out_m1 */
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<4 RK_PB1 3 &pcfg_pull_none>,
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/* cam_clk1_out_m1 */
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<4 RK_PB7 3 &pcfg_pull_none>;
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};
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cam_clk2_out: cam-clk2-out {
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rockchip,pins =
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/* cam_clk2_out */
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<3 RK_PB4 2 &pcfg_pull_none>;
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};
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cam_clk3_out: cam-clk3-out {
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rockchip,pins =
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/* cam_clk3_out */
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<3 RK_PB5 2 &pcfg_pull_none>;
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};
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};
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can0 {
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can0m0_pins: can0m0-pins {
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rockchip,pins =
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/* can0_rx_m0 */
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<3 RK_PA1 4 &pcfg_pull_none>,
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/* can0_tx_m0 */
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<3 RK_PA0 4 &pcfg_pull_none>;
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};
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can0m1_pins: can0m1-pins {
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rockchip,pins =
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/* can0_rx_m1 */
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<3 RK_PB7 6 &pcfg_pull_none>,
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/* can0_tx_m1 */
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<3 RK_PB6 6 &pcfg_pull_none>;
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};
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can0m2_pins: can0m2-pins {
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rockchip,pins =
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/* can0_rx_m2 */
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<0 RK_PC7 2 &pcfg_pull_none>,
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/* can0_tx_m2 */
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<0 RK_PC6 2 &pcfg_pull_none>;
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};
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};
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can1 {
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can1m0_pins: can1m0-pins {
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rockchip,pins =
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/* can1_rx_m0 */
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<1 RK_PB7 4 &pcfg_pull_none>,
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/* can1_tx_m0 */
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<1 RK_PC0 5 &pcfg_pull_none>;
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};
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can1m1_pins: can1m1-pins {
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rockchip,pins =
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/* can1_rx_m1 */
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<0 RK_PC1 4 &pcfg_pull_none>,
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/* can1_tx_m1 */
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<0 RK_PC0 4 &pcfg_pull_none>;
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};
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};
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clk {
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clk_32k_in: clk-32k-in {
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rockchip,pins =
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/* clk_32k_in */
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<0 RK_PB0 1 &pcfg_pull_none>;
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};
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};
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clk0 {
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clk0_32k_out: clk0-32k-out {
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rockchip,pins =
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/* clk0_32k_out */
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<0 RK_PB0 2 &pcfg_pull_none>;
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};
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};
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clk1 {
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clk1_32k_out: clk1-32k-out {
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rockchip,pins =
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/* clk1_32k_out */
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<2 RK_PA1 3 &pcfg_pull_none>;
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};
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};
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cpu {
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cpu_pins: cpu-pins {
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rockchip,pins =
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/* cpu_avs */
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<0 RK_PB7 3 &pcfg_pull_none>;
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};
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};
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dsm {
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dsm_pins: dsm-pins {
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rockchip,pins =
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/* dsm_aud_ln */
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<1 RK_PB4 5 &pcfg_pull_none>,
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/* dsm_aud_lp */
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<1 RK_PB3 5 &pcfg_pull_none>,
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/* dsm_aud_rn */
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<1 RK_PB6 6 &pcfg_pull_none>,
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/* dsm_aud_rp */
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<1 RK_PB5 6 &pcfg_pull_none>;
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};
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};
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emmc {
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emmc_bus8: emmc-bus8 {
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rockchip,pins =
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/* emmc_d0 */
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<1 RK_PA0 1 &pcfg_pull_up_drv_level_2>,
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/* emmc_d1 */
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<1 RK_PA1 1 &pcfg_pull_up_drv_level_2>,
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/* emmc_d2 */
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<1 RK_PA2 1 &pcfg_pull_up_drv_level_2>,
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/* emmc_d3 */
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<1 RK_PA3 1 &pcfg_pull_up_drv_level_2>,
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/* emmc_d4 */
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<1 RK_PA4 1 &pcfg_pull_up_drv_level_2>,
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/* emmc_d5 */
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<1 RK_PA5 1 &pcfg_pull_up_drv_level_2>,
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/* emmc_d6 */
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<1 RK_PA6 1 &pcfg_pull_up_drv_level_2>,
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/* emmc_d7 */
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<1 RK_PA7 1 &pcfg_pull_up_drv_level_2>;
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};
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emmc_clk: emmc-clk {
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rockchip,pins =
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/* emmc_clk */
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<1 RK_PB1 1 &pcfg_pull_up_drv_level_2>;
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};
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emmc_cmd: emmc-cmd {
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rockchip,pins =
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/* emmc_cmd */
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<1 RK_PB0 1 &pcfg_pull_up_drv_level_2>;
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};
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emmc_strb: emmc-strb {
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rockchip,pins =
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/* emmc_strb */
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<1 RK_PB2 1 &pcfg_pull_none>;
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};
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};
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eth {
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ethm0_pins: ethm0-pins {
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rockchip,pins =
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/* eth_clk_25m_out_m0 */
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<4 RK_PB1 2 &pcfg_pull_none>;
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};
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ethm1_pins: ethm1-pins {
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rockchip,pins =
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/* eth_clk_25m_out_m1 */
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<2 RK_PA1 2 &pcfg_pull_none>;
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};
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};
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fspi {
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fspi_pins: fspi-pins {
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rockchip,pins =
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/* fspi_clk */
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<1 RK_PB1 2 &pcfg_pull_none>,
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/* fspi_d0 */
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<1 RK_PA0 2 &pcfg_pull_none>,
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/* fspi_d1 */
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<1 RK_PA1 2 &pcfg_pull_none>,
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/* fspi_d2 */
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<1 RK_PA2 2 &pcfg_pull_none>,
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/* fspi_d3 */
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<1 RK_PA3 2 &pcfg_pull_none>;
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};
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fspi_csn0: fspi-csn0 {
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rockchip,pins =
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/* fspi_csn0 */
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<1 RK_PB0 2 &pcfg_pull_none>;
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};
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fspi_csn1: fspi-csn1 {
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rockchip,pins =
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/* fspi_csn1 */
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<1 RK_PB2 2 &pcfg_pull_none>;
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};
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};
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gpu {
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gpu_pins: gpu-pins {
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rockchip,pins =
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/* gpu_avs */
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<0 RK_PC0 3 &pcfg_pull_none>;
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};
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};
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i2c0 {
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i2c0_xfer: i2c0-xfer {
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rockchip,pins =
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/* i2c0_scl */
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<0 RK_PB1 1 &pcfg_pull_none_smt>,
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/* i2c0_sda */
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<0 RK_PB2 1 &pcfg_pull_none_smt>;
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};
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};
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i2c1 {
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i2c1m0_xfer: i2c1m0-xfer {
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rockchip,pins =
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/* i2c1_scl_m0 */
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<0 RK_PB3 1 &pcfg_pull_none_smt>,
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/* i2c1_sda_m0 */
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<0 RK_PB4 1 &pcfg_pull_none_smt>;
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};
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i2c1m1_xfer: i2c1m1-xfer {
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rockchip,pins =
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/* i2c1_scl_m1 */
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<4 RK_PB4 5 &pcfg_pull_none_smt>,
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/* i2c1_sda_m1 */
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<4 RK_PB5 5 &pcfg_pull_none_smt>;
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};
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};
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i2c2 {
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i2c2m0_xfer: i2c2m0-xfer {
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rockchip,pins =
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/* i2c2_scl_m0 */
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<0 RK_PB5 1 &pcfg_pull_none_smt>,
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/* i2c2_sda_m0 */
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<0 RK_PB6 1 &pcfg_pull_none_smt>;
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};
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i2c2m1_xfer: i2c2m1-xfer {
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rockchip,pins =
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/* i2c2_scl_m1 */
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<3 RK_PD2 5 &pcfg_pull_none_smt>,
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/* i2c2_sda_m1 */
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<3 RK_PD3 5 &pcfg_pull_none_smt>;
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};
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};
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i2c3 {
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i2c3m0_xfer: i2c3m0-xfer {
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rockchip,pins =
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/* i2c3_scl_m0 */
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<3 RK_PA0 1 &pcfg_pull_none_smt>,
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/* i2c3_sda_m0 */
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<3 RK_PA1 1 &pcfg_pull_none_smt>;
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};
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i2c3m1_xfer: i2c3m1-xfer {
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rockchip,pins =
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/* i2c3_scl_m1 */
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<4 RK_PA5 5 &pcfg_pull_none_smt>,
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/* i2c3_sda_m1 */
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<4 RK_PA6 5 &pcfg_pull_none_smt>;
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};
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};
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i2c4 {
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i2c4m0_xfer: i2c4m0-xfer {
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rockchip,pins =
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/* i2c4_scl_m0 */
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<3 RK_PB6 5 &pcfg_pull_none_smt>,
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/* i2c4_sda_m0 */
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<3 RK_PB7 5 &pcfg_pull_none_smt>;
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};
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i2c4m1_xfer: i2c4m1-xfer {
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rockchip,pins =
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/* i2c4_scl_m1 */
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<0 RK_PA5 2 &pcfg_pull_none_smt>,
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/* i2c4_sda_m1 */
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<0 RK_PA4 2 &pcfg_pull_none_smt>;
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};
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};
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i2c5 {
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i2c5m0_xfer: i2c5m0-xfer {
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rockchip,pins =
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/* i2c5_scl_m0 */
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<3 RK_PC2 1 &pcfg_pull_none_smt>,
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/* i2c5_sda_m0 */
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<3 RK_PC3 1 &pcfg_pull_none_smt>;
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};
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i2c5m1_xfer: i2c5m1-xfer {
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rockchip,pins =
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/* i2c5_scl_m1 */
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<1 RK_PC7 4 &pcfg_pull_none_smt>,
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/* i2c5_sda_m1 */
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<1 RK_PD0 4 &pcfg_pull_none_smt>;
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};
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};
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i2s0 {
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i2s0m0_lrck: i2s0m0-lrck {
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rockchip,pins =
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/* i2s0_lrck_m0 */
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<3 RK_PA4 1 &pcfg_pull_none>;
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};
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i2s0m0_mclk: i2s0m0-mclk {
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rockchip,pins =
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/* i2s0_mclk_m0 */
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<3 RK_PA2 1 &pcfg_pull_none>;
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};
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i2s0m0_sclk: i2s0m0-sclk {
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rockchip,pins =
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/* i2s0_sclk_m0 */
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<3 RK_PA3 1 &pcfg_pull_none>;
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};
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i2s0m0_sdi0: i2s0m0-sdi0 {
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rockchip,pins =
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/* i2s0_sdi0_m0 */
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<3 RK_PB1 1 &pcfg_pull_none>;
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};
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i2s0m0_sdi1: i2s0m0-sdi1 {
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rockchip,pins =
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/* i2s0_sdi1_m0 */
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<3 RK_PB0 2 &pcfg_pull_none>;
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};
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i2s0m0_sdi2: i2s0m0-sdi2 {
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rockchip,pins =
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/* i2s0_sdi2_m0 */
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<3 RK_PA7 2 &pcfg_pull_none>;
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};
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i2s0m0_sdi3: i2s0m0-sdi3 {
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rockchip,pins =
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/* i2s0_sdi3_m0 */
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<3 RK_PA6 2 &pcfg_pull_none>;
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};
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i2s0m0_sdo0: i2s0m0-sdo0 {
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rockchip,pins =
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/* i2s0_sdo0_m0 */
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<3 RK_PA5 1 &pcfg_pull_none>;
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};
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i2s0m0_sdo1: i2s0m0-sdo1 {
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rockchip,pins =
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/* i2s0_sdo1_m0 */
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<3 RK_PA6 1 &pcfg_pull_none>;
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};
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i2s0m0_sdo2: i2s0m0-sdo2 {
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rockchip,pins =
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/* i2s0_sdo2_m0 */
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<3 RK_PA7 1 &pcfg_pull_none>;
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};
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i2s0m0_sdo3: i2s0m0-sdo3 {
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rockchip,pins =
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/* i2s0_sdo3_m0 */
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<3 RK_PB0 1 &pcfg_pull_none>;
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};
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i2s0m1_lrck: i2s0m1-lrck {
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rockchip,pins =
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/* i2s0_lrck_m1 */
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<1 RK_PC4 3 &pcfg_pull_none>;
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};
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i2s0m1_mclk: i2s0m1-mclk {
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rockchip,pins =
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/* i2s0_mclk_m1 */
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<1 RK_PC6 3 &pcfg_pull_none>;
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};
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i2s0m1_sclk: i2s0m1-sclk {
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rockchip,pins =
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/* i2s0_sclk_m1 */
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<1 RK_PC5 3 &pcfg_pull_none>;
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};
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i2s0m1_sdi0: i2s0m1-sdi0 {
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rockchip,pins =
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/* i2s0_sdi0_m1 */
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<1 RK_PC1 3 &pcfg_pull_none>;
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};
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i2s0m1_sdi1: i2s0m1-sdi1 {
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rockchip,pins =
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/* i2s0_sdi1_m1 */
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<1 RK_PC2 3 &pcfg_pull_none>;
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};
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i2s0m1_sdi2: i2s0m1-sdi2 {
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rockchip,pins =
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/* i2s0_sdi2_m1 */
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<1 RK_PD3 3 &pcfg_pull_none>;
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};
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i2s0m1_sdi3: i2s0m1-sdi3 {
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rockchip,pins =
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/* i2s0_sdi3_m1 */
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<1 RK_PD4 3 &pcfg_pull_none>;
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};
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i2s0m1_sdo0: i2s0m1-sdo0 {
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rockchip,pins =
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/* i2s0_sdo0_m1 */
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<1 RK_PC3 3 &pcfg_pull_none>;
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};
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i2s0m1_sdo1: i2s0m1-sdo1 {
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rockchip,pins =
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/* i2s0_sdo1_m1 */
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<1 RK_PD1 3 &pcfg_pull_none>;
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};
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i2s0m1_sdo2: i2s0m1-sdo2 {
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rockchip,pins =
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/* i2s0_sdo2_m1 */
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<1 RK_PD2 3 &pcfg_pull_none>;
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};
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i2s0m1_sdo3: i2s0m1-sdo3 {
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rockchip,pins =
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/* i2s0_sdo3_m1 */
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<2 RK_PA1 5 &pcfg_pull_none>;
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};
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};
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i2s1 {
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i2s1m0_lrck: i2s1m0-lrck {
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rockchip,pins =
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/* i2s1_lrck_m0 */
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<3 RK_PC6 2 &pcfg_pull_none>;
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};
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i2s1m0_mclk: i2s1m0-mclk {
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rockchip,pins =
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/* i2s1_mclk_m0 */
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<3 RK_PC4 2 &pcfg_pull_none>;
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};
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i2s1m0_sclk: i2s1m0-sclk {
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rockchip,pins =
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/* i2s1_sclk_m0 */
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<3 RK_PC5 2 &pcfg_pull_none>;
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};
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i2s1m0_sdi0: i2s1m0-sdi0 {
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rockchip,pins =
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/* i2s1_sdi0_m0 */
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<3 RK_PD0 2 &pcfg_pull_none>;
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};
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i2s1m0_sdi1: i2s1m0-sdi1 {
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rockchip,pins =
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/* i2s1_sdi1_m0 */
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<3 RK_PD1 2 &pcfg_pull_none>;
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};
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i2s1m0_sdi2: i2s1m0-sdi2 {
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rockchip,pins =
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/* i2s1_sdi2_m0 */
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<3 RK_PD2 2 &pcfg_pull_none>;
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};
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i2s1m0_sdi3: i2s1m0-sdi3 {
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|
rockchip,pins =
|
|
/* i2s1_sdi3_m0 */
|
|
<3 RK_PD3 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s1m0_sdo0: i2s1m0-sdo0 {
|
|
rockchip,pins =
|
|
/* i2s1_sdo0_m0 */
|
|
<3 RK_PC7 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s1m0_sdo1: i2s1m0-sdo1 {
|
|
rockchip,pins =
|
|
/* i2s1_sdo1_m0 */
|
|
<4 RK_PB4 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s1m0_sdo2: i2s1m0-sdo2 {
|
|
rockchip,pins =
|
|
/* i2s1_sdo2_m0 */
|
|
<4 RK_PB5 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s1m0_sdo3: i2s1m0-sdo3 {
|
|
rockchip,pins =
|
|
/* i2s1_sdo3_m0 */
|
|
<4 RK_PB6 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s1m1_lrck: i2s1m1-lrck {
|
|
rockchip,pins =
|
|
/* i2s1_lrck_m1 */
|
|
<3 RK_PB4 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s1m1_mclk: i2s1m1-mclk {
|
|
rockchip,pins =
|
|
/* i2s1_mclk_m1 */
|
|
<3 RK_PB2 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s1m1_sclk: i2s1m1-sclk {
|
|
rockchip,pins =
|
|
/* i2s1_sclk_m1 */
|
|
<3 RK_PB3 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s1m1_sdi0: i2s1m1-sdi0 {
|
|
rockchip,pins =
|
|
/* i2s1_sdi0_m1 */
|
|
<3 RK_PC1 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s1m1_sdi1: i2s1m1-sdi1 {
|
|
rockchip,pins =
|
|
/* i2s1_sdi1_m1 */
|
|
<3 RK_PC0 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s1m1_sdi2: i2s1m1-sdi2 {
|
|
rockchip,pins =
|
|
/* i2s1_sdi2_m1 */
|
|
<3 RK_PB7 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s1m1_sdi3: i2s1m1-sdi3 {
|
|
rockchip,pins =
|
|
/* i2s1_sdi3_m1 */
|
|
<3 RK_PB6 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s1m1_sdo0: i2s1m1-sdo0 {
|
|
rockchip,pins =
|
|
/* i2s1_sdo0_m1 */
|
|
<3 RK_PB5 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s1m1_sdo1: i2s1m1-sdo1 {
|
|
rockchip,pins =
|
|
/* i2s1_sdo1_m1 */
|
|
<3 RK_PB6 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s1m1_sdo2: i2s1m1-sdo2 {
|
|
rockchip,pins =
|
|
/* i2s1_sdo2_m1 */
|
|
<3 RK_PB7 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s1m1_sdo3: i2s1m1-sdo3 {
|
|
rockchip,pins =
|
|
/* i2s1_sdo3_m1 */
|
|
<3 RK_PC0 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2s2 {
|
|
i2s2m0_lrck: i2s2m0-lrck {
|
|
rockchip,pins =
|
|
/* i2s2_lrck_m0 */
|
|
<1 RK_PD6 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s2m0_mclk: i2s2m0-mclk {
|
|
rockchip,pins =
|
|
/* i2s2_mclk_m0 */
|
|
<2 RK_PA1 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s2m0_sclk: i2s2m0-sclk {
|
|
rockchip,pins =
|
|
/* i2s2_sclk_m0 */
|
|
<1 RK_PD5 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s2m0_sdi: i2s2m0-sdi {
|
|
rockchip,pins =
|
|
/* i2s2_sdi_m0 */
|
|
<2 RK_PA0 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s2m0_sdo: i2s2m0-sdo {
|
|
rockchip,pins =
|
|
/* i2s2_sdo_m0 */
|
|
<1 RK_PD7 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s2m1_lrck: i2s2m1-lrck {
|
|
rockchip,pins =
|
|
/* i2s2_lrck_m1 */
|
|
<4 RK_PA1 3 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s2m1_mclk: i2s2m1-mclk {
|
|
rockchip,pins =
|
|
/* i2s2_mclk_m1 */
|
|
<3 RK_PD6 3 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s2m1_sclk: i2s2m1-sclk {
|
|
rockchip,pins =
|
|
/* i2s2_sclk_m1 */
|
|
<4 RK_PB1 4 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s2m1_sdi: i2s2m1-sdi {
|
|
rockchip,pins =
|
|
/* i2s2_sdi_m1 */
|
|
<3 RK_PD4 4 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s2m1_sdo: i2s2m1-sdo {
|
|
rockchip,pins =
|
|
/* i2s2_sdo_m1 */
|
|
<3 RK_PD5 4 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
isp {
|
|
isp_pins: isp-pins {
|
|
rockchip,pins =
|
|
/* isp_flash_trigin */
|
|
<3 RK_PC1 2 &pcfg_pull_none>,
|
|
/* isp_flash_trigout */
|
|
<3 RK_PC3 2 &pcfg_pull_none>,
|
|
/* isp_prelight_trigout */
|
|
<3 RK_PC2 2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
jtag {
|
|
jtagm0_pins: jtagm0-pins {
|
|
rockchip,pins =
|
|
/* jtag_cpu_mcu_tck_m0 */
|
|
<0 RK_PD1 2 &pcfg_pull_none>,
|
|
/* jtag_cpu_mcu_tms_m0 */
|
|
<0 RK_PD0 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
jtagm1_pins: jtagm1-pins {
|
|
rockchip,pins =
|
|
/* jtag_cpu_mcu_tck_m1 */
|
|
<1 RK_PB5 2 &pcfg_pull_none>,
|
|
/* jtag_cpu_mcu_tms_m1 */
|
|
<1 RK_PB6 2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
npu {
|
|
npu_pins: npu-pins {
|
|
rockchip,pins =
|
|
/* npu_avs */
|
|
<0 RK_PC1 3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pcie20 {
|
|
pcie20m0_pins: pcie20m0-pins {
|
|
rockchip,pins =
|
|
/* pcie20_clkreqn_m0 */
|
|
<0 RK_PA6 1 &pcfg_pull_none>,
|
|
/* pcie20_perstn_m0 */
|
|
<0 RK_PB5 2 &pcfg_pull_none>,
|
|
/* pcie20_waken_m0 */
|
|
<0 RK_PB6 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
pcie20m1_pins: pcie20m1-pins {
|
|
rockchip,pins =
|
|
/* pcie20_clkreqn_m1 */
|
|
<3 RK_PA6 4 &pcfg_pull_none>,
|
|
/* pcie20_perstn_m1 */
|
|
<3 RK_PB0 4 &pcfg_pull_none>,
|
|
/* pcie20_waken_m1 */
|
|
<3 RK_PA7 4 &pcfg_pull_none>;
|
|
};
|
|
|
|
pcie20_buttonrstn: pcie20-buttonrstn {
|
|
rockchip,pins =
|
|
/* pcie20_buttonrstn */
|
|
<0 RK_PB0 3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pdm {
|
|
pdmm0_clk0: pdmm0-clk0 {
|
|
rockchip,pins =
|
|
/* pdm_clk0_m0 */
|
|
<3 RK_PA6 3 &pcfg_pull_none>;
|
|
};
|
|
|
|
pdmm0_clk1: pdmm0-clk1 {
|
|
rockchip,pins =
|
|
/* pdm_clk1_m0 */
|
|
<3 RK_PA2 3 &pcfg_pull_none>;
|
|
};
|
|
|
|
pdmm0_sdi0: pdmm0-sdi0 {
|
|
rockchip,pins =
|
|
/* pdm_sdi0_m0 */
|
|
<3 RK_PB1 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
pdmm0_sdi1: pdmm0-sdi1 {
|
|
rockchip,pins =
|
|
/* pdm_sdi1_m0 */
|
|
<3 RK_PB0 3 &pcfg_pull_none>;
|
|
};
|
|
|
|
pdmm0_sdi2: pdmm0-sdi2 {
|
|
rockchip,pins =
|
|
/* pdm_sdi2_m0 */
|
|
<3 RK_PA7 3 &pcfg_pull_none>;
|
|
};
|
|
|
|
pdmm0_sdi3: pdmm0-sdi3 {
|
|
rockchip,pins =
|
|
/* pdm_sdi3_m0 */
|
|
<3 RK_PA0 3 &pcfg_pull_none>;
|
|
};
|
|
|
|
pdmm1_clk0: pdmm1-clk0 {
|
|
rockchip,pins =
|
|
/* pdm_clk0_m1 */
|
|
<4 RK_PB7 4 &pcfg_pull_none>;
|
|
};
|
|
|
|
pdmm1_clk1: pdmm1-clk1 {
|
|
rockchip,pins =
|
|
/* pdm_clk1_m1 */
|
|
<4 RK_PB1 5 &pcfg_pull_none>;
|
|
};
|
|
|
|
pdmm1_sdi0: pdmm1-sdi0 {
|
|
rockchip,pins =
|
|
/* pdm_sdi0_m1 */
|
|
<4 RK_PA7 4 &pcfg_pull_none>;
|
|
};
|
|
|
|
pdmm1_sdi1: pdmm1-sdi1 {
|
|
rockchip,pins =
|
|
/* pdm_sdi1_m1 */
|
|
<4 RK_PB0 4 &pcfg_pull_none>;
|
|
};
|
|
|
|
pdmm1_sdi2: pdmm1-sdi2 {
|
|
rockchip,pins =
|
|
/* pdm_sdi2_m1 */
|
|
<4 RK_PA5 4 &pcfg_pull_none>;
|
|
};
|
|
|
|
pdmm1_sdi3: pdmm1-sdi3 {
|
|
rockchip,pins =
|
|
/* pdm_sdi3_m1 */
|
|
<4 RK_PA6 4 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pmic {
|
|
pmic_int: pmic-int {
|
|
rockchip,pins =
|
|
<0 RK_PA3 0 &pcfg_pull_up>;
|
|
};
|
|
|
|
soc_slppin_gpio: soc-slppin-gpio {
|
|
rockchip,pins =
|
|
<0 RK_PA2 0 &pcfg_output_low>;
|
|
};
|
|
|
|
soc_slppin_slp: soc-slppin-slp {
|
|
rockchip,pins =
|
|
<0 RK_PA2 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pmu {
|
|
pmu_pins: pmu-pins {
|
|
rockchip,pins =
|
|
/* pmu_debug */
|
|
<0 RK_PA5 3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm0 {
|
|
pwm0m0_pins: pwm0m0-pins {
|
|
rockchip,pins =
|
|
/* pwm0_m0 */
|
|
<0 RK_PC3 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
pwm0m1_pins: pwm0m1-pins {
|
|
rockchip,pins =
|
|
/* pwm0_m1 */
|
|
<1 RK_PC5 4 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm1 {
|
|
pwm1m0_pins: pwm1m0-pins {
|
|
rockchip,pins =
|
|
/* pwm1_m0 */
|
|
<0 RK_PC4 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
pwm1m1_pins: pwm1m1-pins {
|
|
rockchip,pins =
|
|
/* pwm1_m1 */
|
|
<1 RK_PC6 4 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm2 {
|
|
pwm2m0_pins: pwm2m0-pins {
|
|
rockchip,pins =
|
|
/* pwm2_m0 */
|
|
<0 RK_PC5 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
pwm2m1_pins: pwm2m1-pins {
|
|
rockchip,pins =
|
|
/* pwm2_m1 */
|
|
<1 RK_PC7 3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm3 {
|
|
pwm3m0_pins: pwm3m0-pins {
|
|
rockchip,pins =
|
|
/* pwm3_m0 */
|
|
<0 RK_PA7 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
pwm3m1_pins: pwm3m1-pins {
|
|
rockchip,pins =
|
|
/* pwm3_m1 */
|
|
<1 RK_PD0 3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm4 {
|
|
pwm4m0_pins: pwm4m0-pins {
|
|
rockchip,pins =
|
|
/* pwm4_m0 */
|
|
<0 RK_PB7 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
pwm4m1_pins: pwm4m1-pins {
|
|
rockchip,pins =
|
|
/* pwm4_m1 */
|
|
<1 RK_PD1 4 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm5 {
|
|
pwm5m0_pins: pwm5m0-pins {
|
|
rockchip,pins =
|
|
/* pwm5_m0 */
|
|
<0 RK_PC2 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
pwm5m1_pins: pwm5m1-pins {
|
|
rockchip,pins =
|
|
/* pwm5_m1 */
|
|
<1 RK_PD2 4 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm6 {
|
|
pwm6m0_pins: pwm6m0-pins {
|
|
rockchip,pins =
|
|
/* pwm6_m0 */
|
|
<0 RK_PC1 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
pwm6m1_pins: pwm6m1-pins {
|
|
rockchip,pins =
|
|
/* pwm6_m1 */
|
|
<1 RK_PD3 4 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm7 {
|
|
pwm7m0_pins: pwm7m0-pins {
|
|
rockchip,pins =
|
|
/* pwm7_m0 */
|
|
<0 RK_PC0 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
pwm7m1_pins: pwm7m1-pins {
|
|
rockchip,pins =
|
|
/* pwm7_m1 */
|
|
<1 RK_PD4 4 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm8 {
|
|
pwm8m0_pins: pwm8m0-pins {
|
|
rockchip,pins =
|
|
/* pwm8_m0 */
|
|
<3 RK_PA4 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
pwm8m1_pins: pwm8m1-pins {
|
|
rockchip,pins =
|
|
/* pwm8_m1 */
|
|
<1 RK_PC1 4 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm9 {
|
|
pwm9m0_pins: pwm9m0-pins {
|
|
rockchip,pins =
|
|
/* pwm9_m0 */
|
|
<3 RK_PA5 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
pwm9m1_pins: pwm9m1-pins {
|
|
rockchip,pins =
|
|
/* pwm9_m1 */
|
|
<1 RK_PC2 4 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm10 {
|
|
pwm10m0_pins: pwm10m0-pins {
|
|
rockchip,pins =
|
|
/* pwm10_m0 */
|
|
<1 RK_PB5 5 &pcfg_pull_none>;
|
|
};
|
|
|
|
pwm10m1_pins: pwm10m1-pins {
|
|
rockchip,pins =
|
|
/* pwm10_m1 */
|
|
<1 RK_PC3 4 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm11 {
|
|
pwm11m0_pins: pwm11m0-pins {
|
|
rockchip,pins =
|
|
/* pwm11_m0 */
|
|
<1 RK_PB6 5 &pcfg_pull_none>;
|
|
};
|
|
|
|
pwm11m1_pins: pwm11m1-pins {
|
|
rockchip,pins =
|
|
/* pwm11_m1 */
|
|
<1 RK_PC4 4 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm12 {
|
|
pwm12m0_pins: pwm12m0-pins {
|
|
rockchip,pins =
|
|
/* pwm12_m0 */
|
|
<4 RK_PA1 4 &pcfg_pull_none>;
|
|
};
|
|
|
|
pwm12m1_pins: pwm12m1-pins {
|
|
rockchip,pins =
|
|
/* pwm12_m1 */
|
|
<3 RK_PB4 5 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm13 {
|
|
pwm13m0_pins: pwm13m0-pins {
|
|
rockchip,pins =
|
|
/* pwm13_m0 */
|
|
<4 RK_PA4 3 &pcfg_pull_none>;
|
|
};
|
|
|
|
pwm13m1_pins: pwm13m1-pins {
|
|
rockchip,pins =
|
|
/* pwm13_m1 */
|
|
<3 RK_PB5 5 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm14 {
|
|
pwm14m0_pins: pwm14m0-pins {
|
|
rockchip,pins =
|
|
/* pwm14_m0 */
|
|
<3 RK_PC5 4 &pcfg_pull_none>;
|
|
};
|
|
|
|
pwm14m1_pins: pwm14m1-pins {
|
|
rockchip,pins =
|
|
/* pwm14_m1 */
|
|
<1 RK_PD7 5 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm15 {
|
|
pwm15m0_pins: pwm15m0-pins {
|
|
rockchip,pins =
|
|
/* pwm15_m0 */
|
|
<3 RK_PC6 4 &pcfg_pull_none>;
|
|
};
|
|
|
|
pwm15m1_pins: pwm15m1-pins {
|
|
rockchip,pins =
|
|
/* pwm15_m1 */
|
|
<2 RK_PA0 5 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwr {
|
|
pwr_pins: pwr-pins {
|
|
rockchip,pins =
|
|
/* pwr_ctrl0 */
|
|
<0 RK_PA2 1 &pcfg_pull_none>,
|
|
/* pwr_ctrl1 */
|
|
<0 RK_PA3 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
ref {
|
|
ref_pins: ref-pins {
|
|
rockchip,pins =
|
|
/* ref_clk_out */
|
|
<0 RK_PA0 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
rgmii {
|
|
rgmiim0_miim: rgmiim0-miim {
|
|
rockchip,pins =
|
|
/* rgmii_mdc_m0 */
|
|
<4 RK_PB2 2 &pcfg_pull_none>,
|
|
/* rgmii_mdio_m0 */
|
|
<4 RK_PB3 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
rgmiim0_rx_er: rgmiim0-rx_er {
|
|
rockchip,pins =
|
|
/* rgmii_rxer_m0 */
|
|
<4 RK_PB0 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
rgmiim0_rx_bus2: rgmiim0-rx_bus2 {
|
|
rockchip,pins =
|
|
/* rgmii_rxd0_m0 */
|
|
<4 RK_PA5 2 &pcfg_pull_none>,
|
|
/* rgmii_rxd1_m0 */
|
|
<4 RK_PA6 2 &pcfg_pull_none>,
|
|
/* rgmii_rxdv_m0 */
|
|
<4 RK_PA7 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
rgmiim0_tx_bus2: rgmiim0-tx_bus2 {
|
|
rockchip,pins =
|
|
/* rgmii_txd0_m0 */
|
|
<4 RK_PA2 2 &pcfg_pull_none>,
|
|
/* rgmii_txd1_m0 */
|
|
<4 RK_PA3 2 &pcfg_pull_none>,
|
|
/* rgmii_txen_m0 */
|
|
<4 RK_PA4 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
rgmiim0_rgmii_clk: rgmiim0-rgmii_clk {
|
|
rockchip,pins =
|
|
/* rgmii_rxclk_m0 */
|
|
<4 RK_PA1 2 &pcfg_pull_none>,
|
|
/* rgmii_txclk_m0 */
|
|
<3 RK_PD6 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
rgmiim0_rgmii_bus: rgmiim0-rgmii_bus {
|
|
rockchip,pins =
|
|
/* rgmii_rxd2_m0 */
|
|
<3 RK_PD7 2 &pcfg_pull_none>,
|
|
/* rgmii_rxd3_m0 */
|
|
<4 RK_PA0 2 &pcfg_pull_none>,
|
|
/* rgmii_txd2_m0 */
|
|
<3 RK_PD4 2 &pcfg_pull_none>,
|
|
/* rgmii_txd3_m0 */
|
|
<3 RK_PD5 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
rgmiim0_clk: rgmiim0-clk {
|
|
rockchip,pins =
|
|
/* rgmiim0_clk */
|
|
<4 RK_PB7 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
rgmiim1_miim: rgmiim1-miim {
|
|
rockchip,pins =
|
|
/* rgmii_mdc_m1 */
|
|
<1 RK_PC7 2 &pcfg_pull_none>,
|
|
/* rgmii_mdio_m1 */
|
|
<1 RK_PD0 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
rgmiim1_rx_er: rgmiim1-rx_er {
|
|
rockchip,pins =
|
|
/* rgmii_rxer_m1 */
|
|
<2 RK_PA0 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
rgmiim1_rx_bus2: rgmiim1-rx_bus2 {
|
|
rockchip,pins =
|
|
/* rgmii_rxd0_m1 */
|
|
<1 RK_PD4 2 &pcfg_pull_none>,
|
|
/* rgmii_rxd1_m1 */
|
|
<1 RK_PD7 2 &pcfg_pull_none>,
|
|
/* rgmii_rxdv_m1 */
|
|
<1 RK_PD6 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
rgmiim1_tx_bus2: rgmiim1-tx_bus2 {
|
|
rockchip,pins =
|
|
/* rgmii_txd0_m1 */
|
|
<1 RK_PD1 2 &pcfg_pull_none>,
|
|
/* rgmii_txd1_m1 */
|
|
<1 RK_PD2 2 &pcfg_pull_none>,
|
|
/* rgmii_txen_m1 */
|
|
<1 RK_PD3 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
rgmiim1_rgmii_clk: rgmiim1-rgmii_clk {
|
|
rockchip,pins =
|
|
/* rgmii_rxclk_m1 */
|
|
<1 RK_PC6 2 &pcfg_pull_none>,
|
|
/* rgmii_txclk_m1 */
|
|
<1 RK_PC3 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
rgmiim1_rgmii_bus: rgmiim1-rgmii_bus {
|
|
rockchip,pins =
|
|
/* rgmii_rxd2_m1 */
|
|
<1 RK_PC4 2 &pcfg_pull_none>,
|
|
/* rgmii_rxd3_m1 */
|
|
<1 RK_PC5 2 &pcfg_pull_none>,
|
|
/* rgmii_txd2_m1 */
|
|
<1 RK_PC1 2 &pcfg_pull_none>,
|
|
/* rgmii_txd3_m1 */
|
|
<1 RK_PC2 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
rgmiim1_clk: rgmiim1-clk {
|
|
rockchip,pins =
|
|
/* rgmiim1_clk */
|
|
<1 RK_PD5 2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
rmii {
|
|
rmii_pins: rmii-pins {
|
|
rockchip,pins =
|
|
/* rmii_clk */
|
|
<1 RK_PD5 5 &pcfg_pull_none>,
|
|
/* rmii_mdc */
|
|
<1 RK_PC7 5 &pcfg_pull_none>,
|
|
/* rmii_mdio */
|
|
<1 RK_PD0 5 &pcfg_pull_none>,
|
|
/* rmii_rxd0 */
|
|
<1 RK_PD4 5 &pcfg_pull_none>,
|
|
/* rmii_rxd1 */
|
|
<1 RK_PD7 6 &pcfg_pull_none>,
|
|
/* rmii_rxdv_crs */
|
|
<1 RK_PD6 5 &pcfg_pull_none>,
|
|
/* rmii_rxer */
|
|
<2 RK_PA0 6 &pcfg_pull_none>,
|
|
/* rmii_txd0 */
|
|
<1 RK_PD1 5 &pcfg_pull_none>,
|
|
/* rmii_txd1 */
|
|
<1 RK_PD2 5 &pcfg_pull_none>,
|
|
/* rmii_txen */
|
|
<1 RK_PD3 5 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
sdmmc0_pins: sdmmc0-pins {
|
|
sdmmc0_bus4: sdmmc0-bus4 {
|
|
rockchip,pins =
|
|
/* sdmmc0_d0 */
|
|
<1 RK_PB3 1 &pcfg_pull_up_drv_level_2>,
|
|
/* sdmmc0_d1 */
|
|
<1 RK_PB4 1 &pcfg_pull_up_drv_level_2>,
|
|
/* sdmmc0_d2 */
|
|
<1 RK_PB5 1 &pcfg_pull_up_drv_level_2>,
|
|
/* sdmmc0_d3 */
|
|
<1 RK_PB6 1 &pcfg_pull_up_drv_level_2>;
|
|
};
|
|
|
|
sdmmc0_clk: sdmmc0-clk {
|
|
rockchip,pins =
|
|
/* sdmmc0_clk */
|
|
<1 RK_PC0 1 &pcfg_pull_up_drv_level_2>;
|
|
};
|
|
|
|
sdmmc0_cmd: sdmmc0-cmd {
|
|
rockchip,pins =
|
|
/* sdmmc0_cmd */
|
|
<1 RK_PB7 1 &pcfg_pull_up_drv_level_2>;
|
|
};
|
|
|
|
sdmmc0_det: sdmmc0-det {
|
|
rockchip,pins =
|
|
/* sdmmc0_detn */
|
|
<0 RK_PA4 1 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdmmc0_pwren: sdmmc0-pwren {
|
|
rockchip,pins =
|
|
/* sdmmc0_pwren */
|
|
<0 RK_PA5 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
sdmmc1 {
|
|
sdmmc1_bus4: sdmmc1-bus4 {
|
|
rockchip,pins =
|
|
/* sdmmc1_d0 */
|
|
<1 RK_PC1 1 &pcfg_pull_up_drv_level_2>,
|
|
/* sdmmc1_d1 */
|
|
<1 RK_PC2 1 &pcfg_pull_up_drv_level_2>,
|
|
/* sdmmc1_d2 */
|
|
<1 RK_PC3 1 &pcfg_pull_up_drv_level_2>,
|
|
/* sdmmc1_d3 */
|
|
<1 RK_PC4 1 &pcfg_pull_up_drv_level_2>;
|
|
};
|
|
|
|
sdmmc1_clk: sdmmc1-clk {
|
|
rockchip,pins =
|
|
/* sdmmc1_clk */
|
|
<1 RK_PC6 1 &pcfg_pull_up_drv_level_2>;
|
|
};
|
|
|
|
sdmmc1_cmd: sdmmc1-cmd {
|
|
rockchip,pins =
|
|
/* sdmmc1_cmd */
|
|
<1 RK_PC5 1 &pcfg_pull_up_drv_level_2>;
|
|
};
|
|
|
|
sdmmc1_det: sdmmc1-det {
|
|
rockchip,pins =
|
|
/* sdmmc1_detn */
|
|
<1 RK_PD0 1 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdmmc1_pwren: sdmmc1-pwren {
|
|
rockchip,pins =
|
|
/* sdmmc1_pwren */
|
|
<1 RK_PC7 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
spdif {
|
|
spdifm0_pins: spdifm0-pins {
|
|
rockchip,pins =
|
|
/* spdif_tx_m0 */
|
|
<3 RK_PA1 3 &pcfg_pull_none>;
|
|
};
|
|
|
|
spdifm1_pins: spdifm1-pins {
|
|
rockchip,pins =
|
|
/* spdif_tx_m1 */
|
|
<0 RK_PB7 4 &pcfg_pull_none>;
|
|
};
|
|
|
|
spdifm2_pins: spdifm2-pins {
|
|
rockchip,pins =
|
|
/* spdif_tx_m2 */
|
|
<1 RK_PB7 2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
spi0 {
|
|
spi0m0_pins: spi0m0-pins {
|
|
rockchip,pins =
|
|
/* spi0_clk_m0 */
|
|
<0 RK_PC3 3 &pcfg_pull_none>,
|
|
/* spi0_miso_m0 */
|
|
<0 RK_PC5 3 &pcfg_pull_none>,
|
|
/* spi0_mosi_m0 */
|
|
<0 RK_PC4 3 &pcfg_pull_none>;
|
|
};
|
|
|
|
spi0m0_csn0: spi0m0-csn0 {
|
|
rockchip,pins =
|
|
/* spi0m0_csn0 */
|
|
<0 RK_PC2 3 &pcfg_pull_none>;
|
|
};
|
|
spi0m0_csn1: spi0m0-csn1 {
|
|
rockchip,pins =
|
|
/* spi0m0_csn1 */
|
|
<0 RK_PB7 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
spi0m1_pins: spi0m1-pins {
|
|
rockchip,pins =
|
|
/* spi0_clk_m1 */
|
|
<3 RK_PB5 4 &pcfg_pull_none>,
|
|
/* spi0_miso_m1 */
|
|
<3 RK_PC0 4 &pcfg_pull_none>,
|
|
/* spi0_mosi_m1 */
|
|
<3 RK_PB4 4 &pcfg_pull_none>;
|
|
};
|
|
|
|
spi0m1_csn0: spi0m1-csn0 {
|
|
rockchip,pins =
|
|
/* spi0m1_csn0 */
|
|
<3 RK_PB7 4 &pcfg_pull_none>;
|
|
};
|
|
spi0m1_csn1: spi0m1-csn1 {
|
|
rockchip,pins =
|
|
/* spi0m1_csn1 */
|
|
<3 RK_PB6 4 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
spi1 {
|
|
spi1m0_pins: spi1m0-pins {
|
|
rockchip,pins =
|
|
/* spi1_clk_m0 */
|
|
<3 RK_PD6 4 &pcfg_pull_none>,
|
|
/* spi1_miso_m0 */
|
|
<4 RK_PA3 4 &pcfg_pull_none>,
|
|
/* spi1_mosi_m0 */
|
|
<4 RK_PA2 4 &pcfg_pull_none>;
|
|
};
|
|
|
|
spi1m0_csn0: spi1m0-csn0 {
|
|
rockchip,pins =
|
|
/* spi1m0_csn0 */
|
|
<3 RK_PD7 4 &pcfg_pull_none>;
|
|
};
|
|
spi1m0_csn1: spi1m0-csn1 {
|
|
rockchip,pins =
|
|
/* spi1m0_csn1 */
|
|
<4 RK_PA0 4 &pcfg_pull_none>;
|
|
};
|
|
|
|
spi1m1_pins: spi1m1-pins {
|
|
rockchip,pins =
|
|
/* spi1_clk_m1 */
|
|
<1 RK_PC0 4 &pcfg_pull_none>,
|
|
/* spi1_miso_m1 */
|
|
<1 RK_PB4 4 &pcfg_pull_none>,
|
|
/* spi1_mosi_m1 */
|
|
<1 RK_PB3 4 &pcfg_pull_none>;
|
|
};
|
|
|
|
spi1m1_csn0: spi1m1-csn0 {
|
|
rockchip,pins =
|
|
/* spi1m1_csn0 */
|
|
<1 RK_PB6 4 &pcfg_pull_none>;
|
|
};
|
|
spi1m1_csn1: spi1m1-csn1 {
|
|
rockchip,pins =
|
|
/* spi1m1_csn1 */
|
|
<1 RK_PB5 4 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
spi2 {
|
|
spi2m0_pins: spi2m0-pins {
|
|
rockchip,pins =
|
|
/* spi2_clk_m0 */
|
|
<4 RK_PB6 4 &pcfg_pull_none>,
|
|
/* spi2_miso_m0 */
|
|
<3 RK_PD2 4 &pcfg_pull_none>,
|
|
/* spi2_mosi_m0 */
|
|
<3 RK_PD3 4 &pcfg_pull_none>;
|
|
};
|
|
|
|
spi2m0_csn0: spi2m0-csn0 {
|
|
rockchip,pins =
|
|
/* spi2m0_csn0 */
|
|
<4 RK_PB5 4 &pcfg_pull_none>;
|
|
};
|
|
spi2m0_csn1: spi2m0-csn1 {
|
|
rockchip,pins =
|
|
/* spi2m0_csn1 */
|
|
<4 RK_PB4 4 &pcfg_pull_none>;
|
|
};
|
|
|
|
spi2m1_pins: spi2m1-pins {
|
|
rockchip,pins =
|
|
/* spi2_clk_m1 */
|
|
<2 RK_PA1 4 &pcfg_pull_none>,
|
|
/* spi2_miso_m1 */
|
|
<2 RK_PA0 4 &pcfg_pull_none>,
|
|
/* spi2_mosi_m1 */
|
|
<1 RK_PD7 4 &pcfg_pull_none>;
|
|
};
|
|
|
|
spi2m1_csn0: spi2m1-csn0 {
|
|
rockchip,pins =
|
|
/* spi2m1_csn0 */
|
|
<1 RK_PD6 4 &pcfg_pull_none>;
|
|
};
|
|
spi2m1_csn1: spi2m1-csn1 {
|
|
rockchip,pins =
|
|
/* spi2m1_csn1 */
|
|
<1 RK_PD5 4 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
tsadc {
|
|
tsadcm0_pins: tsadcm0-pins {
|
|
rockchip,pins =
|
|
/* tsadc_shut_m0 */
|
|
<0 RK_PA1 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
tsadcm1_pins: tsadcm1-pins {
|
|
rockchip,pins =
|
|
/* tsadc_shut_m1 */
|
|
<0 RK_PA2 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
tsadc_shut_org: tsadc-shut-org {
|
|
rockchip,pins =
|
|
/* tsadc_shut_org */
|
|
<0 RK_PA1 2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart0 {
|
|
uart0m0_xfer: uart0m0-xfer {
|
|
rockchip,pins =
|
|
/* uart0_rx_m0 */
|
|
<0 RK_PD0 1 &pcfg_pull_up>,
|
|
/* uart0_tx_m0 */
|
|
<0 RK_PD1 1 &pcfg_pull_up>;
|
|
};
|
|
|
|
uart0m1_xfer: uart0m1-xfer {
|
|
rockchip,pins =
|
|
/* uart0_rx_m1 */
|
|
<1 RK_PB3 2 &pcfg_pull_up>,
|
|
/* uart0_tx_m1 */
|
|
<1 RK_PB4 2 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
uart1 {
|
|
uart1m0_xfer: uart1m0-xfer {
|
|
rockchip,pins =
|
|
/* uart1_rx_m0 */
|
|
<1 RK_PD1 1 &pcfg_pull_up>,
|
|
/* uart1_tx_m0 */
|
|
<1 RK_PD2 1 &pcfg_pull_up>;
|
|
};
|
|
|
|
uart1m0_ctsn: uart1m0-ctsn {
|
|
rockchip,pins =
|
|
/* uart1m0_ctsn */
|
|
<1 RK_PD4 1 &pcfg_pull_none>;
|
|
};
|
|
uart1m0_rtsn: uart1m0-rtsn {
|
|
rockchip,pins =
|
|
/* uart1m0_rtsn */
|
|
<1 RK_PD3 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart1m1_xfer: uart1m1-xfer {
|
|
rockchip,pins =
|
|
/* uart1_rx_m1 */
|
|
<4 RK_PA6 3 &pcfg_pull_up>,
|
|
/* uart1_tx_m1 */
|
|
<4 RK_PA5 3 &pcfg_pull_up>;
|
|
};
|
|
|
|
uart1m1_ctsn: uart1m1-ctsn {
|
|
rockchip,pins =
|
|
/* uart1m1_ctsn */
|
|
<4 RK_PB0 3 &pcfg_pull_none>;
|
|
};
|
|
uart1m1_rtsn: uart1m1-rtsn {
|
|
rockchip,pins =
|
|
/* uart1m1_rtsn */
|
|
<4 RK_PA7 3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart2 {
|
|
uart2m0_xfer: uart2m0-xfer {
|
|
rockchip,pins =
|
|
/* uart2_rx_m0 */
|
|
<0 RK_PC1 1 &pcfg_pull_up>,
|
|
/* uart2_tx_m0 */
|
|
<0 RK_PC0 1 &pcfg_pull_up>;
|
|
};
|
|
|
|
uart2m0_ctsn: uart2m0-ctsn {
|
|
rockchip,pins =
|
|
/* uart2m0_ctsn */
|
|
<0 RK_PC2 1 &pcfg_pull_none>;
|
|
};
|
|
uart2m0_rtsn: uart2m0-rtsn {
|
|
rockchip,pins =
|
|
/* uart2m0_rtsn */
|
|
<0 RK_PC3 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart2m1_xfer: uart2m1-xfer {
|
|
rockchip,pins =
|
|
/* uart2_rx_m1 */
|
|
<3 RK_PA1 2 &pcfg_pull_up>,
|
|
/* uart2_tx_m1 */
|
|
<3 RK_PA0 2 &pcfg_pull_up>;
|
|
};
|
|
|
|
uart2m1_ctsn: uart2m1-ctsn {
|
|
rockchip,pins =
|
|
/* uart2m1_ctsn */
|
|
<3 RK_PA2 2 &pcfg_pull_none>;
|
|
};
|
|
uart2m1_rtsn: uart2m1-rtsn {
|
|
rockchip,pins =
|
|
/* uart2m1_rtsn */
|
|
<3 RK_PA3 2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart3 {
|
|
uart3m0_xfer: uart3m0-xfer {
|
|
rockchip,pins =
|
|
/* uart3_rx_m0 */
|
|
<4 RK_PB5 6 &pcfg_pull_up>,
|
|
/* uart3_tx_m0 */
|
|
<4 RK_PB4 6 &pcfg_pull_up>;
|
|
};
|
|
|
|
uart3m0_ctsn: uart3m0-ctsn {
|
|
rockchip,pins =
|
|
/* uart3m0_ctsn */
|
|
<4 RK_PB6 3 &pcfg_pull_none>;
|
|
};
|
|
uart3m0_rtsn: uart3m0-rtsn {
|
|
rockchip,pins =
|
|
/* uart3m0_rtsn */
|
|
<3 RK_PD1 4 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart3m1_xfer: uart3m1-xfer {
|
|
rockchip,pins =
|
|
/* uart3_rx_m1 */
|
|
<3 RK_PC0 3 &pcfg_pull_up>,
|
|
/* uart3_tx_m1 */
|
|
<3 RK_PB7 3 &pcfg_pull_up>;
|
|
};
|
|
|
|
uart3m1_ctsn: uart3m1-ctsn {
|
|
rockchip,pins =
|
|
/* uart3m1_ctsn */
|
|
<3 RK_PB6 3 &pcfg_pull_none>;
|
|
};
|
|
uart3m1_rtsn: uart3m1-rtsn {
|
|
rockchip,pins =
|
|
/* uart3m1_rtsn */
|
|
<3 RK_PC1 3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart4 {
|
|
uart4m0_xfer: uart4m0-xfer {
|
|
rockchip,pins =
|
|
/* uart4_rx_m0 */
|
|
<3 RK_PD1 3 &pcfg_pull_up>,
|
|
/* uart4_tx_m0 */
|
|
<3 RK_PD0 3 &pcfg_pull_up>;
|
|
};
|
|
|
|
uart4m0_ctsn: uart4m0-ctsn {
|
|
rockchip,pins =
|
|
/* uart4m0_ctsn */
|
|
<3 RK_PC5 3 &pcfg_pull_none>;
|
|
};
|
|
uart4m0_rtsn: uart4m0-rtsn {
|
|
rockchip,pins =
|
|
/* uart4m0_rtsn */
|
|
<3 RK_PC6 3 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart4m1_xfer: uart4m1-xfer {
|
|
rockchip,pins =
|
|
/* uart4_rx_m1 */
|
|
<1 RK_PD5 3 &pcfg_pull_up>,
|
|
/* uart4_tx_m1 */
|
|
<1 RK_PD6 3 &pcfg_pull_up>;
|
|
};
|
|
|
|
uart4m1_ctsn: uart4m1-ctsn {
|
|
rockchip,pins =
|
|
/* uart4m1_ctsn */
|
|
<2 RK_PA0 3 &pcfg_pull_none>;
|
|
};
|
|
uart4m1_rtsn: uart4m1-rtsn {
|
|
rockchip,pins =
|
|
/* uart4m1_rtsn */
|
|
<1 RK_PD7 3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart5 {
|
|
uart5m0_xfer: uart5m0-xfer {
|
|
rockchip,pins =
|
|
/* uart5_rx_m0 */
|
|
<1 RK_PB7 3 &pcfg_pull_up>,
|
|
/* uart5_tx_m0 */
|
|
<1 RK_PC0 3 &pcfg_pull_up>;
|
|
};
|
|
|
|
uart5m0_ctsn: uart5m0-ctsn {
|
|
rockchip,pins =
|
|
/* uart5m0_ctsn */
|
|
<1 RK_PB5 3 &pcfg_pull_none>;
|
|
};
|
|
uart5m0_rtsn: uart5m0-rtsn {
|
|
rockchip,pins =
|
|
/* uart5m0_rtsn */
|
|
<1 RK_PB6 3 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart5m1_xfer: uart5m1-xfer {
|
|
rockchip,pins =
|
|
/* uart5_rx_m1 */
|
|
<3 RK_PA7 5 &pcfg_pull_up>,
|
|
/* uart5_tx_m1 */
|
|
<3 RK_PA6 5 &pcfg_pull_up>;
|
|
};
|
|
|
|
uart5m1_ctsn: uart5m1-ctsn {
|
|
rockchip,pins =
|
|
/* uart5m1_ctsn */
|
|
<3 RK_PA0 5 &pcfg_pull_none>;
|
|
};
|
|
uart5m1_rtsn: uart5m1-rtsn {
|
|
rockchip,pins =
|
|
/* uart5m1_rtsn */
|
|
<3 RK_PA1 5 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart6 {
|
|
uart6m0_xfer: uart6m0-xfer {
|
|
rockchip,pins =
|
|
/* uart6_rx_m0 */
|
|
<0 RK_PC7 1 &pcfg_pull_up>,
|
|
/* uart6_tx_m0 */
|
|
<0 RK_PC6 1 &pcfg_pull_up>;
|
|
};
|
|
|
|
uart6m0_ctsn: uart6m0-ctsn {
|
|
rockchip,pins =
|
|
/* uart6m0_ctsn */
|
|
<0 RK_PC4 1 &pcfg_pull_none>;
|
|
};
|
|
uart6m0_rtsn: uart6m0-rtsn {
|
|
rockchip,pins =
|
|
/* uart6m0_rtsn */
|
|
<0 RK_PC5 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart6m1_xfer: uart6m1-xfer {
|
|
rockchip,pins =
|
|
/* uart6_rx_m1 */
|
|
<4 RK_PB0 5 &pcfg_pull_up>,
|
|
/* uart6_tx_m1 */
|
|
<4 RK_PA7 5 &pcfg_pull_up>;
|
|
};
|
|
|
|
uart6m1_ctsn: uart6m1-ctsn {
|
|
rockchip,pins =
|
|
/* uart6m1_ctsn */
|
|
<4 RK_PA2 3 &pcfg_pull_none>;
|
|
};
|
|
uart6m1_rtsn: uart6m1-rtsn {
|
|
rockchip,pins =
|
|
/* uart6m1_rtsn */
|
|
<4 RK_PA3 3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart7 {
|
|
uart7m0_xfer: uart7m0-xfer {
|
|
rockchip,pins =
|
|
/* uart7_rx_m0 */
|
|
<3 RK_PC7 3 &pcfg_pull_up>,
|
|
/* uart7_tx_m0 */
|
|
<3 RK_PC4 3 &pcfg_pull_up>;
|
|
};
|
|
|
|
uart7m0_ctsn: uart7m0-ctsn {
|
|
rockchip,pins =
|
|
/* uart7m0_ctsn */
|
|
<3 RK_PD2 3 &pcfg_pull_none>;
|
|
};
|
|
uart7m0_rtsn: uart7m0-rtsn {
|
|
rockchip,pins =
|
|
/* uart7m0_rtsn */
|
|
<3 RK_PD3 3 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart7m1_xfer: uart7m1-xfer {
|
|
rockchip,pins =
|
|
/* uart7_rx_m1 */
|
|
<1 RK_PB3 3 &pcfg_pull_up>,
|
|
/* uart7_tx_m1 */
|
|
<1 RK_PB4 3 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
uart8 {
|
|
uart8m0_xfer: uart8m0-xfer {
|
|
rockchip,pins =
|
|
/* uart8_rx_m0 */
|
|
<3 RK_PB3 3 &pcfg_pull_up>,
|
|
/* uart8_tx_m0 */
|
|
<3 RK_PB2 3 &pcfg_pull_up>;
|
|
};
|
|
|
|
uart8m0_ctsn: uart8m0-ctsn {
|
|
rockchip,pins =
|
|
/* uart8m0_ctsn */
|
|
<3 RK_PB4 3 &pcfg_pull_none>;
|
|
};
|
|
uart8m0_rtsn: uart8m0-rtsn {
|
|
rockchip,pins =
|
|
/* uart8m0_rtsn */
|
|
<3 RK_PB5 3 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart8m1_xfer: uart8m1-xfer {
|
|
rockchip,pins =
|
|
/* uart8_rx_m1 */
|
|
<3 RK_PD5 3 &pcfg_pull_up>,
|
|
/* uart8_tx_m1 */
|
|
<3 RK_PD4 3 &pcfg_pull_up>;
|
|
};
|
|
|
|
uart8m1_ctsn: uart8m1-ctsn {
|
|
rockchip,pins =
|
|
/* uart8m1_ctsn */
|
|
<3 RK_PD7 3 &pcfg_pull_none>;
|
|
};
|
|
uart8m1_rtsn: uart8m1-rtsn {
|
|
rockchip,pins =
|
|
/* uart8m1_rtsn */
|
|
<4 RK_PA0 3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart9 {
|
|
uart9m0_xfer: uart9m0-xfer {
|
|
rockchip,pins =
|
|
/* uart9_rx_m0 */
|
|
<4 RK_PB3 3 &pcfg_pull_up>,
|
|
/* uart9_tx_m0 */
|
|
<4 RK_PB2 3 &pcfg_pull_up>;
|
|
};
|
|
|
|
uart9m0_ctsn: uart9m0-ctsn {
|
|
rockchip,pins =
|
|
/* uart9m0_ctsn */
|
|
<4 RK_PB4 3 &pcfg_pull_none>;
|
|
};
|
|
uart9m0_rtsn: uart9m0-rtsn {
|
|
rockchip,pins =
|
|
/* uart9m0_rtsn */
|
|
<4 RK_PB5 3 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart9m1_xfer: uart9m1-xfer {
|
|
rockchip,pins =
|
|
/* uart9_rx_m1 */
|
|
<3 RK_PC3 3 &pcfg_pull_up>,
|
|
/* uart9_tx_m1 */
|
|
<3 RK_PC2 3 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
vo {
|
|
vo_pins: vo-pins {
|
|
rockchip,pins =
|
|
/* vo_lcdc_clk */
|
|
<4 RK_PB7 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d0 */
|
|
<4 RK_PA4 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d1 */
|
|
<4 RK_PA5 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d2 */
|
|
<4 RK_PB2 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d3 */
|
|
<3 RK_PC4 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d4 */
|
|
<3 RK_PC5 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d5 */
|
|
<3 RK_PC6 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d6 */
|
|
<3 RK_PC7 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d7 */
|
|
<3 RK_PD0 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d8 */
|
|
<4 RK_PA6 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d9 */
|
|
<4 RK_PA7 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d10 */
|
|
<3 RK_PD1 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d11 */
|
|
<3 RK_PD2 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d12 */
|
|
<3 RK_PD3 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d13 */
|
|
<3 RK_PD4 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d14 */
|
|
<3 RK_PD5 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d15 */
|
|
<3 RK_PD6 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d16 */
|
|
<4 RK_PB0 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d17 */
|
|
<4 RK_PB1 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d18 */
|
|
<4 RK_PB3 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d19 */
|
|
<3 RK_PD7 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d20 */
|
|
<4 RK_PA0 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d21 */
|
|
<4 RK_PA1 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d22 */
|
|
<4 RK_PA2 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_d23 */
|
|
<4 RK_PA3 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_den */
|
|
<4 RK_PB6 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_hsync */
|
|
<4 RK_PB4 1 &pcfg_pull_none>,
|
|
/* vo_lcdc_vsync */
|
|
<4 RK_PB5 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
};
|