463 lines
		
	
	
		
			6.4 KiB
		
	
	
	
		
			Plaintext
		
	
	
	
			
		
		
	
	
			463 lines
		
	
	
		
			6.4 KiB
		
	
	
	
		
			Plaintext
		
	
	
	
| /*
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|  * (C) Copyright 2020 Rockchip Electronics Co., Ltd
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|  *
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|  * SPDX-License-Identifier:     GPL-2.0+
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|  */
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| 
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| / {
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| 	aliases {
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| 		ethernet0 = &gmac0;
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| 		ethernet1 = &gmac1;
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| 		mmc0 = &sdhci;
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| 		mmc1 = &sdmmc0;
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| 		mmc2 = &sdmmc1;
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| 	};
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| 
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| 	chosen {
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| 		stdout-path = &uart2;
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| 		u-boot,spl-boot-order = &sdmmc0, &sdhci, &nandc0, &spi_nand, &spi_nor;
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| 	};
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| 
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| 	secure-otp@fe3a0000 {
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| 		compatible = "rockchip,rk3568-secure-otp";
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| 		reg = <0x0 0xfe3a0000 0x0 0x4000>;
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| 		secure_conf = <0xfdd18008>;
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| 		mask_addr = <0xfe880000>;
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| 		cru_rst_addr = <0xfdd20470>;
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| 		u-boot,dm-spl;
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| 	};
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| };
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| 
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| &psci {
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| 	u-boot,dm-pre-reloc;
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| 	status = "okay";
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| };
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| 
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| &crypto {
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| 	u-boot,dm-spl;
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| };
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| 
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| &uart2 {
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| 	clock-frequency = <24000000>;
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| 	u-boot,dm-spl;
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| 	/delete-property/ pinctrl-names;
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| 	/delete-property/ pinctrl-0;
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| 	status = "okay";
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| };
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| 
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| &grf {
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| 	u-boot,dm-spl;
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| 	status = "okay";
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| };
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| 
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| &pmugrf {
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| 	u-boot,dm-spl;
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| 	status = "okay";
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| };
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| 
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| &usb2phy0_grf {
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| 	u-boot,dm-pre-reloc;
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| 	status = "okay";
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| };
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| 
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| &usbdrd30 {
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| 	u-boot,dm-pre-reloc;
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| 	status = "okay";
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| };
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| 
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| &usbdrd_dwc3 {
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| 	u-boot,dm-pre-reloc;
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| 	status = "okay";
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| };
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| 
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| &usbhost30 {
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| 	u-boot,dm-pre-reloc;
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| 	status = "okay";
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| };
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| 
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| &usbhost_dwc3 {
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| 	u-boot,dm-pre-reloc;
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| 	status = "okay";
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| };
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| 
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| &usb2phy0 {
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| 	u-boot,dm-pre-reloc;
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| 	status = "okay";
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| };
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| 
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| &u2phy0_otg {
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| 	u-boot,dm-pre-reloc;
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| 	status = "okay";
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| };
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| 
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| &u2phy0_host {
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| 	u-boot,dm-pre-reloc;
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| 	status = "okay";
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| };
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| 
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| &cru {
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| 	u-boot,dm-spl;
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| 	status = "okay";
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| };
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| 
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| &pmucru {
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| 	u-boot,dm-spl;
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| 	status = "okay";
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| };
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| 
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| &rng {
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| 	u-boot,dm-pre-reloc;
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| 	status = "okay";
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| };
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| 
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| &sfc {
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| 	u-boot,dm-spl;
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| 	/delete-property/ pinctrl-names;
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| 	/delete-property/ pinctrl-0;
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| 	/delete-property/ assigned-clocks;
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| 	/delete-property/ assigned-clock-rates;
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| 	status = "okay";
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| 
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| 	#address-cells = <1>;
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| 	#size-cells = <0>;
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| 	spi_nand: flash@0 {
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| 		u-boot,dm-spl;
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| 		compatible = "spi-nand";
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| 		reg = <0>;
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| 		spi-tx-bus-width = <1>;
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| 		spi-rx-bus-width = <4>;
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| 		spi-max-frequency = <75000000>;
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| 	};
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| 
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| 	spi_nor: flash@1 {
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| 		u-boot,dm-spl;
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| 		compatible = "jedec,spi-nor";
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| 		label = "sfc_nor";
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| 		reg = <0>;
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| 		spi-tx-bus-width = <1>;
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| 		spi-rx-bus-width = <4>;
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| 		spi-max-frequency = <100000000>;
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| 	};
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| };
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| 
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| &saradc {
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| 	u-boot,dm-pre-reloc;
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| 	status = "okay";
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| };
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| 
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| &sdmmc0 {
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| 	u-boot,dm-spl;
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| 	status = "okay";
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| };
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| 
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| &sdmmc0_pins {
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| 	u-boot,dm-spl;
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| };
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| 
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| &sdmmc0_bus4 {
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| 	u-boot,dm-spl;
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| };
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| 
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| &sdmmc0_clk {
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| 	u-boot,dm-spl;
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| };
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| 
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| &sdmmc0_cmd {
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| 	u-boot,dm-spl;
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| };
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| 
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| &sdmmc0_det {
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| 	u-boot,dm-spl;
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| };
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| 
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| &sdmmc1 {
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| 	u-boot,dm-spl;
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| 	/delete-property/ pinctrl-names;
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| 	/delete-property/ pinctrl-0;
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| 	status = "okay";
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| };
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| 
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| &sdhci {
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| 	bus-width = <8>;
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| 	u-boot,dm-spl;
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| 	/delete-property/ pinctrl-names;
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| 	/delete-property/ pinctrl-0;
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| 	mmc-hs200-1_8v;
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| 	status = "okay";
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| };
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| 
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| &nandc0 {
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| 	u-boot,dm-spl;
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| 	status = "okay";
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| 	#address-cells = <1>;
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| 	#size-cells = <0>;
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| 	/delete-property/ pinctrl-names;
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| 	/delete-property/ pinctrl-0;
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| 
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| 	nand@0 {
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| 		u-boot,dm-spl;
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| 		reg = <0>;
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| 		nand-ecc-mode = "hw";
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| 		nand-ecc-strength = <16>;
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| 		nand-ecc-step-size = <1024>;
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| 	};
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| };
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| 
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| &gmac0_clkin {
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| 	u-boot,dm-pre-reloc;
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| };
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| 
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| &gmac1_clkin {
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| 	u-boot,dm-pre-reloc;
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| };
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| 
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| &gmac0 {
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| 	u-boot,dm-pre-reloc;
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| 	phy-mode = "rgmii";
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| 	clock_in_out = "output";
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| 
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| 	snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
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| 	snps,reset-active-low;
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| 	/* Reset time is 20ms, 100ms for rtl8211f */
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| 	snps,reset-delays-us = <0 20000 100000>;
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| 	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
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| 	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
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| 	assigned-clock-rates = <0>, <125000000>;
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| 
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| 	pinctrl-names = "default";
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| 	pinctrl-0 = <&gmac0_miim
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| 		     &gmac0_tx_bus2
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| 		     &gmac0_rx_bus2
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| 		     &gmac0_rgmii_clk
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| 		     &gmac0_rgmii_bus>;
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| 
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| 	tx_delay = <0x3c>;
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| 	rx_delay = <0x2f>;
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| 
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| 	phy-handle = <&rgmii_phy0>;
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| 	status = "disabled";
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| };
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| 
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| &gmac1 {
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| 	u-boot,dm-pre-reloc;
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| 	phy-mode = "rgmii";
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| 	clock_in_out = "output";
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| 
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| 	snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
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| 	snps,reset-active-low;
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| 	/* Reset time is 20ms, 100ms for rtl8211f */
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| 	snps,reset-delays-us = <0 20000 100000>;
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| 
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| 	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
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| 	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
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| 	assigned-clock-rates = <0>, <125000000>;
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| 
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| 	pinctrl-names = "default";
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| 	pinctrl-0 = <&gmac1m1_miim
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| 		     &gmac1m1_tx_bus2
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| 		     &gmac1m1_rx_bus2
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| 		     &gmac1m1_rgmii_clk
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| 		     &gmac1m1_rgmii_bus>;
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| 
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| 	tx_delay = <0x4f>;
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| 	rx_delay = <0x26>;
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| 
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| 	phy-handle = <&rgmii_phy1>;
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| 	status = "disabled";
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| };
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| 
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| &gmac0_stmmac_axi_setup {
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| 	u-boot,dm-pre-reloc;
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| };
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| 
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| &gmac0_mtl_rx_setup {
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| 	u-boot,dm-pre-reloc;
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| 	queue0 {
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| 		u-boot,dm-pre-reloc;
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| 	};
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| };
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| 
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| &gmac0_mtl_tx_setup {
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| 	u-boot,dm-pre-reloc;
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| 	queue0 {
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| 		u-boot,dm-pre-reloc;
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| 	};
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| };
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| 
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| &gmac1_stmmac_axi_setup {
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| 	u-boot,dm-pre-reloc;
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| };
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| 
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| &gmac1_mtl_rx_setup {
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| 	u-boot,dm-pre-reloc;
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| 	queue0 {
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| 		u-boot,dm-pre-reloc;
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| 	};
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| };
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| 
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| &gmac1_mtl_tx_setup {
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| 	u-boot,dm-pre-reloc;
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| 	queue0 {
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| 		u-boot,dm-pre-reloc;
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| 	};
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| };
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| 
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| &mdio0 {
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| 	u-boot,dm-pre-reloc;
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| 	rgmii_phy0: phy@0 {
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| 		compatible = "ethernet-phy-ieee802.3-c22";
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| 		u-boot,dm-pre-reloc;
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| 		reg = <0x0>;
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| 	};
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| };
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| 
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| &mdio1 {
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| 	u-boot,dm-pre-reloc;
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| 	rgmii_phy1: phy@0 {
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| 		compatible = "ethernet-phy-ieee802.3-c22";
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| 		u-boot,dm-pre-reloc;
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| 		reg = <0x0>;
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| 	};
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| };
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| 
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| &gmac0_miim {
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| 	u-boot,dm-pre-reloc;
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| };
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| 
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| &gmac0_clkinout {
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| 	u-boot,dm-pre-reloc;
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| };
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| 
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| &gmac0_rx_bus2 {
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| 	u-boot,dm-pre-reloc;
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| };
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| 
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| &gmac0_tx_bus2 {
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| 	u-boot,dm-pre-reloc;
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| };
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| 
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| &gmac0_rgmii_clk {
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| 	u-boot,dm-pre-reloc;
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| };
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| 
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| &gmac0_rgmii_bus {
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| 	u-boot,dm-pre-reloc;
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| };
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| 
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| &gmac1m1_miim {
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| 	u-boot,dm-pre-reloc;
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| };
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| 
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| &gmac1m1_clkinout {
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| 	u-boot,dm-pre-reloc;
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| };
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| 
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| &gmac1m1_rx_bus2 {
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| 	u-boot,dm-pre-reloc;
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| };
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| 
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| &gmac1m1_tx_bus2 {
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| 	u-boot,dm-pre-reloc;
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| };
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| 
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| &gmac1m1_rgmii_clk {
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| 	u-boot,dm-pre-reloc;
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| };
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| 
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| &gmac1m1_rgmii_bus {
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| 	u-boot,dm-pre-reloc;
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| };
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| 
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| ð0_clkout_pins {
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| 	u-boot,dm-pre-reloc;
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| };
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| 
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| ð1m1_clkout_pins {
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| 	u-boot,dm-pre-reloc;
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| };
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| 
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| &pcie30phy {
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| 	u-boot,dm-pre-reloc;
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| 	status = "okay";
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| };
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| 
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| &pcie3x2 {
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| 	u-boot,dm-pre-reloc;
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| 	status = "okay";
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| };
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| 
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| &pinctrl {
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| 	u-boot,dm-spl;
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| 	status = "okay";
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| };
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| 
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| &gpio0 {
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| 	u-boot,dm-spl;
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| };
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| 
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| &gpio1 {
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| 	u-boot,dm-spl;
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| };
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| 
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| &gpio2 {
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| 	u-boot,dm-spl;
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| };
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| 
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| &pcfg_pull_none_drv_level_1 {
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| 	u-boot,dm-spl;
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| };
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| 
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| &pcfg_pull_none_drv_level_2 {
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| 	u-boot,dm-spl;
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| };
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| 
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| 
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| &pcfg_pull_up_drv_level_1 {
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| 	u-boot,dm-spl;
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| };
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| 
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| &pcfg_pull_up_drv_level_2 {
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| 	u-boot,dm-spl;
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| };
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| 
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| &pcfg_pull_up {
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| 	u-boot,dm-spl;
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| };
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| 
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| &pcfg_pull_none {
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| 	u-boot,dm-spl;
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| };
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| 
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| &wdt {
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| 	u-boot,dm-pre-reloc;
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| 	status = "okay";
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| };
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| 
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| #if 0
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| &i2c0 {
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| 	u-boot,dm-pre-reloc;
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| 	status = "okay";
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| };
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| 
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| &i2c0_xfer {
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| 	u-boot,dm-pre-reloc;
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| 	status = "okay";
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| };
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| 
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| &i2c1 {
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| 	u-boot,dm-pre-reloc;
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| 	status = "okay";
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| };
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| 
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| &i2c1_xfer {
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| 	u-boot,dm-pre-reloc;
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| 	status = "okay";
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| };
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| 
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| &pcfg_pull_none_smt {
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| 	u-boot,dm-pre-reloc;
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| 	status = "okay";
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| };
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| #endif
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| 
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