1589 lines
36 KiB
Plaintext
1589 lines
36 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
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*/
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#include <dt-bindings/pinctrl/rockchip.h>
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#include "rockchip-pinconf.dtsi"
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&pinctrl {
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a7 {
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a7m0_pins: a7m0-pins {
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rockchip,pins =
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/* a7_jtag_tck_m0 */
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<1 RK_PA6 3 &pcfg_pull_none>,
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/* a7_jtag_tms_m0 */
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<1 RK_PA7 3 &pcfg_pull_none>;
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};
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a7m1_pins: a7m1-pins {
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rockchip,pins =
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/* a7_jtag_tck_m1 */
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<3 RK_PA2 2 &pcfg_pull_none>,
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/* a7_jtag_tms_m1 */
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<3 RK_PA3 2 &pcfg_pull_none>;
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};
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};
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acodec {
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acodec_pins: acodec-pins {
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rockchip,pins =
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/* acodec_adc_clk */
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<3 RK_PD1 4 &pcfg_pull_none>,
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/* acodec_adc_data */
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<3 RK_PD7 3 &pcfg_pull_none>,
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/* acodec_adc_sync */
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<3 RK_PD4 3 &pcfg_pull_none>,
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/* acodec_dac_clk */
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<3 RK_PD0 3 &pcfg_pull_none>,
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/* acodec_dac_datal */
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<3 RK_PD6 3 &pcfg_pull_none>,
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/* acodec_dac_datar */
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<3 RK_PD5 3 &pcfg_pull_none>,
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/* acodec_dac_sync */
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<3 RK_PD3 3 &pcfg_pull_none>;
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};
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};
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auddsm {
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auddsm_pins: auddsm-pins {
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rockchip,pins =
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/* auddsm_ln */
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<3 RK_PD3 5 &pcfg_pull_none>,
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/* auddsm_lp */
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<3 RK_PD5 5 &pcfg_pull_none>,
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/* auddsm_rn */
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<4 RK_PA0 5 &pcfg_pull_none>,
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/* auddsm_rp */
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<4 RK_PA1 5 &pcfg_pull_none>;
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};
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};
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audpwm {
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audpwmm0_pins: audpwmm0-pins {
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rockchip,pins =
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/* audpwm_l_m0 */
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<4 RK_PA0 3 &pcfg_pull_none>,
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/* audpwm_r_m0 */
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<4 RK_PA1 3 &pcfg_pull_none>;
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};
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audpwmm1_pins: audpwmm1-pins {
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rockchip,pins =
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/* audpwm_l_m1 */
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<3 RK_PD3 4 &pcfg_pull_none>,
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/* audpwm_r_m1 */
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<3 RK_PD5 4 &pcfg_pull_none>;
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};
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};
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can {
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canm0_pins: canm0-pins {
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rockchip,pins =
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/* can_rxd_m0 */
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<3 RK_PA0 3 &pcfg_pull_none>,
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/* can_txd_m0 */
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<3 RK_PA1 3 &pcfg_pull_none>;
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};
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canm1_pins: canm1-pins {
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rockchip,pins =
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/* can_rxd_m1 */
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<3 RK_PA6 5 &pcfg_pull_none>,
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/* can_txd_m1 */
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<3 RK_PA7 5 &pcfg_pull_none>;
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};
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};
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cif {
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cifm0_dvp_ctl: cifm0-dvp_ctl {
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rockchip,pins =
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/* cif_clkin_m0 */
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<3 RK_PC5 1 &pcfg_pull_none>,
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/* cif_clkout_m0 */
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<3 RK_PC6 1 &pcfg_pull_none>,
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/* cif_d0_m0 */
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<3 RK_PA4 1 &pcfg_pull_none>,
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/* cif_d10_m0 */
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<3 RK_PB6 1 &pcfg_pull_none>,
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/* cif_d11_m0 */
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<3 RK_PB7 1 &pcfg_pull_none>,
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/* cif_d12_m0 */
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<3 RK_PC0 1 &pcfg_pull_none>,
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/* cif_d13_m0 */
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<3 RK_PC1 1 &pcfg_pull_none>,
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/* cif_d14_m0 */
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<3 RK_PC2 1 &pcfg_pull_none>,
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/* cif_d15_m0 */
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<3 RK_PC3 1 &pcfg_pull_none>,
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/* cif_d1_m0 */
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<3 RK_PA5 1 &pcfg_pull_none>,
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/* cif_d2_m0 */
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<3 RK_PA6 1 &pcfg_pull_none>,
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/* cif_d3_m0 */
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<3 RK_PA7 1 &pcfg_pull_none>,
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/* cif_d4_m0 */
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<3 RK_PB0 1 &pcfg_pull_none>,
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/* cif_d5_m0 */
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<3 RK_PB1 1 &pcfg_pull_none>,
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/* cif_d6_m0 */
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<3 RK_PB2 1 &pcfg_pull_none>,
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/* cif_d7_m0 */
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<3 RK_PB3 1 &pcfg_pull_none>,
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/* cif_d8_m0 */
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<3 RK_PB4 1 &pcfg_pull_none>,
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/* cif_d9_m0 */
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<3 RK_PB5 1 &pcfg_pull_none>,
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/* cif_hsync_m0 */
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<3 RK_PC7 1 &pcfg_pull_none>,
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/* cif_vsync_m0 */
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<3 RK_PC4 1 &pcfg_pull_none>;
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};
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cifm1_dvp_ctl: cifm1-dvp_ctl {
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rockchip,pins =
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/* cif_clkin_m1 */
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<2 RK_PD2 3 &pcfg_pull_none>,
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/* cif_clkout_m1 */
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<2 RK_PD1 3 &pcfg_pull_none>,
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/* cif_d0_m1 */
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<2 RK_PA4 3 &pcfg_pull_none>,
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/* cif_d10_m1 */
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<2 RK_PC2 3 &pcfg_pull_none>,
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/* cif_d11_m1 */
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<2 RK_PC3 3 &pcfg_pull_none>,
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/* cif_d12_m1 */
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<2 RK_PC4 3 &pcfg_pull_none>,
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/* cif_d13_m1 */
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<2 RK_PC5 3 &pcfg_pull_none>,
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/* cif_d14_m1 */
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<2 RK_PC6 3 &pcfg_pull_none>,
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/* cif_d15_m1 */
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<2 RK_PC7 3 &pcfg_pull_none>,
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/* cif_d1_m1 */
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<2 RK_PA5 3 &pcfg_pull_none>,
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/* cif_d2_m1 */
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<2 RK_PA6 3 &pcfg_pull_none>,
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/* cif_d3_m1 */
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<2 RK_PB3 3 &pcfg_pull_none>,
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/* cif_d4_m1 */
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<2 RK_PB4 3 &pcfg_pull_none>,
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/* cif_d5_m1 */
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<2 RK_PB5 3 &pcfg_pull_none>,
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/* cif_d6_m1 */
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<2 RK_PB6 3 &pcfg_pull_none>,
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/* cif_d7_m1 */
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<2 RK_PB7 3 &pcfg_pull_none>,
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/* cif_d8_m1 */
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<2 RK_PC0 3 &pcfg_pull_none>,
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/* cif_d9_m1 */
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<2 RK_PC1 3 &pcfg_pull_none>,
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/* cif_hsync_m1 */
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<2 RK_PD3 3 &pcfg_pull_none>,
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/* cif_vsync_m1 */
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<2 RK_PD0 3 &pcfg_pull_none>;
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};
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};
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clk {
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clkm0_pins: clkm0-pins {
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rockchip,pins =
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/* clk_out_ethernet_m0 */
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<3 RK_PC5 2 &pcfg_pull_none>;
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};
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clkm1_pins: clkm1-pins {
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rockchip,pins =
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/* clk_out_ethernet_m1 */
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<2 RK_PC5 2 &pcfg_pull_none>;
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};
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clk_32k: clk-32k {
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rockchip,pins =
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<0 RK_PA2 1 &pcfg_pull_none>;
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};
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clk_ref: clk-ref {
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rockchip,pins =
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<0 RK_PA0 1 &pcfg_pull_none>;
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};
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};
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emmc {
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emmc_rstnout: emmc-rstnout {
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rockchip,pins =
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/* emmc_rstn */
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<1 RK_PA3 2 &pcfg_pull_none>;
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};
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emmc_bus8: emmc-bus8 {
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rockchip,pins =
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/* emmc_d0 */
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<0 RK_PC4 2 &pcfg_pull_up_drv_level_2>,
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/* emmc_d1 */
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<0 RK_PC5 2 &pcfg_pull_up_drv_level_2>,
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/* emmc_d2 */
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<0 RK_PC6 2 &pcfg_pull_up_drv_level_2>,
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/* emmc_d3 */
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<0 RK_PC7 2 &pcfg_pull_up_drv_level_2>,
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/* emmc_d4 */
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<0 RK_PD0 2 &pcfg_pull_up_drv_level_2>,
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/* emmc_d5 */
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<0 RK_PD1 2 &pcfg_pull_up_drv_level_2>,
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/* emmc_d6 */
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<0 RK_PD2 2 &pcfg_pull_up_drv_level_2>,
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/* emmc_d7 */
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<0 RK_PD3 2 &pcfg_pull_up_drv_level_2>;
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};
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emmc_clk: emmc-clk {
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rockchip,pins =
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/* emmc_clk */
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<0 RK_PD7 2 &pcfg_pull_up_drv_level_2>;
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};
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emmc_cmd: emmc-cmd {
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rockchip,pins =
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/* emmc_cmd */
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<0 RK_PD5 2 &pcfg_pull_up_drv_level_2>;
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};
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};
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flash {
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flash_pins: flash-pins {
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rockchip,pins =
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/* flash_ale */
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<1 RK_PA0 1 &pcfg_pull_none>,
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/* flash_cle */
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<0 RK_PD7 1 &pcfg_pull_none>,
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/* flash_cs0n */
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<0 RK_PD4 1 &pcfg_pull_none>,
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/* flash_d0 */
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<0 RK_PC4 1 &pcfg_pull_none>,
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/* flash_d1 */
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<0 RK_PC5 1 &pcfg_pull_none>,
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/* flash_d2 */
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<0 RK_PC6 1 &pcfg_pull_none>,
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/* flash_d3 */
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<0 RK_PC7 1 &pcfg_pull_none>,
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/* flash_d4 */
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<0 RK_PD0 1 &pcfg_pull_none>,
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/* flash_d5 */
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<0 RK_PD1 1 &pcfg_pull_none>,
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/* flash_d6 */
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<0 RK_PD2 1 &pcfg_pull_none>,
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/* flash_d7 */
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<0 RK_PD3 1 &pcfg_pull_none>,
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/* flash_rdn */
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<1 RK_PA2 1 &pcfg_pull_none>,
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/* flash_rdyn */
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<1 RK_PA1 1 &pcfg_pull_none>,
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/* flash_trig_in */
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<1 RK_PC5 4 &pcfg_pull_none>,
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/* flash_trig_out */
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<1 RK_PC4 4 &pcfg_pull_none>,
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/* flash_vol_sel */
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<0 RK_PB3 1 &pcfg_pull_none>,
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/* flash_wpn */
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<1 RK_PA3 1 &pcfg_pull_none>,
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/* flash_wrn */
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<0 RK_PD5 1 &pcfg_pull_none>;
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};
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};
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fspi {
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fspi_pins: fspi-pins {
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rockchip,pins =
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/* fspi_clk */
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<1 RK_PA3 3 &pcfg_pull_down>,
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/* fspi_cs0n */
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<0 RK_PD4 3 &pcfg_pull_up>,
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/* fspi_d0 */
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<1 RK_PA0 3 &pcfg_pull_up>,
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/* fspi_d1 */
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<1 RK_PA1 3 &pcfg_pull_up>,
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/* fspi_d2 */
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<0 RK_PD6 3 &pcfg_pull_up>,
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/* fspi_d3 */
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<1 RK_PA2 3 &pcfg_pull_up>;
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};
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fspi_cs1: fspi-cs1 {
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rockchip,pins =
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/* fspi_cs1n */
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<1 RK_PD1 3 &pcfg_pull_up>;
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};
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};
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i2c0 {
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i2c0_xfer: i2c0-xfer {
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rockchip,pins =
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/* i2c0_scl */
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<0 RK_PB4 1 &pcfg_pull_none_smt>,
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/* i2c0_sda */
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<0 RK_PB5 1 &pcfg_pull_none_smt>;
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};
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};
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i2c1 {
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i2c1_xfer: i2c1-xfer {
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rockchip,pins =
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/* i2c1_scl */
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<1 RK_PD3 1 &pcfg_pull_none_smt>,
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/* i2c1_sda */
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<1 RK_PD2 1 &pcfg_pull_none_smt>;
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};
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};
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i2c2 {
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i2c2_xfer: i2c2-xfer {
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rockchip,pins =
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/* i2c2_scl */
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<0 RK_PC2 1 &pcfg_pull_none_smt>,
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/* i2c2_sda */
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<0 RK_PC3 1 &pcfg_pull_none_smt>;
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};
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};
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i2c3 {
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i2c3m0_xfer: i2c3m0-xfer {
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rockchip,pins =
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/* i2c3_scl_m0 */
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<3 RK_PA4 5 &pcfg_pull_none_smt>,
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/* i2c3_sda_m0 */
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<3 RK_PA5 5 &pcfg_pull_none_smt>;
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};
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i2c3m1_xfer: i2c3m1-xfer {
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rockchip,pins =
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/* i2c3_scl_m1 */
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<2 RK_PD4 7 &pcfg_pull_none_smt>,
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/* i2c3_sda_m1 */
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<2 RK_PD5 7 &pcfg_pull_none_smt>;
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};
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i2c3m2_xfer: i2c3m2-xfer {
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rockchip,pins =
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/* i2c3_scl_m2 */
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<1 RK_PD6 3 &pcfg_pull_none_smt>,
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/* i2c3_sda_m2 */
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<1 RK_PD7 3 &pcfg_pull_none_smt>;
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};
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};
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i2c4 {
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i2c4m0_xfer: i2c4m0-xfer {
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rockchip,pins =
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/* i2c4_scl_m0 */
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<3 RK_PA0 7 &pcfg_pull_none_smt>,
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/* i2c4_sda_m0 */
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<3 RK_PA1 7 &pcfg_pull_none_smt>;
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};
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i2c4m1_xfer: i2c4m1-xfer {
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rockchip,pins =
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/* i2c4_scl_m1 */
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<4 RK_PA0 4 &pcfg_pull_none_smt>,
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/* i2c4_sda_m1 */
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<4 RK_PA1 4 &pcfg_pull_none_smt>;
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};
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};
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i2c5 {
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i2c5m0_xfer: i2c5m0-xfer {
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rockchip,pins =
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/* i2c5_scl_m0 */
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<2 RK_PA5 7 &pcfg_pull_none_smt>,
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/* i2c5_sda_m0 */
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<2 RK_PB3 7 &pcfg_pull_none_smt>;
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};
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i2c5m1_xfer: i2c5m1-xfer {
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rockchip,pins =
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/* i2c5_scl_m1 */
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<3 RK_PB0 5 &pcfg_pull_none_smt>,
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/* i2c5_sda_m1 */
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<3 RK_PB1 5 &pcfg_pull_none_smt>;
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};
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i2c5m2_xfer: i2c5m2-xfer {
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rockchip,pins =
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/* i2c5_scl_m2 */
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<1 RK_PD0 4 &pcfg_pull_none_smt>,
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/* i2c5_sda_m2 */
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<1 RK_PD1 4 &pcfg_pull_none_smt>;
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};
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};
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i2s0 {
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i2s0m0_lrck_rx: i2s0m0-lrck-rx {
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rockchip,pins =
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<3 RK_PD4 1 &pcfg_pull_none>;
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};
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i2s0m0_lrck_tx: i2s0m0-lrck-tx {
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rockchip,pins =
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<3 RK_PD3 1 &pcfg_pull_none>;
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};
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i2s0m0_mclk: i2s0m0-mclk {
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rockchip,pins =
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<3 RK_PD2 1 &pcfg_pull_none>;
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};
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i2s0m0_sclk_rx: i2s0m0-sclk-rx {
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rockchip,pins =
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<3 RK_PD1 1 &pcfg_pull_none>;
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};
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i2s0m0_sclk_tx: i2s0m0-sclk-tx {
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rockchip,pins =
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<3 RK_PD0 1 &pcfg_pull_none>;
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};
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i2s0m0_sdi0: i2s0m0-sdi0 {
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rockchip,pins =
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<3 RK_PD6 1 &pcfg_pull_none>;
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};
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i2s0m0_sdo0: i2s0m0-sdo0 {
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rockchip,pins =
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<3 RK_PD5 1 &pcfg_pull_none>;
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};
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i2s0m0_sdo1_sdi3: i2s0m0-sdo1-sdi3 {
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rockchip,pins =
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<3 RK_PD7 1 &pcfg_pull_none>;
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};
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i2s0m0_sdo2_sdi2: i2s0m0-sdo2-sdi2 {
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rockchip,pins =
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<4 RK_PA0 1 &pcfg_pull_none>;
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};
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i2s0m0_sdo3_sdi1: i2s0m0-sdo3-sdi1 {
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rockchip,pins =
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<4 RK_PA1 1 &pcfg_pull_none>;
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};
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i2s0m1_lrck_rx: i2s0m1-lrck-rx {
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rockchip,pins =
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<3 RK_PB2 3 &pcfg_pull_none>;
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};
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i2s0m1_lrck_tx: i2s0m1-lrck-tx {
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rockchip,pins =
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<3 RK_PA5 3 &pcfg_pull_none>;
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};
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i2s0m1_mclk: i2s0m1-mclk {
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rockchip,pins =
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<3 RK_PB0 3 &pcfg_pull_none>;
|
|
};
|
|
i2s0m1_sclk_rx: i2s0m1-sclk-rx {
|
|
rockchip,pins =
|
|
<3 RK_PB1 3 &pcfg_pull_none>;
|
|
};
|
|
i2s0m1_sclk_tx: i2s0m1-sclk-tx {
|
|
rockchip,pins =
|
|
<3 RK_PA4 3 &pcfg_pull_none>;
|
|
};
|
|
i2s0m1_sdi0: i2s0m1-sdi0 {
|
|
rockchip,pins =
|
|
<3 RK_PA7 3 &pcfg_pull_none>;
|
|
};
|
|
i2s0m1_sdo0: i2s0m1-sdo0 {
|
|
rockchip,pins =
|
|
<3 RK_PA6 3 &pcfg_pull_none>;
|
|
};
|
|
i2s0m1_sdo1_sdi3: i2s0m1-sdo1-sdi3 {
|
|
rockchip,pins =
|
|
<3 RK_PB3 3 &pcfg_pull_none>;
|
|
};
|
|
i2s0m1_sdo2_sdi2: i2s0m1-sdo2-sdi2 {
|
|
rockchip,pins =
|
|
<3 RK_PB4 3 &pcfg_pull_none>;
|
|
};
|
|
i2s0m1_sdo3_sdi1: i2s0m1-sdo3-sdi1 {
|
|
rockchip,pins =
|
|
<3 RK_PB5 3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
i2s1 {
|
|
i2s1m0_lrck: i2s1m0-lrck {
|
|
rockchip,pins =
|
|
<1 RK_PA0 4 &pcfg_pull_none>;
|
|
};
|
|
i2s1m0_mclk: i2s1m0-mclk {
|
|
rockchip,pins =
|
|
<0 RK_PD4 4 &pcfg_pull_none>;
|
|
};
|
|
i2s1m0_sclk: i2s1m0-sclk {
|
|
rockchip,pins =
|
|
<1 RK_PA1 4 &pcfg_pull_none>;
|
|
};
|
|
i2s1m0_sdi: i2s1m0-sdi {
|
|
rockchip,pins =
|
|
<1 RK_PA2 4 &pcfg_pull_none>;
|
|
};
|
|
i2s1m0_sdo: i2s1m0-sdo {
|
|
rockchip,pins =
|
|
<0 RK_PD6 4 &pcfg_pull_none>;
|
|
};
|
|
i2s1m1_lrck: i2s1m1-lrck {
|
|
rockchip,pins =
|
|
<1 RK_PD7 2 &pcfg_pull_none>;
|
|
};
|
|
i2s1m1_mclk: i2s1m1-mclk {
|
|
rockchip,pins =
|
|
<1 RK_PD5 2 &pcfg_pull_none>;
|
|
};
|
|
i2s1m1_sclk: i2s1m1-sclk {
|
|
rockchip,pins =
|
|
<1 RK_PD6 2 &pcfg_pull_none>;
|
|
};
|
|
i2s1m1_sdi: i2s1m1-sdi {
|
|
rockchip,pins =
|
|
<2 RK_PA0 2 &pcfg_pull_none>;
|
|
};
|
|
i2s1m1_sdo: i2s1m1-sdo {
|
|
rockchip,pins =
|
|
<2 RK_PA1 2 &pcfg_pull_none>;
|
|
};
|
|
i2s1m2_lrck: i2s1m2-lrck {
|
|
rockchip,pins =
|
|
<2 RK_PD2 6 &pcfg_pull_none>;
|
|
};
|
|
i2s1m2_mclk: i2s1m2-mclk {
|
|
rockchip,pins =
|
|
<2 RK_PC7 6 &pcfg_pull_none>;
|
|
};
|
|
i2s1m2_sclk: i2s1m2-sclk {
|
|
rockchip,pins =
|
|
<2 RK_PD1 6 &pcfg_pull_none>;
|
|
};
|
|
i2s1m2_sdi: i2s1m2-sdi {
|
|
rockchip,pins =
|
|
<2 RK_PD3 6 &pcfg_pull_none>;
|
|
};
|
|
i2s1m2_sdo: i2s1m2-sdo {
|
|
rockchip,pins =
|
|
<2 RK_PD0 6 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
i2s2 {
|
|
i2s2m0_lrck: i2s2m0-lrck {
|
|
rockchip,pins =
|
|
<1 RK_PC7 1 &pcfg_pull_none>;
|
|
};
|
|
i2s2m0_mclk: i2s2m0-mclk {
|
|
rockchip,pins =
|
|
<1 RK_PD0 1 &pcfg_pull_none>;
|
|
};
|
|
i2s2m0_sclk: i2s2m0-sclk {
|
|
rockchip,pins =
|
|
<1 RK_PC6 1 &pcfg_pull_none>;
|
|
};
|
|
i2s2m0_sdi: i2s2m0-sdi {
|
|
rockchip,pins =
|
|
<1 RK_PC5 1 &pcfg_pull_none>;
|
|
};
|
|
i2s2m0_sdo: i2s2m0-sdo {
|
|
rockchip,pins =
|
|
<1 RK_PC4 1 &pcfg_pull_none>;
|
|
};
|
|
i2s2m1_lrck: i2s2m1-lrck {
|
|
rockchip,pins =
|
|
<2 RK_PB2 2 &pcfg_pull_none>;
|
|
};
|
|
i2s2m1_mclk: i2s2m1-mclk {
|
|
rockchip,pins =
|
|
<2 RK_PB3 2 &pcfg_pull_none>;
|
|
};
|
|
i2s2m1_sclk: i2s2m1-sclk {
|
|
rockchip,pins =
|
|
<2 RK_PB1 2 &pcfg_pull_none>;
|
|
};
|
|
i2s2m1_sdi: i2s2m1-sdi {
|
|
rockchip,pins =
|
|
<2 RK_PB0 2 &pcfg_pull_none>;
|
|
};
|
|
i2s2m1_sdo: i2s2m1-sdo {
|
|
rockchip,pins =
|
|
<2 RK_PA7 2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
lcdc {
|
|
lcdc_ctl: lcdc-ctl {
|
|
rockchip,pins =
|
|
/* lcdc_clk */
|
|
<2 RK_PD7 1 &pcfg_pull_none>,
|
|
/* lcdc_d0 */
|
|
<2 RK_PA4 1 &pcfg_pull_none>,
|
|
/* lcdc_d1 */
|
|
<2 RK_PA5 1 &pcfg_pull_none>,
|
|
/* lcdc_d10 */
|
|
<2 RK_PB6 1 &pcfg_pull_none>,
|
|
/* lcdc_d11 */
|
|
<2 RK_PB7 1 &pcfg_pull_none>,
|
|
/* lcdc_d12 */
|
|
<2 RK_PC0 1 &pcfg_pull_none>,
|
|
/* lcdc_d13 */
|
|
<2 RK_PC1 1 &pcfg_pull_none>,
|
|
/* lcdc_d14 */
|
|
<2 RK_PC2 1 &pcfg_pull_none>,
|
|
/* lcdc_d15 */
|
|
<2 RK_PC3 1 &pcfg_pull_none>,
|
|
/* lcdc_d16 */
|
|
<2 RK_PC4 1 &pcfg_pull_none>,
|
|
/* lcdc_d17 */
|
|
<2 RK_PC5 1 &pcfg_pull_none>,
|
|
/* lcdc_d18 */
|
|
<2 RK_PC6 1 &pcfg_pull_none>,
|
|
/* lcdc_d19 */
|
|
<2 RK_PC7 1 &pcfg_pull_none>,
|
|
/* lcdc_d2 */
|
|
<2 RK_PA6 1 &pcfg_pull_none>,
|
|
/* lcdc_d20 */
|
|
<2 RK_PD0 1 &pcfg_pull_none>,
|
|
/* lcdc_d21 */
|
|
<2 RK_PD1 1 &pcfg_pull_none>,
|
|
/* lcdc_d22 */
|
|
<2 RK_PD2 1 &pcfg_pull_none>,
|
|
/* lcdc_d23 */
|
|
<2 RK_PD3 1 &pcfg_pull_none>,
|
|
/* lcdc_d3 */
|
|
<2 RK_PA7 1 &pcfg_pull_none>,
|
|
/* lcdc_d4 */
|
|
<2 RK_PB0 1 &pcfg_pull_none>,
|
|
/* lcdc_d5 */
|
|
<2 RK_PB1 1 &pcfg_pull_none>,
|
|
/* lcdc_d6 */
|
|
<2 RK_PB2 1 &pcfg_pull_none>,
|
|
/* lcdc_d7 */
|
|
<2 RK_PB3 1 &pcfg_pull_none>,
|
|
/* lcdc_d8 */
|
|
<2 RK_PB4 1 &pcfg_pull_none>,
|
|
/* lcdc_d9 */
|
|
<2 RK_PB5 1 &pcfg_pull_none>,
|
|
/* lcdc_den */
|
|
<2 RK_PD4 1 &pcfg_pull_none>,
|
|
/* lcdc_hsync */
|
|
<2 RK_PD5 1 &pcfg_pull_none>,
|
|
/* lcdc_vsync */
|
|
<2 RK_PD6 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
mcu {
|
|
mcu_pins: mcu-pins {
|
|
rockchip,pins =
|
|
/* mcu_jtag_tck */
|
|
<1 RK_PA6 4 &pcfg_pull_none>,
|
|
/* mcu_jtag_tdi */
|
|
<1 RK_PB1 4 &pcfg_pull_none>,
|
|
/* mcu_jtag_tdo */
|
|
<1 RK_PB0 4 &pcfg_pull_none>,
|
|
/* mcu_jtag_tms */
|
|
<1 RK_PA7 4 &pcfg_pull_none>,
|
|
/* mcu_jtag_trstn */
|
|
<1 RK_PA5 4 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
mipi {
|
|
mipim1_pins: mipim1-pins {
|
|
rockchip,pins =
|
|
/* mipi_csi_clk1_m1 */
|
|
<2 RK_PA2 1 &pcfg_pull_none>;
|
|
};
|
|
mipi_csi_clk0: mipi-csi-clk0 {
|
|
rockchip,pins =
|
|
<2 RK_PA3 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
pdm {
|
|
pdmm0_clk: pdmm0-clk {
|
|
rockchip,pins =
|
|
/* pdm_clk0_m0 */
|
|
<3 RK_PD4 2 &pcfg_pull_none>;
|
|
};
|
|
pdmm0_clk1: pdmm0-clk1 {
|
|
rockchip,pins =
|
|
<3 RK_PD1 2 &pcfg_pull_none>;
|
|
};
|
|
pdmm0_sdi0: pdmm0-sdi0 {
|
|
rockchip,pins =
|
|
<3 RK_PD6 2 &pcfg_pull_none>;
|
|
};
|
|
pdmm0_sdi1: pdmm0-sdi1 {
|
|
rockchip,pins =
|
|
<4 RK_PA1 2 &pcfg_pull_none>;
|
|
};
|
|
pdmm0_sdi2: pdmm0-sdi2 {
|
|
rockchip,pins =
|
|
<4 RK_PA0 2 &pcfg_pull_none>;
|
|
};
|
|
pdmm0_sdi3: pdmm0-sdi3 {
|
|
rockchip,pins =
|
|
<3 RK_PD7 2 &pcfg_pull_none>;
|
|
};
|
|
pdmm1_clk: pdmm1-clk {
|
|
rockchip,pins =
|
|
/* pdm_clk0_m1 */
|
|
<3 RK_PC0 3 &pcfg_pull_none>;
|
|
};
|
|
pdmm1_clk1: pdmm1-clk1 {
|
|
rockchip,pins =
|
|
<3 RK_PC3 3 &pcfg_pull_none>;
|
|
};
|
|
pdmm1_sdi0: pdmm1-sdi0 {
|
|
rockchip,pins =
|
|
<3 RK_PC1 3 &pcfg_pull_none>;
|
|
};
|
|
pdmm1_sdi1: pdmm1-sdi1 {
|
|
rockchip,pins =
|
|
<3 RK_PC2 3 &pcfg_pull_none>;
|
|
};
|
|
pdmm1_sdi2: pdmm1-sdi2 {
|
|
rockchip,pins =
|
|
<3 RK_PB6 3 &pcfg_pull_none>;
|
|
};
|
|
pdmm1_sdi3: pdmm1-sdi3 {
|
|
rockchip,pins =
|
|
<3 RK_PB7 3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
pmic {
|
|
pmic_pins: pmic-pins {
|
|
rockchip,pins =
|
|
/* pmic_int */
|
|
<0 RK_PB1 1 &pcfg_pull_none>,
|
|
/* pmic_sleep */
|
|
<0 RK_PB2 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
pmu {
|
|
pmu_pins: pmu-pins {
|
|
rockchip,pins =
|
|
/* pmu_debug */
|
|
<0 RK_PC1 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
prelight {
|
|
prelight_pins: prelight-pins {
|
|
rockchip,pins =
|
|
/* prelight_trig_out */
|
|
<1 RK_PC6 4 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
pwm0 {
|
|
pwm0m0_pins: pwm0m0-pins {
|
|
rockchip,pins =
|
|
/* pwm0_m0 */
|
|
<0 RK_PB6 3 &pcfg_pull_none>;
|
|
};
|
|
pwm0m0_pins_pull_down: pwm0m0-pins-pull-down {
|
|
rockchip,pins =
|
|
/* pwm0_m0 */
|
|
<0 RK_PB6 3 &pcfg_pull_down>;
|
|
};
|
|
pwm0m1_pins: pwm0m1-pins {
|
|
rockchip,pins =
|
|
/* pwm0_m1 */
|
|
<2 RK_PB3 5 &pcfg_pull_none>;
|
|
};
|
|
pwm0m1_pins_pull_down: pwm0m1-pins-pull-down {
|
|
rockchip,pins =
|
|
/* pwm0_m1 */
|
|
<2 RK_PB3 5 &pcfg_pull_down>;
|
|
};
|
|
};
|
|
pwm1 {
|
|
pwm1m0_pins: pwm1m0-pins {
|
|
rockchip,pins =
|
|
/* pwm1_m0 */
|
|
<0 RK_PB7 3 &pcfg_pull_none>;
|
|
};
|
|
pwm1m0_pins_pull_down: pwm1m0-pins-pull-down {
|
|
rockchip,pins =
|
|
/* pwm1_m0 */
|
|
<0 RK_PB7 3 &pcfg_pull_down>;
|
|
};
|
|
pwm1m1_pins: pwm1m1-pins {
|
|
rockchip,pins =
|
|
/* pwm1_m1 */
|
|
<2 RK_PB2 5 &pcfg_pull_none>;
|
|
};
|
|
pwm1m1_pins_pull_down: pwm1m1-pins-pull-down {
|
|
rockchip,pins =
|
|
/* pwm1_m1 */
|
|
<2 RK_PB2 5 &pcfg_pull_down>;
|
|
};
|
|
};
|
|
pwm10 {
|
|
pwm10m0_pins: pwm10m0-pins {
|
|
rockchip,pins =
|
|
/* pwm10_m0 */
|
|
<3 RK_PA6 6 &pcfg_pull_none>;
|
|
};
|
|
pwm10m0_pins_pull_down: pwm10m0-pins-pull-down {
|
|
rockchip,pins =
|
|
/* pwm10_m0 */
|
|
<3 RK_PA6 6 &pcfg_pull_down>;
|
|
};
|
|
pwm10m1_pins: pwm10m1-pins {
|
|
rockchip,pins =
|
|
/* pwm10_m1 */
|
|
<2 RK_PD5 5 &pcfg_pull_none>;
|
|
};
|
|
pwm10m1_pins_pull_down: pwm10m1-pins-pull-down {
|
|
rockchip,pins =
|
|
/* pwm10_m1 */
|
|
<2 RK_PD5 5 &pcfg_pull_down>;
|
|
};
|
|
};
|
|
pwm11 {
|
|
pwm11m0_pins: pwm11m0-pins {
|
|
rockchip,pins =
|
|
/* pwm11_ir_m0 */
|
|
<3 RK_PA7 6 &pcfg_pull_none>;
|
|
};
|
|
pwm11m0_pins_pull_down: pwm11m0-pins-pull-down {
|
|
rockchip,pins =
|
|
/* pwm11_ir_m0 */
|
|
<3 RK_PA7 6 &pcfg_pull_down>;
|
|
};
|
|
pwm11m1_pins: pwm11m1-pins {
|
|
rockchip,pins =
|
|
/* pwm11_ir_m1 */
|
|
<2 RK_PD4 5 &pcfg_pull_none>;
|
|
};
|
|
pwm11m1_pins_pull_down: pwm11m1-pins-pull-down {
|
|
rockchip,pins =
|
|
/* pwm11_ir_m1 */
|
|
<2 RK_PD4 5 &pcfg_pull_down>;
|
|
};
|
|
};
|
|
pwm2 {
|
|
pwm2m0_pins: pwm2m0-pins {
|
|
rockchip,pins =
|
|
/* pwm2_m0 */
|
|
<0 RK_PC0 3 &pcfg_pull_none>;
|
|
};
|
|
pwm2m0_pins_pull_down: pwm2m0-pins-pull-down {
|
|
rockchip,pins =
|
|
/* pwm2_m0 */
|
|
<0 RK_PC0 3 &pcfg_pull_down>;
|
|
};
|
|
pwm2m1_pins: pwm2m1-pins {
|
|
rockchip,pins =
|
|
/* pwm2_m1 */
|
|
<2 RK_PB1 5 &pcfg_pull_none>;
|
|
};
|
|
pwm2m1_pins_pull_down: pwm2m1-pins-pull-down {
|
|
rockchip,pins =
|
|
/* pwm2_m1 */
|
|
<2 RK_PB1 5 &pcfg_pull_down>;
|
|
};
|
|
};
|
|
pwm3 {
|
|
pwm3m0_pins: pwm3m0-pins {
|
|
rockchip,pins =
|
|
/* pwm3_ir_m0 */
|
|
<0 RK_PC1 3 &pcfg_pull_none>;
|
|
};
|
|
pwm3m0_pins_pull_down: pwm3m0-pins-pull-down {
|
|
rockchip,pins =
|
|
/* pwm3_ir_m0 */
|
|
<0 RK_PC1 3 &pcfg_pull_down>;
|
|
};
|
|
pwm3m1_pins: pwm3m1-pins {
|
|
rockchip,pins =
|
|
/* pwm3_ir_m1 */
|
|
<2 RK_PB0 5 &pcfg_pull_none>;
|
|
};
|
|
pwm3m1_pins_pull_down: pwm3m1-pins-pull-down {
|
|
rockchip,pins =
|
|
/* pwm3_ir_m1 */
|
|
<2 RK_PB0 5 &pcfg_pull_down>;
|
|
};
|
|
};
|
|
pwm4 {
|
|
pwm4m0_pins: pwm4m0-pins {
|
|
rockchip,pins =
|
|
/* pwm4_m0 */
|
|
<0 RK_PC2 3 &pcfg_pull_none>;
|
|
};
|
|
pwm4m0_pins_pull_down: pwm4m0-pins-pull-down {
|
|
rockchip,pins =
|
|
/* pwm4_m0 */
|
|
<0 RK_PC2 3 &pcfg_pull_down>;
|
|
};
|
|
pwm4m1_pins: pwm4m1-pins {
|
|
rockchip,pins =
|
|
/* pwm4_m1 */
|
|
<2 RK_PA7 5 &pcfg_pull_none>;
|
|
};
|
|
pwm4m1_pins_pull_down: pwm4m1-pins-pull-down {
|
|
rockchip,pins =
|
|
/* pwm4_m1 */
|
|
<2 RK_PA7 5 &pcfg_pull_down>;
|
|
};
|
|
};
|
|
pwm5 {
|
|
pwm5m0_pins: pwm5m0-pins {
|
|
rockchip,pins =
|
|
/* pwm5_m0 */
|
|
<0 RK_PC3 3 &pcfg_pull_none>;
|
|
};
|
|
pwm5m0_pins_pull_down: pwm5m0-pins-pull-down {
|
|
rockchip,pins =
|
|
/* pwm5_m0 */
|
|
<0 RK_PC3 3 &pcfg_pull_down>;
|
|
};
|
|
pwm5m1_pins: pwm5m1-pins {
|
|
rockchip,pins =
|
|
/* pwm5_m1 */
|
|
<2 RK_PA6 5 &pcfg_pull_none>;
|
|
};
|
|
pwm5m1_pins_pull_down: pwm5m1-pins-pull-down {
|
|
rockchip,pins =
|
|
/* pwm5_m1 */
|
|
<2 RK_PA6 5 &pcfg_pull_down>;
|
|
};
|
|
};
|
|
pwm6 {
|
|
pwm6m0_pins: pwm6m0-pins {
|
|
rockchip,pins =
|
|
/* pwm6_m0 */
|
|
<0 RK_PB2 3 &pcfg_pull_none>;
|
|
};
|
|
pwm6m0_pins_pull_down: pwm6m0-pins-pull-down {
|
|
rockchip,pins =
|
|
/* pwm6_m0 */
|
|
<0 RK_PB2 3 &pcfg_pull_down>;
|
|
};
|
|
pwm6m1_pins: pwm6m1-pins {
|
|
rockchip,pins =
|
|
/* pwm6_m1 */
|
|
<3 RK_PA1 5 &pcfg_pull_none>;
|
|
};
|
|
pwm6m1_pins_pull_up: pwm6m1-pins-pull-up {
|
|
rockchip,pins =
|
|
/* pwm6_m1 */
|
|
<3 RK_PA1 5 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
pwm7 {
|
|
pwm7m0_pins: pwm7m0-pins {
|
|
rockchip,pins =
|
|
/* pwm7_ir_m0 */
|
|
<0 RK_PB1 3 &pcfg_pull_none>;
|
|
};
|
|
pwm7m0_pins_pull_down: pwm7m0-pins-pull-down {
|
|
rockchip,pins =
|
|
/* pwm7_ir_m0 */
|
|
<0 RK_PB1 3 &pcfg_pull_down>;
|
|
};
|
|
pwm7m1_pins: pwm7m1-pins {
|
|
rockchip,pins =
|
|
/* pwm7_ir_m1 */
|
|
<3 RK_PA0 5 &pcfg_pull_none>;
|
|
};
|
|
pwm7m1_pins_pull_up: pwm7m1-pins-pull-up {
|
|
rockchip,pins =
|
|
/* pwm7_ir_m1 */
|
|
<3 RK_PA0 5 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
pwm8 {
|
|
pwm8m0_pins: pwm8m0-pins {
|
|
rockchip,pins =
|
|
/* pwm8_m0 */
|
|
<3 RK_PA4 6 &pcfg_pull_none>;
|
|
};
|
|
pwm8m0_pins_pull_down: pwm8m0-pins-pull-down {
|
|
rockchip,pins =
|
|
/* pwm8_m0 */
|
|
<3 RK_PA4 6 &pcfg_pull_down>;
|
|
};
|
|
pwm8m1_pins: pwm8m1-pins {
|
|
rockchip,pins =
|
|
/* pwm8_m1 */
|
|
<2 RK_PD7 5 &pcfg_pull_none>;
|
|
};
|
|
pwm8m1_pins_pull_down: pwm8m1-pins-pull-down {
|
|
rockchip,pins =
|
|
/* pwm8_m1 */
|
|
<2 RK_PD7 5 &pcfg_pull_down>;
|
|
};
|
|
};
|
|
pwm9 {
|
|
pwm9m0_pins: pwm9m0-pins {
|
|
rockchip,pins =
|
|
/* pwm9_m0 */
|
|
<3 RK_PA5 6 &pcfg_pull_none>;
|
|
};
|
|
pwm9m0_pins_pull_down: pwm9m0-pins-pull-down {
|
|
rockchip,pins =
|
|
/* pwm9_m0 */
|
|
<3 RK_PA5 6 &pcfg_pull_down>;
|
|
};
|
|
pwm9m1_pins: pwm9m1-pins {
|
|
rockchip,pins =
|
|
/* pwm9_m1 */
|
|
<2 RK_PD6 5 &pcfg_pull_none>;
|
|
};
|
|
pwm9m1_pins_pull_down: pwm9m1-pins-pull-down {
|
|
rockchip,pins =
|
|
/* pwm9_m1 */
|
|
<2 RK_PD6 5 &pcfg_pull_down>;
|
|
};
|
|
};
|
|
rgmii {
|
|
rgmiim0_pins: rgmiim0-pins {
|
|
rockchip,pins =
|
|
/* rgmii_clk_m0 */
|
|
<3 RK_PC0 2 &pcfg_pull_none>,
|
|
/* rgmii_mdc_m0 */
|
|
<3 RK_PC4 2 &pcfg_pull_none>,
|
|
/* rgmii_mdio_m0 */
|
|
<3 RK_PC3 2 &pcfg_pull_none>,
|
|
/* rgmii_rxclk_m0 */
|
|
<3 RK_PC7 2 &pcfg_pull_none>,
|
|
/* rgmii_rxd0_m0 */
|
|
<3 RK_PB6 2 &pcfg_pull_none>,
|
|
/* rgmii_rxd1_m0 */
|
|
<3 RK_PB7 2 &pcfg_pull_none>,
|
|
/* rgmii_rxd2_m0 */
|
|
<3 RK_PA7 2 &pcfg_pull_none>,
|
|
/* rgmii_rxd3_m0 */
|
|
<3 RK_PB0 2 &pcfg_pull_none>,
|
|
/* rgmii_rxdv_m0 */
|
|
<3 RK_PC1 2 &pcfg_pull_none>,
|
|
/* rgmii_txclk_m0 */
|
|
<3 RK_PC6 2 &pcfg_pull_none_drv_level_12>,
|
|
/* rgmii_txd0_m0 */
|
|
<3 RK_PB3 2 &pcfg_pull_none_drv_level_12>,
|
|
/* rgmii_txd1_m0 */
|
|
<3 RK_PB4 2 &pcfg_pull_none_drv_level_12>,
|
|
/* rgmii_txd2_m0 */
|
|
<3 RK_PB1 2 &pcfg_pull_none_drv_level_12>,
|
|
/* rgmii_txd3_m0 */
|
|
<3 RK_PB2 2 &pcfg_pull_none_drv_level_12>,
|
|
/* rgmii_txen_m0 */
|
|
<3 RK_PB5 2 &pcfg_pull_none_drv_level_12>;
|
|
};
|
|
rgmiim1_pins: rgmiim1-pins {
|
|
rockchip,pins =
|
|
/* rgmii_clk_m1 */
|
|
<2 RK_PB7 2 &pcfg_pull_none>,
|
|
/* rgmii_mdc_m1 */
|
|
<2 RK_PC2 2 &pcfg_pull_none>,
|
|
/* rgmii_mdio_m1 */
|
|
<2 RK_PC1 2 &pcfg_pull_none>,
|
|
/* rgmii_rxclk_m1 */
|
|
<2 RK_PD3 2 &pcfg_pull_none>,
|
|
/* rgmii_rxd0_m1 */
|
|
<2 RK_PB5 2 &pcfg_pull_none>,
|
|
/* rgmii_rxd1_m1 */
|
|
<2 RK_PB6 2 &pcfg_pull_none>,
|
|
/* rgmii_rxd2_m1 */
|
|
<2 RK_PC7 2 &pcfg_pull_none>,
|
|
/* rgmii_rxd3_m1 */
|
|
<2 RK_PD0 2 &pcfg_pull_none>,
|
|
/* rgmii_rxdv_m1 */
|
|
<2 RK_PB4 2 &pcfg_pull_none>,
|
|
/* rgmii_txclk_m1 */
|
|
<2 RK_PD2 2 &pcfg_pull_none_drv_level_12>,
|
|
/* rgmii_txd0_m1 */
|
|
<2 RK_PC3 2 &pcfg_pull_none_drv_level_12>,
|
|
/* rgmii_txd1_m1 */
|
|
<2 RK_PC4 2 &pcfg_pull_none_drv_level_12>,
|
|
/* rgmii_txd2_m1 */
|
|
<2 RK_PD1 2 &pcfg_pull_none_drv_level_12>,
|
|
/* rgmii_txd3_m1 */
|
|
<2 RK_PA4 2 &pcfg_pull_none_drv_level_12>,
|
|
/* rgmii_txen_m1 */
|
|
<2 RK_PC6 2 &pcfg_pull_none_drv_level_12>;
|
|
};
|
|
};
|
|
rmii {
|
|
rmiim0_pins: rmiim0-pins {
|
|
rockchip,pins =
|
|
/* rmii_clk_m0 */
|
|
<3 RK_PC0 2 &pcfg_pull_none>,
|
|
/* rmii_mdc_m0 */
|
|
<3 RK_PC4 2 &pcfg_pull_none>,
|
|
/* rmii_mdio_m0 */
|
|
<3 RK_PC3 2 &pcfg_pull_none>,
|
|
/* rmii_rxd0_m0 */
|
|
<3 RK_PB6 2 &pcfg_pull_none>,
|
|
/* rmii_rxd1_m0 */
|
|
<3 RK_PB7 2 &pcfg_pull_none>,
|
|
/* rmii_rxdv_m0 */
|
|
<3 RK_PC1 2 &pcfg_pull_none>,
|
|
/* rmii_rxer_m0 */
|
|
<3 RK_PC2 2 &pcfg_pull_none>,
|
|
/* rmii_txd0_m0 */
|
|
<3 RK_PB3 2 &pcfg_pull_none_drv_level_12>,
|
|
/* rmii_txd1_m0 */
|
|
<3 RK_PB4 2 &pcfg_pull_none_drv_level_12>,
|
|
/* rmii_txen_m0 */
|
|
<3 RK_PB5 2 &pcfg_pull_none_drv_level_12>;
|
|
};
|
|
rmiim1_pins: rmiim1-pins {
|
|
rockchip,pins =
|
|
/* rmii_clk_m1 */
|
|
<2 RK_PB7 2 &pcfg_pull_none>,
|
|
/* rmii_mdc_m1 */
|
|
<2 RK_PC2 2 &pcfg_pull_none>,
|
|
/* rmii_mdio_m1 */
|
|
<2 RK_PC1 2 &pcfg_pull_none>,
|
|
/* rmii_rxd0_m1 */
|
|
<2 RK_PB5 2 &pcfg_pull_none>,
|
|
/* rmii_rxd1_m1 */
|
|
<2 RK_PB6 2 &pcfg_pull_none>,
|
|
/* rmii_rxdv_m1 */
|
|
<2 RK_PB4 2 &pcfg_pull_none>,
|
|
/* rmii_rxer_m1 */
|
|
<2 RK_PC0 2 &pcfg_pull_none>,
|
|
/* rmii_txd0_m1 */
|
|
<2 RK_PC3 2 &pcfg_pull_none_drv_level_12>,
|
|
/* rmii_txd1_m1 */
|
|
<2 RK_PC4 2 &pcfg_pull_none_drv_level_12>,
|
|
/* rmii_txen_m1 */
|
|
<2 RK_PC6 2 &pcfg_pull_none_drv_level_12>;
|
|
};
|
|
};
|
|
clk_out_ethernet {
|
|
clk_out_ethernetm0_pins: clk-out-ethernetm0-pins {
|
|
rockchip,pins =
|
|
/* clk_out_ethernet_m0 */
|
|
<3 RK_PC5 2 &pcfg_pull_none>;
|
|
};
|
|
clk_out_ethernetm1_pins: clk-out-ethernetm1-pins {
|
|
rockchip,pins =
|
|
/* clk_out_ethernet_m1 */
|
|
<2 RK_PC5 2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
sdmmc0: sdmmc0 {
|
|
sdmmc0_bus4: sdmmc0-bus4 {
|
|
rockchip,pins =
|
|
/* sdmmc0_d0 */
|
|
<1 RK_PA4 1 &pcfg_pull_up_drv_level_2>,
|
|
/* sdmmc0_d1 */
|
|
<1 RK_PA5 1 &pcfg_pull_up_drv_level_2>,
|
|
/* sdmmc0_d2 */
|
|
<1 RK_PA6 1 &pcfg_pull_up_drv_level_2>,
|
|
/* sdmmc0_d3 */
|
|
<1 RK_PA7 1 &pcfg_pull_up_drv_level_2>;
|
|
};
|
|
sdmmc0_clk: sdmmc0-clk {
|
|
rockchip,pins =
|
|
/* sdmmc0_clk */
|
|
<1 RK_PB0 1 &pcfg_pull_up_drv_level_2>;
|
|
};
|
|
sdmmc0_cmd: sdmmc0-cmd {
|
|
rockchip,pins =
|
|
/* sdmmc0_cmd */
|
|
<1 RK_PB1 1 &pcfg_pull_up_drv_level_2>;
|
|
};
|
|
sdmmc0_det: sdmmc0-det {
|
|
rockchip,pins =
|
|
<0 RK_PA3 1 &pcfg_pull_none>;
|
|
};
|
|
sdmmc0_pwr: sdmmc0-pwr {
|
|
rockchip,pins =
|
|
<0 RK_PC0 1 &pcfg_pull_none>;
|
|
};
|
|
sdmmc0_idle_pins: sdmmc0-idle-pins {
|
|
rockchip,pins =
|
|
/* sdmmc0_d0 */
|
|
<1 RK_PA4 1 &pcfg_pull_down>,
|
|
/* sdmmc0_d1 */
|
|
<1 RK_PA5 1 &pcfg_pull_down>,
|
|
/* sdmmc0_d2 */
|
|
<1 RK_PA6 1 &pcfg_pull_down>,
|
|
/* sdmmc0_d3 */
|
|
<1 RK_PA7 1 &pcfg_pull_down>,
|
|
/* sdmmc0_clk */
|
|
<1 RK_PB0 1 &pcfg_pull_down>,
|
|
/* sdmmc0_cmd */
|
|
<1 RK_PB1 1 &pcfg_pull_down>;
|
|
};
|
|
};
|
|
sdmmc1: sdmmc1 {
|
|
sdmmc1_bus4: sdmmc1-bus4 {
|
|
rockchip,pins =
|
|
/* sdmmc1_d0 */
|
|
<1 RK_PB4 1 &pcfg_pull_up_drv_level_2>,
|
|
/* sdmmc1_d1 */
|
|
<1 RK_PB5 1 &pcfg_pull_up_drv_level_2>,
|
|
/* sdmmc1_d2 */
|
|
<1 RK_PB6 1 &pcfg_pull_up_drv_level_2>,
|
|
/* sdmmc1_d3 */
|
|
<1 RK_PB7 1 &pcfg_pull_up_drv_level_2>;
|
|
};
|
|
sdmmc1_clk: sdmmc1-clk {
|
|
rockchip,pins =
|
|
/* sdmmc1_clk */
|
|
<1 RK_PB2 1 &pcfg_pull_up_drv_level_2>;
|
|
};
|
|
sdmmc1_cmd: sdmmc1-cmd {
|
|
rockchip,pins =
|
|
/* sdmmc1_cmd */
|
|
<1 RK_PB3 1 &pcfg_pull_up_drv_level_2>;
|
|
};
|
|
sdmmc1_det: sdmmc1-det {
|
|
rockchip,pins =
|
|
<1 RK_PD0 2 &pcfg_pull_none>;
|
|
};
|
|
sdmmc1_pwr: sdmmc1-pwr {
|
|
rockchip,pins =
|
|
<1 RK_PD1 2 &pcfg_pull_none>;
|
|
};
|
|
sdmmc1_idle_pins: sdmmc1-idle-pins {
|
|
rockchip,pins =
|
|
/* sdmmc1_d0 */
|
|
<1 RK_PB4 1 &pcfg_pull_down>,
|
|
/* sdmmc1_d1 */
|
|
<1 RK_PB5 1 &pcfg_pull_down>,
|
|
/* sdmmc1_d2 */
|
|
<1 RK_PB6 1 &pcfg_pull_down>,
|
|
/* sdmmc1_d3 */
|
|
<1 RK_PB7 1 &pcfg_pull_down>,
|
|
/* sdmmc1_cmd */
|
|
<1 RK_PB3 1 &pcfg_pull_down>,
|
|
/* sdmmc1_clk */
|
|
<1 RK_PB2 1 &pcfg_pull_down>;
|
|
};
|
|
};
|
|
spi0 {
|
|
spi0m0_clk: spi0m0-clk {
|
|
rockchip,pins =
|
|
<0 RK_PB0 1 &pcfg_pull_none>;
|
|
};
|
|
spi0m0_cs0n: spi0m0-cs0n {
|
|
rockchip,pins =
|
|
<0 RK_PA5 1 &pcfg_pull_none>;
|
|
};
|
|
spi0m0_cs1n: spi0m0-cs1n {
|
|
rockchip,pins =
|
|
<0 RK_PA4 1 &pcfg_pull_none>;
|
|
};
|
|
spi0m0_miso: spi0m0-miso {
|
|
rockchip,pins =
|
|
<0 RK_PA7 1 &pcfg_pull_none>;
|
|
};
|
|
spi0m0_mosi: spi0m0-mosi {
|
|
rockchip,pins =
|
|
<0 RK_PA6 1 &pcfg_pull_none>;
|
|
};
|
|
spi0m0_clk_hs: spi0m0-clk_hs {
|
|
rockchip,pins =
|
|
<0 RK_PB0 1 &pcfg_pull_up_drv_level_2>;
|
|
};
|
|
spi0m0_miso_hs: spi0m0-miso_hs {
|
|
rockchip,pins =
|
|
<0 RK_PA7 1 &pcfg_pull_up_drv_level_2>;
|
|
};
|
|
spi0m0_mosi_hs: spi0m0-mosi_hs {
|
|
rockchip,pins =
|
|
<0 RK_PA6 1 &pcfg_pull_up_drv_level_2>;
|
|
};
|
|
spi0m1_clk: spi0m1-clk {
|
|
rockchip,pins =
|
|
<2 RK_PA1 1 &pcfg_pull_none>;
|
|
};
|
|
spi0m1_cs0n: spi0m1-cs0n {
|
|
rockchip,pins =
|
|
<2 RK_PA0 1 &pcfg_pull_none>;
|
|
};
|
|
spi0m1_cs1n: spi0m1-cs1n {
|
|
rockchip,pins =
|
|
<1 RK_PD5 1 &pcfg_pull_none>;
|
|
};
|
|
spi0m1_miso: spi0m1-miso {
|
|
rockchip,pins =
|
|
<1 RK_PD7 1 &pcfg_pull_none>;
|
|
};
|
|
spi0m1_mosi: spi0m1-mosi {
|
|
rockchip,pins =
|
|
<1 RK_PD6 1 &pcfg_pull_none>;
|
|
};
|
|
spi0m2_clk: spi0m2-clk {
|
|
rockchip,pins =
|
|
<2 RK_PB2 6 &pcfg_pull_none>;
|
|
};
|
|
spi0m2_cs0n: spi0m2-cs0n {
|
|
rockchip,pins =
|
|
<2 RK_PA7 6 &pcfg_pull_none>;
|
|
};
|
|
spi0m2_cs1n: spi0m2-cs1n {
|
|
rockchip,pins =
|
|
<2 RK_PB3 6 &pcfg_pull_none>;
|
|
};
|
|
spi0m2_miso: spi0m2-miso {
|
|
rockchip,pins =
|
|
<2 RK_PB1 6 &pcfg_pull_none>;
|
|
};
|
|
spi0m2_mosi: spi0m2-mosi {
|
|
rockchip,pins =
|
|
<2 RK_PB0 6 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
spi1 {
|
|
spi1m0_clk: spi1m0-clk {
|
|
rockchip,pins =
|
|
<3 RK_PC0 5 &pcfg_pull_none>;
|
|
};
|
|
spi1m0_cs0n: spi1m0-cs0n {
|
|
rockchip,pins =
|
|
<3 RK_PB5 5 &pcfg_pull_none>;
|
|
};
|
|
spi1m0_cs1n: spi1m0-cs1n {
|
|
rockchip,pins =
|
|
<3 RK_PB4 5 &pcfg_pull_none>;
|
|
};
|
|
spi1m0_miso: spi1m0-miso {
|
|
rockchip,pins =
|
|
<3 RK_PB7 5 &pcfg_pull_none>;
|
|
};
|
|
spi1m0_mosi: spi1m0-mosi {
|
|
rockchip,pins =
|
|
<3 RK_PB6 5 &pcfg_pull_none>;
|
|
};
|
|
spi1m0_clk_hs: spi1m0-clk_hs {
|
|
rockchip,pins =
|
|
<3 RK_PC0 5 &pcfg_pull_up_drv_level_2>;
|
|
};
|
|
spi1m0_miso_hs: spi1m0-miso_hs {
|
|
rockchip,pins =
|
|
<3 RK_PB7 5 &pcfg_pull_up_drv_level_2>;
|
|
};
|
|
spi1m0_mosi_hs: spi1m0-mosi_hs {
|
|
rockchip,pins =
|
|
<3 RK_PB6 5 &pcfg_pull_up_drv_level_2>;
|
|
};
|
|
spi1m1_clk: spi1m1-clk {
|
|
rockchip,pins =
|
|
<1 RK_PC6 3 &pcfg_pull_none>;
|
|
};
|
|
spi1m1_cs0n: spi1m1-cs0n {
|
|
rockchip,pins =
|
|
<1 RK_PC7 3 &pcfg_pull_none>;
|
|
};
|
|
spi1m1_cs1n: spi1m1-cs1n {
|
|
rockchip,pins =
|
|
<1 RK_PD0 3 &pcfg_pull_none>;
|
|
};
|
|
spi1m1_miso: spi1m1-miso {
|
|
rockchip,pins =
|
|
<1 RK_PC5 3 &pcfg_pull_none>;
|
|
};
|
|
spi1m1_mosi: spi1m1-mosi {
|
|
rockchip,pins =
|
|
<1 RK_PC4 3 &pcfg_pull_none>;
|
|
};
|
|
spi1m2_clk: spi1m2-clk {
|
|
rockchip,pins =
|
|
<2 RK_PD5 6 &pcfg_pull_none>;
|
|
};
|
|
spi1m2_cs0n: spi1m2-cs0n {
|
|
rockchip,pins =
|
|
<2 RK_PD4 6 &pcfg_pull_none>;
|
|
};
|
|
spi1m2_cs1n: spi1m2-cs1n {
|
|
rockchip,pins =
|
|
<3 RK_PA0 6 &pcfg_pull_none>;
|
|
};
|
|
spi1m2_miso: spi1m2-miso {
|
|
rockchip,pins =
|
|
<2 RK_PD7 6 &pcfg_pull_none>;
|
|
};
|
|
spi1m2_mosi: spi1m2-mosi {
|
|
rockchip,pins =
|
|
<2 RK_PD6 6 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
tsadc {
|
|
tsadcm0_pins: tsadcm0-pins {
|
|
rockchip,pins =
|
|
/* tsadc_shut_m0 */
|
|
<0 RK_PA1 1 &pcfg_pull_none>;
|
|
};
|
|
tsadcm1_pins: tsadcm1-pins {
|
|
rockchip,pins =
|
|
/* tsadc_shut_m1 */
|
|
<0 RK_PB2 2 &pcfg_pull_none>;
|
|
};
|
|
tsadc_shutorg: tsadc-shutorg {
|
|
rockchip,pins =
|
|
<0 RK_PA1 2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
uart0 {
|
|
uart0_xfer: uart0-xfer {
|
|
rockchip,pins =
|
|
/* uart0_rx */
|
|
<1 RK_PC2 1 &pcfg_pull_up>,
|
|
/* uart0_tx */
|
|
<1 RK_PC3 1 &pcfg_pull_up>;
|
|
};
|
|
uart0_ctsn: uart0-ctsn {
|
|
rockchip,pins =
|
|
<1 RK_PC1 1 &pcfg_pull_none>;
|
|
};
|
|
uart0_rtsn: uart0-rtsn {
|
|
rockchip,pins =
|
|
<1 RK_PC0 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
uart1 {
|
|
uart1m0_xfer: uart1m0-xfer {
|
|
rockchip,pins =
|
|
/* uart1_rx_m0 */
|
|
<0 RK_PB7 2 &pcfg_pull_up>,
|
|
/* uart1_tx_m0 */
|
|
<0 RK_PB6 2 &pcfg_pull_up>;
|
|
};
|
|
uart1m0_ctsn: uart1m0-ctsn {
|
|
rockchip,pins =
|
|
<0 RK_PC1 2 &pcfg_pull_none>;
|
|
};
|
|
uart1m0_rtsn: uart1m0-rtsn {
|
|
rockchip,pins =
|
|
<0 RK_PC0 2 &pcfg_pull_none>;
|
|
};
|
|
uart1m1_xfer: uart1m1-xfer {
|
|
rockchip,pins =
|
|
/* uart1_rx_m1 */
|
|
<1 RK_PD1 5 &pcfg_pull_up>,
|
|
/* uart1_tx_m1 */
|
|
<1 RK_PD0 5 &pcfg_pull_up>;
|
|
};
|
|
uart1m1_ctsn: uart1m1-ctsn {
|
|
rockchip,pins =
|
|
<1 RK_PC7 5 &pcfg_pull_none>;
|
|
};
|
|
uart1m1_rtsn: uart1m1-rtsn {
|
|
rockchip,pins =
|
|
<1 RK_PC6 5 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
uart2 {
|
|
uart2m0_xfer: uart2m0-xfer {
|
|
rockchip,pins =
|
|
/* uart2_rx_m0 */
|
|
<1 RK_PA4 3 &pcfg_pull_up>,
|
|
/* uart2_tx_m0 */
|
|
<1 RK_PA5 3 &pcfg_pull_up>;
|
|
};
|
|
uart2m1_xfer: uart2m1-xfer {
|
|
rockchip,pins =
|
|
/* uart2_rx_m1 */
|
|
<3 RK_PA3 1 &pcfg_pull_up>,
|
|
/* uart2_tx_m1 */
|
|
<3 RK_PA2 1 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
uart3 {
|
|
uart3m0_xfer: uart3m0-xfer {
|
|
rockchip,pins =
|
|
/* uart3_rx_m0 */
|
|
<3 RK_PC7 4 &pcfg_pull_up>,
|
|
/* uart3_tx_m0 */
|
|
<3 RK_PC6 4 &pcfg_pull_up>;
|
|
};
|
|
uart3m0_ctsn: uart3m0-ctsn {
|
|
rockchip,pins =
|
|
<3 RK_PC5 4 &pcfg_pull_none>;
|
|
};
|
|
uart3m0_rtsn: uart3m0-rtsn {
|
|
rockchip,pins =
|
|
<3 RK_PC4 4 &pcfg_pull_none>;
|
|
};
|
|
uart3m1_xfer: uart3m1-xfer {
|
|
rockchip,pins =
|
|
/* uart3_rx_m1 */
|
|
<1 RK_PA6 2 &pcfg_pull_up>,
|
|
/* uart3_tx_m1 */
|
|
<1 RK_PA7 2 &pcfg_pull_up>;
|
|
};
|
|
uart3m2_xfer: uart3m2-xfer {
|
|
rockchip,pins =
|
|
/* uart3_rx_m2 */
|
|
<3 RK_PA1 4 &pcfg_pull_up>,
|
|
/* uart3_tx_m2 */
|
|
<3 RK_PA0 4 &pcfg_pull_up>;
|
|
};
|
|
uart3m2_ctsn: uart3m2-ctsn {
|
|
rockchip,pins =
|
|
<2 RK_PD7 4 &pcfg_pull_none>;
|
|
};
|
|
uart3m2_rtsn: uart3m2-rtsn {
|
|
rockchip,pins =
|
|
<2 RK_PD6 4 &pcfg_pull_none>;
|
|
};
|
|
uart3_ctsn: uart3-ctsn {
|
|
rockchip,pins =
|
|
<1 RK_PB1 2 &pcfg_pull_none>;
|
|
};
|
|
uart3_rtsn: uart3-rtsn {
|
|
rockchip,pins =
|
|
<1 RK_PB0 2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
uart4 {
|
|
uart4m0_xfer: uart4m0-xfer {
|
|
rockchip,pins =
|
|
/* uart4_rx_m0 */
|
|
<3 RK_PA5 4 &pcfg_pull_up>,
|
|
/* uart4_tx_m0 */
|
|
<3 RK_PA4 4 &pcfg_pull_up>;
|
|
};
|
|
uart4m0_ctsn: uart4m0-ctsn {
|
|
rockchip,pins =
|
|
<3 RK_PB3 4 &pcfg_pull_none>;
|
|
};
|
|
uart4m0_rtsn: uart4m0-rtsn {
|
|
rockchip,pins =
|
|
<3 RK_PB2 4 &pcfg_pull_none>;
|
|
};
|
|
uart4m1_xfer: uart4m1-xfer {
|
|
rockchip,pins =
|
|
/* uart4_rx_m1 */
|
|
<2 RK_PA7 4 &pcfg_pull_up>,
|
|
/* uart4_tx_m1 */
|
|
<2 RK_PA6 4 &pcfg_pull_up>;
|
|
};
|
|
uart4m1_ctsn: uart4m1-ctsn {
|
|
rockchip,pins =
|
|
<2 RK_PA5 4 &pcfg_pull_none>;
|
|
};
|
|
uart4m1_rtsn: uart4m1-rtsn {
|
|
rockchip,pins =
|
|
<2 RK_PA4 4 &pcfg_pull_none>;
|
|
};
|
|
uart4m2_xfer: uart4m2-xfer {
|
|
rockchip,pins =
|
|
/* uart4_rx_m2 */
|
|
<1 RK_PD4 3 &pcfg_pull_up>,
|
|
/* uart4_tx_m2 */
|
|
<1 RK_PD5 3 &pcfg_pull_up>;
|
|
};
|
|
uart4m2_ctsn: uart4m2-ctsn {
|
|
rockchip,pins =
|
|
<1 RK_PD3 3 &pcfg_pull_none>;
|
|
};
|
|
uart4m2_rtsn: uart4m2-rtsn {
|
|
rockchip,pins =
|
|
<1 RK_PD2 3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
uart5 {
|
|
uart5m0_xfer: uart5m0-xfer {
|
|
rockchip,pins =
|
|
/* uart5_rx_m0 */
|
|
<3 RK_PA7 4 &pcfg_pull_up>,
|
|
/* uart5_tx_m0 */
|
|
<3 RK_PA6 4 &pcfg_pull_up>;
|
|
};
|
|
uart5m0_ctsn: uart5m0-ctsn {
|
|
rockchip,pins =
|
|
<3 RK_PB1 4 &pcfg_pull_none>;
|
|
};
|
|
uart5m0_rtsn: uart5m0-rtsn {
|
|
rockchip,pins =
|
|
<3 RK_PB0 4 &pcfg_pull_none>;
|
|
};
|
|
uart5m1_xfer: uart5m1-xfer {
|
|
rockchip,pins =
|
|
/* uart5_rx_m1 */
|
|
<2 RK_PB1 4 &pcfg_pull_up>,
|
|
/* uart5_tx_m1 */
|
|
<2 RK_PB0 4 &pcfg_pull_up>;
|
|
};
|
|
uart5m1_ctsn: uart5m1-ctsn {
|
|
rockchip,pins =
|
|
<2 RK_PB3 4 &pcfg_pull_none>;
|
|
};
|
|
uart5m1_rtsn: uart5m1-rtsn {
|
|
rockchip,pins =
|
|
<2 RK_PB2 4 &pcfg_pull_none>;
|
|
};
|
|
uart5m2_xfer: uart5m2-xfer {
|
|
rockchip,pins =
|
|
/* uart5_rx_m2 */
|
|
<2 RK_PA1 3 &pcfg_pull_up>,
|
|
/* uart5_tx_m2 */
|
|
<2 RK_PA0 3 &pcfg_pull_up>;
|
|
};
|
|
uart5m2_ctsn: uart5m2-ctsn {
|
|
rockchip,pins =
|
|
<2 RK_PA3 3 &pcfg_pull_none>;
|
|
};
|
|
uart5m2_rtsn: uart5m2-rtsn {
|
|
rockchip,pins =
|
|
<2 RK_PA2 3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
};
|