455 lines
12 KiB
Plaintext
455 lines
12 KiB
Plaintext
/*
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* Copyright (C) 2014 STMicroelectronics Limited.
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* Author: Peter Griffin <peter.griffin@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* publishhed by the Free Software Foundation.
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*/
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#include "stih410-clock.dtsi"
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#include "stih407-family.dtsi"
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#include "stih410-pinctrl.dtsi"
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/ {
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aliases {
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bdisp0 = &bdisp0;
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};
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cpus {
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cpu@0 {
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st,syscfg = <&syscfg_core 0x8e0>;
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st,syscfg-eng = <&syscfg_opp 0x4 0x0>;
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clocks = <&clk_m_a9>;
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operating-points-v2 = <&cpu0_opp_table>;
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};
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cpu@1 {
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clocks = <&clk_m_a9>;
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operating-points-v2 = <&cpu0_opp_table>;
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};
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};
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cpu0_opp_table: opp_table0 {
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compatible = "operating-points-v2";
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opp-shared;
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opp@1500000000 {
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opp-supported-hw = <0xffffffff 0xffffffff 0xffffffff>;
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opp-hz = /bits/ 64 <1500000000>;
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clock-latency-ns = <10000000>;
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opp-suspend;
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};
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opp@1200000000 {
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opp-supported-hw = <0xffffffff 0xffffffff 0xffffffff>;
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opp-hz = /bits/ 64 <1200000000>;
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clock-latency-ns = <10000000>;
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};
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opp@800000000 {
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opp-supported-hw = <0xffffffff 0xffffffff 0xffffffff>;
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opp-hz = /bits/ 64 <800000000>;
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clock-latency-ns = <10000000>;
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};
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opp@400000000 {
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opp-supported-hw = <0xffffffff 0xffffffff 0xffffffff>;
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opp-hz = /bits/ 64 <400000000>;
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clock-latency-ns = <10000000>;
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};
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};
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soc {
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syscfg_opp: @08a6583c {
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compatible = "syscon";
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reg = <0x08a6583c 0x8>;
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};
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usb2_picophy1: phy2 {
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compatible = "st,stih407-usb2-phy";
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#phy-cells = <0>;
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st,syscfg = <&syscfg_core 0xf8 0xf4>;
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resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
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<&picophyreset STIH407_PICOPHY0_RESET>;
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reset-names = "global", "port";
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status = "disabled";
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};
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usb2_picophy2: phy3 {
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compatible = "st,stih407-usb2-phy";
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#phy-cells = <0>;
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st,syscfg = <&syscfg_core 0xfc 0xf4>;
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resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
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<&picophyreset STIH407_PICOPHY1_RESET>;
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reset-names = "global", "port";
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status = "disabled";
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};
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ohci0: usb@9a03c00 {
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compatible = "st,st-ohci-300x";
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reg = <0x9a03c00 0x100>;
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interrupts = <GIC_SPI 180 IRQ_TYPE_NONE>;
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clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
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<&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
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resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
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<&softreset STIH407_USB2_PORT0_SOFTRESET>;
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reset-names = "power", "softreset";
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phys = <&usb2_picophy1>;
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phy-names = "usb";
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status = "disabled";
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};
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ehci0: usb@9a03e00 {
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compatible = "st,st-ehci-300x";
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reg = <0x9a03e00 0x100>;
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interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb0>;
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clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
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<&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
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resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
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<&softreset STIH407_USB2_PORT0_SOFTRESET>;
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reset-names = "power", "softreset";
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phys = <&usb2_picophy1>;
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phy-names = "usb";
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status = "disabled";
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};
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ohci1: usb@9a83c00 {
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compatible = "st,st-ohci-300x";
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reg = <0x9a83c00 0x100>;
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interrupts = <GIC_SPI 181 IRQ_TYPE_NONE>;
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clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
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<&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
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resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
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<&softreset STIH407_USB2_PORT1_SOFTRESET>;
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reset-names = "power", "softreset";
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phys = <&usb2_picophy2>;
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phy-names = "usb";
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status = "disabled";
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};
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ehci1: usb@9a83e00 {
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compatible = "st,st-ehci-300x";
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reg = <0x9a83e00 0x100>;
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interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb1>;
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clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
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<&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
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resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
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<&softreset STIH407_USB2_PORT1_SOFTRESET>;
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reset-names = "power", "softreset";
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phys = <&usb2_picophy2>;
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phy-names = "usb";
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status = "disabled";
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};
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sti-display-subsystem {
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compatible = "st,sti-display-subsystem";
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#address-cells = <1>;
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#size-cells = <1>;
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assigned-clocks = <&clk_s_d2_quadfs 0>,
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<&clk_s_d2_quadfs 1>,
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<&clk_s_c0_pll1 0>,
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<&clk_s_c0_flexgen CLK_COMPO_DVP>,
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<&clk_s_c0_flexgen CLK_MAIN_DISP>,
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<&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
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<&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
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<&clk_s_d2_flexgen CLK_PIX_GDP1>,
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<&clk_s_d2_flexgen CLK_PIX_GDP2>,
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<&clk_s_d2_flexgen CLK_PIX_GDP3>,
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<&clk_s_d2_flexgen CLK_PIX_GDP4>;
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assigned-clock-parents = <0>,
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<0>,
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<0>,
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<&clk_s_c0_pll1 0>,
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<&clk_s_c0_pll1 0>,
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<&clk_s_d2_quadfs 0>,
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<&clk_s_d2_quadfs 1>,
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<&clk_s_d2_quadfs 0>,
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<&clk_s_d2_quadfs 0>,
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<&clk_s_d2_quadfs 0>,
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<&clk_s_d2_quadfs 0>;
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assigned-clock-rates = <297000000>,
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<297000000>,
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<0>,
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<400000000>,
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<400000000>;
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ranges;
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sti-compositor@9d11000 {
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compatible = "st,stih407-compositor";
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reg = <0x9d11000 0x1000>;
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clock-names = "compo_main",
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"compo_aux",
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"pix_main",
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"pix_aux",
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"pix_gdp1",
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"pix_gdp2",
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"pix_gdp3",
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"pix_gdp4",
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"main_parent",
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"aux_parent";
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clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>,
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<&clk_s_c0_flexgen CLK_COMPO_DVP>,
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<&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
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<&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
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<&clk_s_d2_flexgen CLK_PIX_GDP1>,
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<&clk_s_d2_flexgen CLK_PIX_GDP2>,
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<&clk_s_d2_flexgen CLK_PIX_GDP3>,
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<&clk_s_d2_flexgen CLK_PIX_GDP4>,
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<&clk_s_d2_quadfs 0>,
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<&clk_s_d2_quadfs 1>;
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reset-names = "compo-main", "compo-aux";
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resets = <&softreset STIH407_COMPO_SOFTRESET>,
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<&softreset STIH407_COMPO_SOFTRESET>;
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st,vtg = <&vtg_main>, <&vtg_aux>;
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};
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sti-tvout@8d08000 {
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compatible = "st,stih407-tvout";
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reg = <0x8d08000 0x1000>;
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reg-names = "tvout-reg";
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reset-names = "tvout";
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resets = <&softreset STIH407_HDTVOUT_SOFTRESET>;
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#address-cells = <1>;
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#size-cells = <1>;
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assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
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<&clk_s_d2_flexgen CLK_TMDS_HDMI>,
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<&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
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<&clk_s_d0_flexgen CLK_PCM_0>,
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<&clk_s_d2_flexgen CLK_PIX_HDDAC>,
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<&clk_s_d2_flexgen CLK_HDDAC>;
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assigned-clock-parents = <&clk_s_d2_quadfs 0>,
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<&clk_tmdsout_hdmi>,
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<&clk_s_d2_quadfs 0>,
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<&clk_s_d0_quadfs 0>,
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<&clk_s_d2_quadfs 0>,
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<&clk_s_d2_quadfs 0>;
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};
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sti_hdmi: sti-hdmi@8d04000 {
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compatible = "st,stih407-hdmi";
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#sound-dai-cells = <0>;
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reg = <0x8d04000 0x1000>;
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reg-names = "hdmi-reg";
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interrupts = <GIC_SPI 106 IRQ_TYPE_NONE>;
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interrupt-names = "irq";
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clock-names = "pix",
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"tmds",
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"phy",
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"audio",
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"main_parent",
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"aux_parent";
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clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
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<&clk_s_d2_flexgen CLK_TMDS_HDMI>,
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<&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
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<&clk_s_d0_flexgen CLK_PCM_0>,
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<&clk_s_d2_quadfs 0>,
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<&clk_s_d2_quadfs 1>;
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hdmi,hpd-gpio = <&pio5 3>;
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reset-names = "hdmi";
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resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;
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ddc = <&hdmiddc>;
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};
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sti-hda@8d02000 {
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compatible = "st,stih407-hda";
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status = "disabled";
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reg = <0x8d02000 0x400>, <0x92b0120 0x4>;
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reg-names = "hda-reg", "video-dacs-ctrl";
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clock-names = "pix",
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"hddac",
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"main_parent",
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"aux_parent";
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clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
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<&clk_s_d2_flexgen CLK_HDDAC>,
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<&clk_s_d2_quadfs 0>,
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<&clk_s_d2_quadfs 1>;
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};
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sti-dvo@8d00400 {
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compatible = "st,stih407-dvo";
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status = "disabled";
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reg = <0x8d00400 0x200>;
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reg-names = "dvo-reg";
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clock-names = "dvo_pix",
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"dvo",
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"main_parent",
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"aux_parent";
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clocks = <&clk_s_d2_flexgen CLK_PIX_DVO>,
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<&clk_s_d2_flexgen CLK_DVO>,
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<&clk_s_d2_quadfs 0>,
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<&clk_s_d2_quadfs 1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_dvo>;
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};
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sti-hqvdp@9c000000 {
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compatible = "st,stih407-hqvdp";
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reg = <0x9C00000 0x100000>;
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clock-names = "hqvdp", "pix_main";
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clocks = <&clk_s_c0_flexgen CLK_MAIN_DISP>,
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<&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>;
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reset-names = "hqvdp";
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resets = <&softreset STIH407_HDQVDP_SOFTRESET>;
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st,vtg = <&vtg_main>;
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};
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};
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bdisp0:bdisp@9f10000 {
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compatible = "st,stih407-bdisp";
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reg = <0x9f10000 0x1000>;
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interrupts = <GIC_SPI 38 IRQ_TYPE_NONE>;
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clock-names = "bdisp";
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clocks = <&clk_s_c0_flexgen CLK_IC_BDISP_0>;
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};
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hva@8c85000 {
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compatible = "st,st-hva";
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reg = <0x8c85000 0x400>, <0x6000000 0x40000>;
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reg-names = "hva_registers", "hva_esram";
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interrupts = <GIC_SPI 58 IRQ_TYPE_NONE>,
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<GIC_SPI 59 IRQ_TYPE_NONE>;
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clock-names = "clk_hva";
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clocks = <&clk_s_c0_flexgen CLK_HVA>;
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};
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thermal@91a0000 {
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compatible = "st,stih407-thermal";
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reg = <0x91a0000 0x28>;
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clock-names = "thermal";
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clocks = <&clk_sysin>;
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interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>;
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};
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g1@8c80000 {
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compatible = "st,g1";
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reg = <0x8c80000 0x194>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_NONE>;
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};
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temp0{
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compatible = "st,stih407-thermal";
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reg = <0x91a0000 0x28>;
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clock-names = "thermal";
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clocks = <&clk_sysin>;
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interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>;
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};
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delta0 {
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compatible = "st,delta";
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clock-names = "delta", "delta-st231", "delta-flash-promip";
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clocks = <&clk_s_c0_flexgen CLK_VID_DMU>,
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<&clk_s_c0_flexgen CLK_ST231_DMU>,
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<&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
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};
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h264pp0: h264pp@8c00000 {
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compatible = "st,h264pp";
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reg = <0x8c00000 0x20000>;
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interrupts = <GIC_SPI 53 IRQ_TYPE_NONE>;
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clock-names = "clk_h264pp_0";
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clocks = <&clk_s_c0_flexgen CLK_PP_DMU>;
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};
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mali: mali@09f00000 {
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compatible = "arm,mali-400";
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reg = <0x09f00000 0x10000>;
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interrupts = <GIC_SPI 49 IRQ_TYPE_NONE>,
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<GIC_SPI 50 IRQ_TYPE_NONE>,
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<GIC_SPI 41 IRQ_TYPE_NONE>,
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<GIC_SPI 45 IRQ_TYPE_NONE>,
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<GIC_SPI 42 IRQ_TYPE_NONE>,
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<GIC_SPI 46 IRQ_TYPE_NONE>,
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<GIC_SPI 43 IRQ_TYPE_NONE>,
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<GIC_SPI 47 IRQ_TYPE_NONE>,
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<GIC_SPI 44 IRQ_TYPE_NONE>,
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<GIC_SPI 48 IRQ_TYPE_NONE>;
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interrupt-names = "IRQGP",
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"IRQGPMMU",
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"IRQPP0",
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"IRQPPMMU0",
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"IRQPP1",
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"IRQPPMMU1",
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"IRQPP2",
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"IRQPPMMU2",
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"IRQPP3",
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"IRQPPMMU3";
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clock-names = "gpu-clk";
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clocks = <&clk_s_c0_flexgen CLK_ICN_GPU>;
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reset-names = "gpu";
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resets = <&softreset STIH407_GPU_SOFTRESET>;
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};
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delta0 {
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compatible = "st,st-delta";
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clock-names = "delta",
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"delta-st231",
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"delta-flash-promip";
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clocks = <&clk_s_c0_flexgen CLK_VID_DMU>,
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<&clk_s_c0_flexgen CLK_ST231_DMU>,
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<&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
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};
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h264pp0: h264pp@8c00000 {
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compatible = "st,h264pp";
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reg = <0x8c00000 0x20000>;
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interrupts = <GIC_SPI 53 IRQ_TYPE_NONE>;
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clock-names = "clk_h264pp_0";
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clocks = <&clk_s_c0_flexgen CLK_PP_DMU>;
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};
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mali: mali@09f00000 {
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compatible = "arm,mali-400";
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reg = <0x09f00000 0x10000>;
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interrupts = <GIC_SPI 49 IRQ_TYPE_NONE>,
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<GIC_SPI 50 IRQ_TYPE_NONE>,
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<GIC_SPI 41 IRQ_TYPE_NONE>,
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<GIC_SPI 45 IRQ_TYPE_NONE>,
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<GIC_SPI 42 IRQ_TYPE_NONE>,
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<GIC_SPI 46 IRQ_TYPE_NONE>,
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<GIC_SPI 43 IRQ_TYPE_NONE>,
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<GIC_SPI 47 IRQ_TYPE_NONE>,
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<GIC_SPI 44 IRQ_TYPE_NONE>,
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<GIC_SPI 48 IRQ_TYPE_NONE>;
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interrupt-names = "IRQGP",
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"IRQGPMMU",
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"IRQPP0",
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"IRQPPMMU0",
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"IRQPP1",
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"IRQPPMMU1",
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"IRQPP2",
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"IRQPPMMU2",
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"IRQPP3",
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"IRQPPMMU3";
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clock-names = "gpu-clk";
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clocks = <&clk_s_c0_flexgen CLK_ICN_GPU>;
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reset-names = "gpu";
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resets = <&softreset STIH407_GPU_SOFTRESET>;
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};
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hva@8c85000{
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compatible = "st,st-hva";
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reg = <0x8c85000 0x400>, <0x6000000 0x40000>;
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reg-names = "hva_registers", "hva_esram";
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interrupts = <GIC_SPI 58 IRQ_TYPE_NONE>,
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<GIC_SPI 59 IRQ_TYPE_NONE>;
|
|
clock-names = "clk_hva";
|
|
clocks = <&clk_s_c0_flexgen CLK_HVA>;
|
|
};
|
|
};
|
|
};
|