736 lines
28 KiB
C++
736 lines
28 KiB
C++
/*
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* Copyright (C) 2016 The Android Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "jni_macro_assembler_x86.h"
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#include "base/casts.h"
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#include "entrypoints/quick/quick_entrypoints.h"
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#include "lock_word.h"
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#include "thread.h"
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#include "utils/assembler.h"
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namespace art {
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namespace x86 {
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static Register GetScratchRegister() {
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// ECX is an argument register on entry and gets spilled in BuildFrame().
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// After that, we can use it as a scratch register.
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return ECX;
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}
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static dwarf::Reg DWARFReg(Register reg) {
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return dwarf::Reg::X86Core(static_cast<int>(reg));
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}
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constexpr size_t kFramePointerSize = 4;
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static constexpr size_t kNativeStackAlignment = 16;
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static_assert(kNativeStackAlignment == kStackAlignment);
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#define __ asm_.
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void X86JNIMacroAssembler::BuildFrame(size_t frame_size,
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ManagedRegister method_reg,
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ArrayRef<const ManagedRegister> spill_regs) {
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DCHECK_EQ(CodeSize(), 0U); // Nothing emitted yet.
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cfi().SetCurrentCFAOffset(4); // Return address on stack.
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if (frame_size == kFramePointerSize) {
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// For @CriticalNative tail call.
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CHECK(method_reg.IsNoRegister());
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CHECK(spill_regs.empty());
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} else if (method_reg.IsNoRegister()) {
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CHECK_ALIGNED(frame_size, kNativeStackAlignment);
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} else {
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CHECK_ALIGNED(frame_size, kStackAlignment);
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}
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int gpr_count = 0;
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for (int i = spill_regs.size() - 1; i >= 0; --i) {
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Register spill = spill_regs[i].AsX86().AsCpuRegister();
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__ pushl(spill);
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gpr_count++;
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cfi().AdjustCFAOffset(kFramePointerSize);
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cfi().RelOffset(DWARFReg(spill), 0);
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}
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// return address then method on stack.
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int32_t adjust = frame_size - gpr_count * kFramePointerSize -
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kFramePointerSize /*return address*/ -
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(method_reg.IsRegister() ? kFramePointerSize /*method*/ : 0u);
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if (adjust != 0) {
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__ addl(ESP, Immediate(-adjust));
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cfi().AdjustCFAOffset(adjust);
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}
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if (method_reg.IsRegister()) {
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__ pushl(method_reg.AsX86().AsCpuRegister());
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cfi().AdjustCFAOffset(kFramePointerSize);
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}
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DCHECK_EQ(static_cast<size_t>(cfi().GetCurrentCFAOffset()), frame_size);
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}
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void X86JNIMacroAssembler::RemoveFrame(size_t frame_size,
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ArrayRef<const ManagedRegister> spill_regs,
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bool may_suspend ATTRIBUTE_UNUSED) {
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CHECK_ALIGNED(frame_size, kNativeStackAlignment);
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cfi().RememberState();
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// -kFramePointerSize for ArtMethod*.
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int adjust = frame_size - spill_regs.size() * kFramePointerSize - kFramePointerSize;
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if (adjust != 0) {
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__ addl(ESP, Immediate(adjust));
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cfi().AdjustCFAOffset(-adjust);
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}
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for (size_t i = 0; i < spill_regs.size(); ++i) {
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Register spill = spill_regs[i].AsX86().AsCpuRegister();
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__ popl(spill);
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cfi().AdjustCFAOffset(-static_cast<int>(kFramePointerSize));
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cfi().Restore(DWARFReg(spill));
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}
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__ ret();
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// The CFI should be restored for any code that follows the exit block.
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cfi().RestoreState();
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cfi().DefCFAOffset(frame_size);
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}
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void X86JNIMacroAssembler::IncreaseFrameSize(size_t adjust) {
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if (adjust != 0u) {
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CHECK_ALIGNED(adjust, kNativeStackAlignment);
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__ addl(ESP, Immediate(-adjust));
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cfi().AdjustCFAOffset(adjust);
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}
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}
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static void DecreaseFrameSizeImpl(X86Assembler* assembler, size_t adjust) {
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if (adjust != 0u) {
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CHECK_ALIGNED(adjust, kNativeStackAlignment);
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assembler->addl(ESP, Immediate(adjust));
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assembler->cfi().AdjustCFAOffset(-adjust);
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}
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}
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ManagedRegister X86JNIMacroAssembler::CoreRegisterWithSize(ManagedRegister src, size_t size) {
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DCHECK(src.AsX86().IsCpuRegister());
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DCHECK_EQ(size, 4u);
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return src;
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}
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void X86JNIMacroAssembler::DecreaseFrameSize(size_t adjust) {
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DecreaseFrameSizeImpl(&asm_, adjust);
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}
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void X86JNIMacroAssembler::Store(FrameOffset offs, ManagedRegister msrc, size_t size) {
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Store(X86ManagedRegister::FromCpuRegister(ESP), MemberOffset(offs.Int32Value()), msrc, size);
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}
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void X86JNIMacroAssembler::Store(ManagedRegister mbase,
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MemberOffset offs,
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ManagedRegister msrc,
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size_t size) {
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X86ManagedRegister base = mbase.AsX86();
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X86ManagedRegister src = msrc.AsX86();
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if (src.IsNoRegister()) {
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CHECK_EQ(0u, size);
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} else if (src.IsCpuRegister()) {
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CHECK_EQ(4u, size);
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__ movl(Address(base.AsCpuRegister(), offs), src.AsCpuRegister());
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} else if (src.IsRegisterPair()) {
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CHECK_EQ(8u, size);
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__ movl(Address(base.AsCpuRegister(), offs), src.AsRegisterPairLow());
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__ movl(Address(base.AsCpuRegister(), FrameOffset(offs.Int32Value()+4)),
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src.AsRegisterPairHigh());
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} else if (src.IsX87Register()) {
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if (size == 4) {
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__ fstps(Address(base.AsCpuRegister(), offs));
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} else {
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__ fstpl(Address(base.AsCpuRegister(), offs));
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}
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} else {
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CHECK(src.IsXmmRegister());
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if (size == 4) {
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__ movss(Address(base.AsCpuRegister(), offs), src.AsXmmRegister());
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} else {
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__ movsd(Address(base.AsCpuRegister(), offs), src.AsXmmRegister());
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}
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}
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}
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void X86JNIMacroAssembler::StoreRef(FrameOffset dest, ManagedRegister msrc) {
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X86ManagedRegister src = msrc.AsX86();
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CHECK(src.IsCpuRegister());
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__ movl(Address(ESP, dest), src.AsCpuRegister());
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}
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void X86JNIMacroAssembler::StoreRawPtr(FrameOffset dest, ManagedRegister msrc) {
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X86ManagedRegister src = msrc.AsX86();
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CHECK(src.IsCpuRegister());
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__ movl(Address(ESP, dest), src.AsCpuRegister());
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}
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void X86JNIMacroAssembler::StoreImmediateToFrame(FrameOffset dest, uint32_t imm) {
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__ movl(Address(ESP, dest), Immediate(imm));
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}
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void X86JNIMacroAssembler::StoreStackOffsetToThread(ThreadOffset32 thr_offs, FrameOffset fr_offs) {
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Register scratch = GetScratchRegister();
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__ leal(scratch, Address(ESP, fr_offs));
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__ fs()->movl(Address::Absolute(thr_offs), scratch);
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}
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void X86JNIMacroAssembler::StoreStackPointerToThread(ThreadOffset32 thr_offs) {
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__ fs()->movl(Address::Absolute(thr_offs), ESP);
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}
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void X86JNIMacroAssembler::StoreSpanning(FrameOffset /*dst*/,
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ManagedRegister /*src*/,
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FrameOffset /*in_off*/) {
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UNIMPLEMENTED(FATAL); // this case only currently exists for ARM
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}
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void X86JNIMacroAssembler::Load(ManagedRegister mdest, FrameOffset src, size_t size) {
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Load(mdest, X86ManagedRegister::FromCpuRegister(ESP), MemberOffset(src.Int32Value()), size);
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}
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void X86JNIMacroAssembler::Load(ManagedRegister mdest,
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ManagedRegister mbase,
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MemberOffset offs,
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size_t size) {
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X86ManagedRegister dest = mdest.AsX86();
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X86ManagedRegister base = mbase.AsX86();
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if (dest.IsNoRegister()) {
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CHECK_EQ(0u, size);
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} else if (dest.IsCpuRegister()) {
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CHECK_EQ(4u, size);
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__ movl(dest.AsCpuRegister(), Address(base.AsCpuRegister(), offs));
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} else if (dest.IsRegisterPair()) {
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CHECK_EQ(8u, size);
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__ movl(dest.AsRegisterPairLow(), Address(base.AsCpuRegister(), offs));
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__ movl(dest.AsRegisterPairHigh(),
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Address(base.AsCpuRegister(), FrameOffset(offs.Int32Value()+4)));
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} else if (dest.IsX87Register()) {
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if (size == 4) {
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__ flds(Address(base.AsCpuRegister(), offs));
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} else {
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__ fldl(Address(base.AsCpuRegister(), offs));
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}
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} else {
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CHECK(dest.IsXmmRegister());
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if (size == 4) {
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__ movss(dest.AsXmmRegister(), Address(base.AsCpuRegister(), offs));
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} else {
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__ movsd(dest.AsXmmRegister(), Address(base.AsCpuRegister(), offs));
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}
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}
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}
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void X86JNIMacroAssembler::LoadFromThread(ManagedRegister mdest, ThreadOffset32 src, size_t size) {
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X86ManagedRegister dest = mdest.AsX86();
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if (dest.IsNoRegister()) {
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CHECK_EQ(0u, size);
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} else if (dest.IsCpuRegister()) {
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if (size == 1u) {
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__ fs()->movzxb(dest.AsCpuRegister(), Address::Absolute(src));
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} else {
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CHECK_EQ(4u, size);
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__ fs()->movl(dest.AsCpuRegister(), Address::Absolute(src));
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}
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} else if (dest.IsRegisterPair()) {
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CHECK_EQ(8u, size);
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__ fs()->movl(dest.AsRegisterPairLow(), Address::Absolute(src));
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__ fs()->movl(dest.AsRegisterPairHigh(), Address::Absolute(ThreadOffset32(src.Int32Value()+4)));
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} else if (dest.IsX87Register()) {
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if (size == 4) {
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__ fs()->flds(Address::Absolute(src));
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} else {
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__ fs()->fldl(Address::Absolute(src));
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}
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} else {
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CHECK(dest.IsXmmRegister());
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if (size == 4) {
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__ fs()->movss(dest.AsXmmRegister(), Address::Absolute(src));
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} else {
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__ fs()->movsd(dest.AsXmmRegister(), Address::Absolute(src));
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}
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}
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}
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void X86JNIMacroAssembler::LoadRef(ManagedRegister mdest, FrameOffset src) {
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X86ManagedRegister dest = mdest.AsX86();
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CHECK(dest.IsCpuRegister());
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__ movl(dest.AsCpuRegister(), Address(ESP, src));
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}
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void X86JNIMacroAssembler::LoadRef(ManagedRegister mdest, ManagedRegister base, MemberOffset offs,
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bool unpoison_reference) {
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X86ManagedRegister dest = mdest.AsX86();
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CHECK(dest.IsCpuRegister() && dest.IsCpuRegister());
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__ movl(dest.AsCpuRegister(), Address(base.AsX86().AsCpuRegister(), offs));
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if (unpoison_reference) {
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__ MaybeUnpoisonHeapReference(dest.AsCpuRegister());
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}
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}
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void X86JNIMacroAssembler::LoadRawPtr(ManagedRegister mdest,
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ManagedRegister base,
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Offset offs) {
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X86ManagedRegister dest = mdest.AsX86();
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CHECK(dest.IsCpuRegister() && dest.IsCpuRegister());
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__ movl(dest.AsCpuRegister(), Address(base.AsX86().AsCpuRegister(), offs));
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}
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void X86JNIMacroAssembler::LoadRawPtrFromThread(ManagedRegister mdest, ThreadOffset32 offs) {
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X86ManagedRegister dest = mdest.AsX86();
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CHECK(dest.IsCpuRegister());
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__ fs()->movl(dest.AsCpuRegister(), Address::Absolute(offs));
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}
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void X86JNIMacroAssembler::SignExtend(ManagedRegister mreg, size_t size) {
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X86ManagedRegister reg = mreg.AsX86();
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CHECK(size == 1 || size == 2) << size;
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CHECK(reg.IsCpuRegister()) << reg;
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if (size == 1) {
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__ movsxb(reg.AsCpuRegister(), reg.AsByteRegister());
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} else {
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__ movsxw(reg.AsCpuRegister(), reg.AsCpuRegister());
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}
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}
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void X86JNIMacroAssembler::ZeroExtend(ManagedRegister mreg, size_t size) {
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X86ManagedRegister reg = mreg.AsX86();
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CHECK(size == 1 || size == 2) << size;
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CHECK(reg.IsCpuRegister()) << reg;
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if (size == 1) {
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__ movzxb(reg.AsCpuRegister(), reg.AsByteRegister());
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} else {
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__ movzxw(reg.AsCpuRegister(), reg.AsCpuRegister());
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}
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}
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void X86JNIMacroAssembler::MoveArguments(ArrayRef<ArgumentLocation> dests,
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ArrayRef<ArgumentLocation> srcs,
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ArrayRef<FrameOffset> refs) {
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size_t arg_count = dests.size();
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DCHECK_EQ(arg_count, srcs.size());
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DCHECK_EQ(arg_count, refs.size());
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// Store register args to stack slots. Convert processed references to `jobject`.
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bool found_hidden_arg = false;
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for (size_t i = 0; i != arg_count; ++i) {
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const ArgumentLocation& src = srcs[i];
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const ArgumentLocation& dest = dests[i];
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const FrameOffset ref = refs[i];
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DCHECK_EQ(src.GetSize(), dest.GetSize()); // Even for references.
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if (src.IsRegister()) {
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if (UNLIKELY(dest.IsRegister())) {
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if (dest.GetRegister().Equals(src.GetRegister())) {
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// JNI compiler sometimes adds a no-op move.
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continue;
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}
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// Native ABI has only stack arguments but we may pass one "hidden arg" in register.
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CHECK(!found_hidden_arg);
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found_hidden_arg = true;
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DCHECK_EQ(ref, kInvalidReferenceOffset);
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DCHECK(
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!dest.GetRegister().Equals(X86ManagedRegister::FromCpuRegister(GetScratchRegister())));
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Move(dest.GetRegister(), src.GetRegister(), dest.GetSize());
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} else {
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if (ref != kInvalidReferenceOffset) {
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// Note: We can clobber `src` here as the register cannot hold more than one argument.
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// This overload of `CreateJObject()` currently does not use the scratch
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// register ECX, so this shall not clobber another argument.
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CreateJObject(src.GetRegister(), ref, src.GetRegister(), /*null_allowed=*/ i != 0u);
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}
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Store(dest.GetFrameOffset(), src.GetRegister(), dest.GetSize());
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}
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} else {
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// Delay copying until we have spilled all registers, including the scratch register ECX.
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}
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}
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// Copy incoming stack args. Convert processed references to `jobject`.
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for (size_t i = 0; i != arg_count; ++i) {
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const ArgumentLocation& src = srcs[i];
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const ArgumentLocation& dest = dests[i];
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const FrameOffset ref = refs[i];
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DCHECK_EQ(src.GetSize(), dest.GetSize()); // Even for references.
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if (!src.IsRegister()) {
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DCHECK(!dest.IsRegister());
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if (ref != kInvalidReferenceOffset) {
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DCHECK_EQ(srcs[i].GetFrameOffset(), refs[i]);
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CreateJObject(dest.GetFrameOffset(), ref, /*null_allowed=*/ i != 0u);
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} else {
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Copy(dest.GetFrameOffset(), src.GetFrameOffset(), dest.GetSize());
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}
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}
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}
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}
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void X86JNIMacroAssembler::Move(ManagedRegister mdest, ManagedRegister msrc, size_t size) {
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DCHECK(!mdest.Equals(X86ManagedRegister::FromCpuRegister(GetScratchRegister())));
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X86ManagedRegister dest = mdest.AsX86();
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X86ManagedRegister src = msrc.AsX86();
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if (!dest.Equals(src)) {
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if (dest.IsCpuRegister() && src.IsCpuRegister()) {
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__ movl(dest.AsCpuRegister(), src.AsCpuRegister());
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} else if (src.IsX87Register() && dest.IsXmmRegister()) {
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// Pass via stack and pop X87 register
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IncreaseFrameSize(16);
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if (size == 4) {
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CHECK_EQ(src.AsX87Register(), ST0);
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__ fstps(Address(ESP, 0));
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__ movss(dest.AsXmmRegister(), Address(ESP, 0));
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} else {
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CHECK_EQ(src.AsX87Register(), ST0);
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__ fstpl(Address(ESP, 0));
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__ movsd(dest.AsXmmRegister(), Address(ESP, 0));
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}
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DecreaseFrameSize(16);
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} else {
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// TODO: x87, SSE
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UNIMPLEMENTED(FATAL) << ": Move " << dest << ", " << src;
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}
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}
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}
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void X86JNIMacroAssembler::CopyRef(FrameOffset dest, FrameOffset src) {
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Register scratch = GetScratchRegister();
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__ movl(scratch, Address(ESP, src));
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__ movl(Address(ESP, dest), scratch);
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}
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void X86JNIMacroAssembler::CopyRef(FrameOffset dest,
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ManagedRegister base,
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MemberOffset offs,
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bool unpoison_reference) {
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Register scratch = GetScratchRegister();
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__ movl(scratch, Address(base.AsX86().AsCpuRegister(), offs));
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if (unpoison_reference) {
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__ MaybeUnpoisonHeapReference(scratch);
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}
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__ movl(Address(ESP, dest), scratch);
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}
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void X86JNIMacroAssembler::CopyRawPtrFromThread(FrameOffset fr_offs, ThreadOffset32 thr_offs) {
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Register scratch = GetScratchRegister();
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__ fs()->movl(scratch, Address::Absolute(thr_offs));
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__ movl(Address(ESP, fr_offs), scratch);
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}
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void X86JNIMacroAssembler::CopyRawPtrToThread(ThreadOffset32 thr_offs,
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FrameOffset fr_offs,
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ManagedRegister mscratch) {
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X86ManagedRegister scratch = mscratch.AsX86();
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CHECK(scratch.IsCpuRegister());
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Load(scratch, fr_offs, 4);
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__ fs()->movl(Address::Absolute(thr_offs), scratch.AsCpuRegister());
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}
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void X86JNIMacroAssembler::Copy(FrameOffset dest, FrameOffset src, size_t size) {
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DCHECK(size == 4 || size == 8) << size;
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Register scratch = GetScratchRegister();
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__ movl(scratch, Address(ESP, src));
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__ movl(Address(ESP, dest), scratch);
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if (size == 8) {
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__ movl(scratch, Address(ESP, FrameOffset(src.Int32Value() + 4)));
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__ movl(Address(ESP, FrameOffset(dest.Int32Value() + 4)), scratch);
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}
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}
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void X86JNIMacroAssembler::Copy(FrameOffset /*dst*/,
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ManagedRegister /*src_base*/,
|
|
Offset /*src_offset*/,
|
|
ManagedRegister /*scratch*/,
|
|
size_t /*size*/) {
|
|
UNIMPLEMENTED(FATAL);
|
|
}
|
|
|
|
void X86JNIMacroAssembler::Copy(ManagedRegister dest_base,
|
|
Offset dest_offset,
|
|
FrameOffset src,
|
|
ManagedRegister scratch,
|
|
size_t size) {
|
|
CHECK(scratch.IsNoRegister());
|
|
CHECK_EQ(size, 4u);
|
|
__ pushl(Address(ESP, src));
|
|
__ popl(Address(dest_base.AsX86().AsCpuRegister(), dest_offset));
|
|
}
|
|
|
|
void X86JNIMacroAssembler::Copy(FrameOffset dest,
|
|
FrameOffset src_base,
|
|
Offset src_offset,
|
|
ManagedRegister mscratch,
|
|
size_t size) {
|
|
Register scratch = mscratch.AsX86().AsCpuRegister();
|
|
CHECK_EQ(size, 4u);
|
|
__ movl(scratch, Address(ESP, src_base));
|
|
__ movl(scratch, Address(scratch, src_offset));
|
|
__ movl(Address(ESP, dest), scratch);
|
|
}
|
|
|
|
void X86JNIMacroAssembler::Copy(ManagedRegister dest,
|
|
Offset dest_offset,
|
|
ManagedRegister src,
|
|
Offset src_offset,
|
|
ManagedRegister scratch,
|
|
size_t size) {
|
|
CHECK_EQ(size, 4u);
|
|
CHECK(scratch.IsNoRegister());
|
|
__ pushl(Address(src.AsX86().AsCpuRegister(), src_offset));
|
|
__ popl(Address(dest.AsX86().AsCpuRegister(), dest_offset));
|
|
}
|
|
|
|
void X86JNIMacroAssembler::Copy(FrameOffset dest,
|
|
Offset dest_offset,
|
|
FrameOffset src,
|
|
Offset src_offset,
|
|
ManagedRegister mscratch,
|
|
size_t size) {
|
|
Register scratch = mscratch.AsX86().AsCpuRegister();
|
|
CHECK_EQ(size, 4u);
|
|
CHECK_EQ(dest.Int32Value(), src.Int32Value());
|
|
__ movl(scratch, Address(ESP, src));
|
|
__ pushl(Address(scratch, src_offset));
|
|
__ popl(Address(scratch, dest_offset));
|
|
}
|
|
|
|
void X86JNIMacroAssembler::MemoryBarrier(ManagedRegister) {
|
|
__ mfence();
|
|
}
|
|
|
|
void X86JNIMacroAssembler::CreateJObject(ManagedRegister mout_reg,
|
|
FrameOffset spilled_reference_offset,
|
|
ManagedRegister min_reg,
|
|
bool null_allowed) {
|
|
X86ManagedRegister out_reg = mout_reg.AsX86();
|
|
X86ManagedRegister in_reg = min_reg.AsX86();
|
|
CHECK(in_reg.IsCpuRegister());
|
|
CHECK(out_reg.IsCpuRegister());
|
|
VerifyObject(in_reg, null_allowed);
|
|
if (null_allowed) {
|
|
Label null_arg;
|
|
if (!out_reg.Equals(in_reg)) {
|
|
__ xorl(out_reg.AsCpuRegister(), out_reg.AsCpuRegister());
|
|
}
|
|
__ testl(in_reg.AsCpuRegister(), in_reg.AsCpuRegister());
|
|
__ j(kZero, &null_arg);
|
|
__ leal(out_reg.AsCpuRegister(), Address(ESP, spilled_reference_offset));
|
|
__ Bind(&null_arg);
|
|
} else {
|
|
__ leal(out_reg.AsCpuRegister(), Address(ESP, spilled_reference_offset));
|
|
}
|
|
}
|
|
|
|
void X86JNIMacroAssembler::CreateJObject(FrameOffset out_off,
|
|
FrameOffset spilled_reference_offset,
|
|
bool null_allowed) {
|
|
Register scratch = GetScratchRegister();
|
|
if (null_allowed) {
|
|
Label null_arg;
|
|
__ movl(scratch, Address(ESP, spilled_reference_offset));
|
|
__ testl(scratch, scratch);
|
|
__ j(kZero, &null_arg);
|
|
__ leal(scratch, Address(ESP, spilled_reference_offset));
|
|
__ Bind(&null_arg);
|
|
} else {
|
|
__ leal(scratch, Address(ESP, spilled_reference_offset));
|
|
}
|
|
__ movl(Address(ESP, out_off), scratch);
|
|
}
|
|
|
|
void X86JNIMacroAssembler::VerifyObject(ManagedRegister /*src*/, bool /*could_be_null*/) {
|
|
// TODO: not validating references
|
|
}
|
|
|
|
void X86JNIMacroAssembler::VerifyObject(FrameOffset /*src*/, bool /*could_be_null*/) {
|
|
// TODO: not validating references
|
|
}
|
|
|
|
void X86JNIMacroAssembler::Jump(ManagedRegister mbase, Offset offset) {
|
|
X86ManagedRegister base = mbase.AsX86();
|
|
CHECK(base.IsCpuRegister());
|
|
__ jmp(Address(base.AsCpuRegister(), offset.Int32Value()));
|
|
}
|
|
|
|
void X86JNIMacroAssembler::Call(ManagedRegister mbase, Offset offset) {
|
|
X86ManagedRegister base = mbase.AsX86();
|
|
CHECK(base.IsCpuRegister());
|
|
__ call(Address(base.AsCpuRegister(), offset.Int32Value()));
|
|
// TODO: place reference map on call
|
|
}
|
|
|
|
void X86JNIMacroAssembler::CallFromThread(ThreadOffset32 offset) {
|
|
__ fs()->call(Address::Absolute(offset));
|
|
}
|
|
|
|
void X86JNIMacroAssembler::GetCurrentThread(ManagedRegister dest) {
|
|
__ fs()->movl(dest.AsX86().AsCpuRegister(),
|
|
Address::Absolute(Thread::SelfOffset<kX86PointerSize>()));
|
|
}
|
|
|
|
void X86JNIMacroAssembler::GetCurrentThread(FrameOffset offset) {
|
|
Register scratch = GetScratchRegister();
|
|
__ fs()->movl(scratch, Address::Absolute(Thread::SelfOffset<kX86PointerSize>()));
|
|
__ movl(Address(ESP, offset), scratch);
|
|
}
|
|
|
|
void X86JNIMacroAssembler::TryToTransitionFromRunnableToNative(
|
|
JNIMacroLabel* label, ArrayRef<const ManagedRegister> scratch_regs) {
|
|
constexpr uint32_t kNativeStateValue = Thread::StoredThreadStateValue(ThreadState::kNative);
|
|
constexpr uint32_t kRunnableStateValue = Thread::StoredThreadStateValue(ThreadState::kRunnable);
|
|
constexpr ThreadOffset32 thread_flags_offset = Thread::ThreadFlagsOffset<kX86PointerSize>();
|
|
constexpr ThreadOffset32 thread_held_mutex_mutator_lock_offset =
|
|
Thread::HeldMutexOffset<kX86PointerSize>(kMutatorLock);
|
|
|
|
// We need to preserve managed argument EAX.
|
|
DCHECK_GE(scratch_regs.size(), 2u);
|
|
Register saved_eax = scratch_regs[0].AsX86().AsCpuRegister();
|
|
Register scratch = scratch_regs[1].AsX86().AsCpuRegister();
|
|
|
|
// CAS release, old_value = kRunnableStateValue, new_value = kNativeStateValue, no flags.
|
|
__ movl(saved_eax, EAX); // Save EAX.
|
|
static_assert(kRunnableStateValue == 0u);
|
|
__ xorl(EAX, EAX);
|
|
__ movl(scratch, Immediate(kNativeStateValue));
|
|
__ fs()->LockCmpxchgl(Address::Absolute(thread_flags_offset.Uint32Value()), scratch);
|
|
// LOCK CMPXCHG has full barrier semantics, so we don't need barriers here.
|
|
__ movl(EAX, saved_eax); // Restore EAX; MOV does not change flags.
|
|
// If any flags are set, go to the slow path.
|
|
__ j(kNotZero, X86JNIMacroLabel::Cast(label)->AsX86());
|
|
|
|
// Clear `self->tlsPtr_.held_mutexes[kMutatorLock]`.
|
|
__ fs()->movl(Address::Absolute(thread_held_mutex_mutator_lock_offset.Uint32Value()),
|
|
Immediate(0));
|
|
}
|
|
|
|
void X86JNIMacroAssembler::TryToTransitionFromNativeToRunnable(
|
|
JNIMacroLabel* label,
|
|
ArrayRef<const ManagedRegister> scratch_regs,
|
|
ManagedRegister return_reg) {
|
|
constexpr uint32_t kNativeStateValue = Thread::StoredThreadStateValue(ThreadState::kNative);
|
|
constexpr uint32_t kRunnableStateValue = Thread::StoredThreadStateValue(ThreadState::kRunnable);
|
|
constexpr ThreadOffset32 thread_flags_offset = Thread::ThreadFlagsOffset<kX86PointerSize>();
|
|
constexpr ThreadOffset32 thread_held_mutex_mutator_lock_offset =
|
|
Thread::HeldMutexOffset<kX86PointerSize>(kMutatorLock);
|
|
constexpr ThreadOffset32 thread_mutator_lock_offset =
|
|
Thread::MutatorLockOffset<kX86PointerSize>();
|
|
|
|
size_t scratch_index = 0u;
|
|
auto get_scratch_reg = [&]() {
|
|
while (true) {
|
|
DCHECK_LT(scratch_index, scratch_regs.size());
|
|
X86ManagedRegister scratch_reg = scratch_regs[scratch_index].AsX86();
|
|
++scratch_index;
|
|
DCHECK(!scratch_reg.Overlaps(return_reg.AsX86()));
|
|
if (scratch_reg.AsCpuRegister() != EAX) {
|
|
return scratch_reg.AsCpuRegister();
|
|
}
|
|
}
|
|
};
|
|
Register scratch = get_scratch_reg();
|
|
bool preserve_eax = return_reg.AsX86().Overlaps(X86ManagedRegister::FromCpuRegister(EAX));
|
|
Register saved_eax = preserve_eax ? get_scratch_reg() : kNoRegister;
|
|
|
|
// CAS acquire, old_value = kNativeStateValue, new_value = kRunnableStateValue, no flags.
|
|
if (preserve_eax) {
|
|
__ movl(saved_eax, EAX); // Save EAX.
|
|
}
|
|
__ movl(EAX, Immediate(kNativeStateValue));
|
|
static_assert(kRunnableStateValue == 0u);
|
|
__ xorl(scratch, scratch);
|
|
__ fs()->LockCmpxchgl(Address::Absolute(thread_flags_offset.Uint32Value()), scratch);
|
|
// LOCK CMPXCHG has full barrier semantics, so we don't need barriers here.
|
|
if (preserve_eax) {
|
|
__ movl(EAX, saved_eax); // Restore EAX; MOV does not change flags.
|
|
}
|
|
// If any flags are set, or the state is not Native, go to the slow path.
|
|
// (While the thread can theoretically transition between different Suspended states,
|
|
// it would be very unexpected to see a state other than Native at this point.)
|
|
__ j(kNotZero, X86JNIMacroLabel::Cast(label)->AsX86());
|
|
|
|
// Set `self->tlsPtr_.held_mutexes[kMutatorLock]` to the mutator lock.
|
|
__ fs()->movl(scratch, Address::Absolute(thread_mutator_lock_offset.Uint32Value()));
|
|
__ fs()->movl(Address::Absolute(thread_held_mutex_mutator_lock_offset.Uint32Value()),
|
|
scratch);
|
|
}
|
|
|
|
void X86JNIMacroAssembler::SuspendCheck(JNIMacroLabel* label) {
|
|
__ fs()->testl(Address::Absolute(Thread::ThreadFlagsOffset<kX86PointerSize>()),
|
|
Immediate(Thread::SuspendOrCheckpointRequestFlags()));
|
|
__ j(kNotZero, X86JNIMacroLabel::Cast(label)->AsX86());
|
|
}
|
|
|
|
void X86JNIMacroAssembler::ExceptionPoll(JNIMacroLabel* label) {
|
|
__ fs()->cmpl(Address::Absolute(Thread::ExceptionOffset<kX86PointerSize>()), Immediate(0));
|
|
__ j(kNotEqual, X86JNIMacroLabel::Cast(label)->AsX86());
|
|
}
|
|
|
|
void X86JNIMacroAssembler::DeliverPendingException() {
|
|
// Pass exception as argument in EAX
|
|
__ fs()->movl(EAX, Address::Absolute(Thread::ExceptionOffset<kX86PointerSize>()));
|
|
__ fs()->call(Address::Absolute(QUICK_ENTRYPOINT_OFFSET(kX86PointerSize, pDeliverException)));
|
|
// this call should never return
|
|
__ int3();
|
|
}
|
|
|
|
std::unique_ptr<JNIMacroLabel> X86JNIMacroAssembler::CreateLabel() {
|
|
return std::unique_ptr<JNIMacroLabel>(new X86JNIMacroLabel());
|
|
}
|
|
|
|
void X86JNIMacroAssembler::Jump(JNIMacroLabel* label) {
|
|
CHECK(label != nullptr);
|
|
__ jmp(X86JNIMacroLabel::Cast(label)->AsX86());
|
|
}
|
|
|
|
static Condition UnaryConditionToX86Condition(JNIMacroUnaryCondition cond) {
|
|
switch (cond) {
|
|
case JNIMacroUnaryCondition::kZero:
|
|
return kZero;
|
|
case JNIMacroUnaryCondition::kNotZero:
|
|
return kNotZero;
|
|
default:
|
|
LOG(FATAL) << "Not implemented condition: " << static_cast<int>(cond);
|
|
UNREACHABLE();
|
|
}
|
|
}
|
|
|
|
void X86JNIMacroAssembler::TestGcMarking(JNIMacroLabel* label, JNIMacroUnaryCondition cond) {
|
|
CHECK(label != nullptr);
|
|
|
|
// CMP self->tls32_.is_gc_marking, 0
|
|
// Jcc <Offset>
|
|
DCHECK_EQ(Thread::IsGcMarkingSize(), 4u);
|
|
__ fs()->cmpl(Address::Absolute(Thread::IsGcMarkingOffset<kX86PointerSize>()), Immediate(0));
|
|
__ j(UnaryConditionToX86Condition(cond), X86JNIMacroLabel::Cast(label)->AsX86());
|
|
}
|
|
|
|
void X86JNIMacroAssembler::TestMarkBit(ManagedRegister mref,
|
|
JNIMacroLabel* label,
|
|
JNIMacroUnaryCondition cond) {
|
|
DCHECK(kUseBakerReadBarrier);
|
|
Register ref = mref.AsX86().AsCpuRegister();
|
|
static_assert(LockWord::kMarkBitStateSize == 1u);
|
|
__ testl(Address(ref, mirror::Object::MonitorOffset().SizeValue()),
|
|
Immediate(LockWord::kMarkBitStateMaskShifted));
|
|
__ j(UnaryConditionToX86Condition(cond), X86JNIMacroLabel::Cast(label)->AsX86());
|
|
}
|
|
|
|
void X86JNIMacroAssembler::Bind(JNIMacroLabel* label) {
|
|
CHECK(label != nullptr);
|
|
__ Bind(X86JNIMacroLabel::Cast(label)->AsX86());
|
|
}
|
|
|
|
#undef __
|
|
|
|
} // namespace x86
|
|
} // namespace art
|