79 lines
2.1 KiB
ArmAsm
79 lines
2.1 KiB
ArmAsm
/*
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* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <neoverse_n1.h>
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#include <cpu_macros.S>
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#include <platform_def.h>
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.globl plat_arm_calc_core_pos
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.globl plat_reset_handler
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/* -----------------------------------------------------
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* unsigned int plat_arm_calc_core_pos(u_register_t mpidr)
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*
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* Helper function to calculate the core position.
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* ((ChipId * N1SDP_MAX_CLUSTERS_PER_CHIP + ClusterId) *
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* N1SDP_MAX_CPUS_PER_CLUSTER * N1SDP_MAX_PE_PER_CPU) +
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* (CPUId * N1SDP_MAX_PE_PER_CPU) + ThreadId
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*
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* which can be simplified as:
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*
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* (((ChipId * N1SDP_MAX_CLUSTERS_PER_CHIP + ClusterId) *
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* N1SDP_MAX_CPUS_PER_CLUSTER + CPUId) * N1SDP_MAX_PE_PER_CPU) +
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* ThreadId
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* ------------------------------------------------------
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*/
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func plat_arm_calc_core_pos
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mov x4, x0
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/*
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* The MT bit in MPIDR is always set for n1sdp and the
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* affinity level 0 corresponds to thread affinity level.
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*/
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/* Extract individual affinity fields from MPIDR */
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ubfx x0, x4, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
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ubfx x1, x4, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
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ubfx x2, x4, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
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ubfx x3, x4, #MPIDR_AFF3_SHIFT, #MPIDR_AFFINITY_BITS
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/* Compute linear position */
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mov x4, #N1SDP_MAX_CLUSTERS_PER_CHIP
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madd x2, x3, x4, x2
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mov x4, #N1SDP_MAX_CPUS_PER_CLUSTER
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madd x1, x2, x4, x1
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mov x4, #N1SDP_MAX_PE_PER_CPU
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madd x0, x1, x4, x0
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ret
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endfunc plat_arm_calc_core_pos
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/* -----------------------------------------------------
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* void plat_reset_handler(void);
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*
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* Determine the CPU MIDR and disable power down bit for
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* that CPU.
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* -----------------------------------------------------
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*/
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func plat_reset_handler
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jump_if_cpu_midr NEOVERSE_N1_MIDR, N1
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ret
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/* -----------------------------------------------------
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* Disable CPU power down bit in power control register
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* -----------------------------------------------------
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*/
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N1:
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mrs x0, NEOVERSE_N1_CPUPWRCTLR_EL1
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bic x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK
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msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0
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isb
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ret
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endfunc plat_reset_handler
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