138 lines
3.8 KiB
C
138 lines
3.8 KiB
C
/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#include <assert.h>
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#include <platform_def.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <plat_marvell.h>
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/* Weak definitions may be overridden in specific ARM standard platform */
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#pragma weak plat_get_ns_image_entrypoint
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#pragma weak plat_marvell_get_mmap
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/*
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* Set up the page tables for the generic and platform-specific memory regions.
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* The extents of the generic memory regions are specified by the function
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* arguments and consist of:
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* - Trusted SRAM seen by the BL image;
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* - Code section;
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* - Read-only data section;
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* - Coherent memory region, if applicable.
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*/
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void marvell_setup_page_tables(uintptr_t total_base,
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size_t total_size,
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uintptr_t code_start,
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uintptr_t code_limit,
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uintptr_t rodata_start,
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uintptr_t rodata_limit
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#if USE_COHERENT_MEM
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,
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uintptr_t coh_start,
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uintptr_t coh_limit
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#endif
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)
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{
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/*
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* Map the Trusted SRAM with appropriate memory attributes.
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* Subsequent mappings will adjust the attributes for specific regions.
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*/
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VERBOSE("Trusted SRAM seen by this BL image: %p - %p\n",
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(void *) total_base, (void *) (total_base + total_size));
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mmap_add_region(total_base, total_base,
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total_size,
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MT_MEMORY | MT_RW | MT_SECURE);
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/* Re-map the code section */
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VERBOSE("Code region: %p - %p\n",
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(void *) code_start, (void *) code_limit);
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mmap_add_region(code_start, code_start,
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code_limit - code_start,
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MT_CODE | MT_SECURE);
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/* Re-map the read-only data section */
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VERBOSE("Read-only data region: %p - %p\n",
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(void *) rodata_start, (void *) rodata_limit);
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mmap_add_region(rodata_start, rodata_start,
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rodata_limit - rodata_start,
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MT_RO_DATA | MT_SECURE);
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#if USE_COHERENT_MEM
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/* Re-map the coherent memory region */
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VERBOSE("Coherent region: %p - %p\n",
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(void *) coh_start, (void *) coh_limit);
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mmap_add_region(coh_start, coh_start,
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coh_limit - coh_start,
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MT_DEVICE | MT_RW | MT_SECURE);
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#endif
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/* Now (re-)map the platform-specific memory regions */
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mmap_add(plat_marvell_get_mmap());
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/* Create the page tables to reflect the above mappings */
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init_xlat_tables();
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}
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unsigned long plat_get_ns_image_entrypoint(void)
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{
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return PLAT_MARVELL_NS_IMAGE_OFFSET;
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}
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/*****************************************************************************
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* Gets SPSR for BL32 entry
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*****************************************************************************
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*/
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uint32_t marvell_get_spsr_for_bl32_entry(void)
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{
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/*
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* The Secure Payload Dispatcher service is responsible for
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* setting the SPSR prior to entry into the BL32 image.
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*/
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return 0;
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}
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/*****************************************************************************
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* Gets SPSR for BL33 entry
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*****************************************************************************
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*/
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uint32_t marvell_get_spsr_for_bl33_entry(void)
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{
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unsigned long el_status;
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unsigned int mode;
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uint32_t spsr;
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/* Figure out what mode we enter the non-secure world in */
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el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
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el_status &= ID_AA64PFR0_ELX_MASK;
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mode = (el_status) ? MODE_EL2 : MODE_EL1;
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/*
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* TODO: Consider the possibility of specifying the SPSR in
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* the FIP ToC and allowing the platform to have a say as
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* well.
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*/
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spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
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return spsr;
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}
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/*****************************************************************************
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* Returns ARM platform specific memory map regions.
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*****************************************************************************
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*/
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const mmap_region_t *plat_marvell_get_mmap(void)
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{
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return plat_marvell_mmap;
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}
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