256 lines
8.0 KiB
TableGen
256 lines
8.0 KiB
TableGen
//===-- CaymanInstructions.td - CM Instruction defs -------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// TableGen definitions for instructions which are available only on Cayman
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// family GPUs.
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//
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//===----------------------------------------------------------------------===//
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def isCayman : Predicate<"Subtarget->hasCaymanISA()">;
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//===----------------------------------------------------------------------===//
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// Cayman Instructions
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//===----------------------------------------------------------------------===//
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let Predicates = [isCayman] in {
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def MULADD_INT24_cm : R600_3OP <0x08, "MULADD_INT24",
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[(set i32:$dst, (AMDGPUmad_i24 i32:$src0, i32:$src1, i32:$src2))], VecALU
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>;
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def MUL_INT24_cm : R600_2OP <0x5B, "MUL_INT24",
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[(set i32:$dst, (AMDGPUmul_i24 i32:$src0, i32:$src1))], VecALU
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>;
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def : IMad24Pat<MULADD_INT24_cm>;
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let isVector = 1 in {
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def RECIP_IEEE_cm : RECIP_IEEE_Common<0x86>;
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def MULLO_INT_cm : MULLO_INT_Common<0x8F>;
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def MULHI_INT_cm : MULHI_INT_Common<0x90>;
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def MULLO_UINT_cm : MULLO_UINT_Common<0x91>;
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def MULHI_UINT_cm : MULHI_UINT_Common<0x92>;
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def RECIPSQRT_CLAMPED_cm : RECIPSQRT_CLAMPED_Common<0x87>;
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def EXP_IEEE_cm : EXP_IEEE_Common<0x81>;
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def LOG_IEEE_cm : LOG_IEEE_Common<0x83>;
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def RECIP_CLAMPED_cm : RECIP_CLAMPED_Common<0x84>;
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def RECIPSQRT_IEEE_cm : RECIPSQRT_IEEE_Common<0x89>;
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def SIN_cm : SIN_Common<0x8D>;
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def COS_cm : COS_Common<0x8E>;
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} // End isVector = 1
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def : RsqPat<RECIPSQRT_IEEE_cm, f32>;
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def : POW_Common <LOG_IEEE_cm, EXP_IEEE_cm, MUL>;
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defm DIV_cm : DIV_Common<RECIP_IEEE_cm>;
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// RECIP_UINT emulation for Cayman
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// The multiplication scales from [0,1] to the unsigned integer range
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def : Pat <
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(AMDGPUurecip i32:$src0),
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(FLT_TO_UINT_eg (MUL_IEEE (RECIP_IEEE_cm (UINT_TO_FLT_eg $src0)),
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(MOV_IMM_I32 CONST.FP_UINT_MAX_PLUS_1)))
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>;
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def CF_END_CM : CF_CLAUSE_EG<32, (ins), "CF_END"> {
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let ADDR = 0;
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let POP_COUNT = 0;
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let COUNT = 0;
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}
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def : Pat<(fsqrt f32:$src), (MUL R600_Reg32:$src, (RECIPSQRT_CLAMPED_cm $src))>;
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class RAT_STORE_DWORD <RegisterClass rc, ValueType vt, bits<4> mask> :
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CF_MEM_RAT_CACHELESS <0x14, 0, mask,
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(ins rc:$rw_gpr, R600_TReg32_X:$index_gpr),
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"STORE_DWORD $rw_gpr, $index_gpr",
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[(global_store vt:$rw_gpr, i32:$index_gpr)]> {
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let eop = 0; // This bit is not used on Cayman.
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}
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def RAT_STORE_DWORD32 : RAT_STORE_DWORD <R600_TReg32_X, i32, 0x1>;
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def RAT_STORE_DWORD64 : RAT_STORE_DWORD <R600_Reg64, v2i32, 0x3>;
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def RAT_STORE_DWORD128 : RAT_STORE_DWORD <R600_Reg128, v4i32, 0xf>;
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def RAT_STORE_TYPED_cm: CF_MEM_RAT_STORE_TYPED<0> {
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let eop = 0; // This bit is not used on Cayman.
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}
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class VTX_READ_cm <string name, bits<8> buffer_id, dag outs, list<dag> pattern>
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: VTX_WORD0_cm, VTX_READ<name, buffer_id, outs, pattern> {
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// Static fields
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let VC_INST = 0;
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let FETCH_TYPE = 2;
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let FETCH_WHOLE_QUAD = 0;
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let BUFFER_ID = buffer_id;
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let SRC_REL = 0;
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// XXX: We can infer this field based on the SRC_GPR. This would allow us
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// to store vertex addresses in any channel, not just X.
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let SRC_SEL_X = 0;
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let SRC_SEL_Y = 0;
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let STRUCTURED_READ = 0;
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let LDS_REQ = 0;
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let COALESCED_READ = 0;
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let Inst{31-0} = Word0;
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}
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class VTX_READ_8_cm <bits<8> buffer_id, list<dag> pattern>
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: VTX_READ_cm <"VTX_READ_8 $dst_gpr, $src_gpr", buffer_id,
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(outs R600_TReg32_X:$dst_gpr), pattern> {
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let DST_SEL_X = 0;
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let DST_SEL_Y = 7; // Masked
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let DST_SEL_Z = 7; // Masked
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let DST_SEL_W = 7; // Masked
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let DATA_FORMAT = 1; // FMT_8
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}
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class VTX_READ_16_cm <bits<8> buffer_id, list<dag> pattern>
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: VTX_READ_cm <"VTX_READ_16 $dst_gpr, $src_gpr", buffer_id,
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(outs R600_TReg32_X:$dst_gpr), pattern> {
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let DST_SEL_X = 0;
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let DST_SEL_Y = 7; // Masked
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let DST_SEL_Z = 7; // Masked
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let DST_SEL_W = 7; // Masked
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let DATA_FORMAT = 5; // FMT_16
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}
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class VTX_READ_32_cm <bits<8> buffer_id, list<dag> pattern>
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: VTX_READ_cm <"VTX_READ_32 $dst_gpr, $src_gpr", buffer_id,
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(outs R600_TReg32_X:$dst_gpr), pattern> {
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let DST_SEL_X = 0;
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let DST_SEL_Y = 7; // Masked
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let DST_SEL_Z = 7; // Masked
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let DST_SEL_W = 7; // Masked
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let DATA_FORMAT = 0xD; // COLOR_32
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// This is not really necessary, but there were some GPU hangs that appeared
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// to be caused by ALU instructions in the next instruction group that wrote
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// to the $src_gpr registers of the VTX_READ.
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// e.g.
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// %T3_X<def> = VTX_READ_PARAM_32_eg %T2_X<kill>, 24
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// %T2_X<def> = MOV %ZERO
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//Adding this constraint prevents this from happening.
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let Constraints = "$src_gpr.ptr = $dst_gpr";
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}
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class VTX_READ_64_cm <bits<8> buffer_id, list<dag> pattern>
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: VTX_READ_cm <"VTX_READ_64 $dst_gpr, $src_gpr", buffer_id,
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(outs R600_Reg64:$dst_gpr), pattern> {
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let DST_SEL_X = 0;
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let DST_SEL_Y = 1;
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let DST_SEL_Z = 7;
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let DST_SEL_W = 7;
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let DATA_FORMAT = 0x1D; // COLOR_32_32
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}
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class VTX_READ_128_cm <bits<8> buffer_id, list<dag> pattern>
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: VTX_READ_cm <"VTX_READ_128 $dst_gpr.XYZW, $src_gpr", buffer_id,
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(outs R600_Reg128:$dst_gpr), pattern> {
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let DST_SEL_X = 0;
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let DST_SEL_Y = 1;
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let DST_SEL_Z = 2;
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let DST_SEL_W = 3;
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let DATA_FORMAT = 0x22; // COLOR_32_32_32_32
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// XXX: Need to force VTX_READ_128 instructions to write to the same register
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// that holds its buffer address to avoid potential hangs. We can't use
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// the same constraint as VTX_READ_32_eg, because the $src_gpr.ptr and $dst
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// registers are different sizes.
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}
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//===----------------------------------------------------------------------===//
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// VTX Read from parameter memory space
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//===----------------------------------------------------------------------===//
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def VTX_READ_PARAM_8_cm : VTX_READ_8_cm <0,
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[(set i32:$dst_gpr, (load_param_exti8 ADDRVTX_READ:$src_gpr))]
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>;
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def VTX_READ_PARAM_16_cm : VTX_READ_16_cm <0,
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[(set i32:$dst_gpr, (load_param_exti16 ADDRVTX_READ:$src_gpr))]
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>;
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def VTX_READ_PARAM_32_cm : VTX_READ_32_cm <0,
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[(set i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
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>;
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def VTX_READ_PARAM_64_cm : VTX_READ_64_cm <0,
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[(set v2i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
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>;
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def VTX_READ_PARAM_128_cm : VTX_READ_128_cm <0,
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[(set v4i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))]
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>;
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//===----------------------------------------------------------------------===//
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// VTX Read from global memory space
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//===----------------------------------------------------------------------===//
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// 8-bit reads
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def VTX_READ_ID1_8_cm : VTX_READ_8_cm <1,
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[(set i32:$dst_gpr, (vtx_id1_az_extloadi8 ADDRVTX_READ:$src_gpr))]
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>;
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// 16-bit reads
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def VTX_READ_ID1_16_cm : VTX_READ_16_cm <1,
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[(set i32:$dst_gpr, (vtx_id1_az_extloadi16 ADDRVTX_READ:$src_gpr))]
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>;
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// 32-bit reads
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def VTX_READ_ID1_32_cm : VTX_READ_32_cm <1,
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[(set i32:$dst_gpr, (vtx_id1_load ADDRVTX_READ:$src_gpr))]
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>;
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// 64-bit reads
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def VTX_READ_ID1_64_cm : VTX_READ_64_cm <1,
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[(set v2i32:$dst_gpr, (vtx_id1_load ADDRVTX_READ:$src_gpr))]
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>;
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// 128-bit reads
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def VTX_READ_ID1_128_cm : VTX_READ_128_cm <1,
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[(set v4i32:$dst_gpr, (vtx_id1_load ADDRVTX_READ:$src_gpr))]
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>;
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// 8-bit reads
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def VTX_READ_ID2_8_cm : VTX_READ_8_cm <2,
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[(set i32:$dst_gpr, (vtx_id2_az_extloadi8 ADDRVTX_READ:$src_gpr))]
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>;
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// 16-bit reads
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def VTX_READ_ID2_16_cm : VTX_READ_16_cm <2,
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[(set i32:$dst_gpr, (vtx_id2_az_extloadi16 ADDRVTX_READ:$src_gpr))]
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>;
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// 32-bit reads
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def VTX_READ_ID2_32_cm : VTX_READ_32_cm <2,
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[(set i32:$dst_gpr, (vtx_id2_load ADDRVTX_READ:$src_gpr))]
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>;
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// 64-bit reads
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def VTX_READ_ID2_64_cm : VTX_READ_64_cm <2,
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[(set v2i32:$dst_gpr, (vtx_id2_load ADDRVTX_READ:$src_gpr))]
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>;
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// 128-bit reads
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def VTX_READ_ID2_128_cm : VTX_READ_128_cm <2,
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[(set v4i32:$dst_gpr, (vtx_id2_load ADDRVTX_READ:$src_gpr))]
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>;
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} // End isCayman
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