112 lines
4.1 KiB
C++
112 lines
4.1 KiB
C++
//===-- AMDGPUMCTargetDesc.cpp - AMDGPU Target Descriptions ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief This file provides AMDGPU specific target descriptions.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUMCTargetDesc.h"
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#include "AMDGPUELFStreamer.h"
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#include "AMDGPUMCAsmInfo.h"
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#include "AMDGPUTargetStreamer.h"
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#include "InstPrinter/AMDGPUInstPrinter.h"
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#include "SIDefines.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MachineLocation.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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#define GET_INSTRINFO_MC_DESC
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#include "AMDGPUGenInstrInfo.inc"
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#define GET_SUBTARGETINFO_MC_DESC
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#include "AMDGPUGenSubtargetInfo.inc"
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#define GET_REGINFO_MC_DESC
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#include "AMDGPUGenRegisterInfo.inc"
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static MCInstrInfo *createAMDGPUMCInstrInfo() {
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MCInstrInfo *X = new MCInstrInfo();
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InitAMDGPUMCInstrInfo(X);
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return X;
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}
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static MCRegisterInfo *createAMDGPUMCRegisterInfo(const Triple &TT) {
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MCRegisterInfo *X = new MCRegisterInfo();
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InitAMDGPUMCRegisterInfo(X, 0);
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return X;
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}
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static MCSubtargetInfo *
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createAMDGPUMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
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return createAMDGPUMCSubtargetInfoImpl(TT, CPU, FS);
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}
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static MCInstPrinter *createAMDGPUMCInstPrinter(const Triple &T,
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unsigned SyntaxVariant,
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const MCAsmInfo &MAI,
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const MCInstrInfo &MII,
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const MCRegisterInfo &MRI) {
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return new AMDGPUInstPrinter(MAI, MII, MRI);
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}
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static MCTargetStreamer *createAMDGPUAsmTargetStreamer(MCStreamer &S,
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formatted_raw_ostream &OS,
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MCInstPrinter *InstPrint,
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bool isVerboseAsm) {
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return new AMDGPUTargetAsmStreamer(S, OS);
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}
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static MCTargetStreamer * createAMDGPUObjectTargetStreamer(
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MCStreamer &S,
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const MCSubtargetInfo &STI) {
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return new AMDGPUTargetELFStreamer(S);
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}
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static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context,
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MCAsmBackend &MAB, raw_pwrite_stream &OS,
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MCCodeEmitter *Emitter, bool RelaxAll) {
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if (T.getOS() == Triple::AMDHSA)
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return createAMDGPUELFStreamer(Context, MAB, OS, Emitter, RelaxAll);
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return createELFStreamer(Context, MAB, OS, Emitter, RelaxAll);
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}
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extern "C" void LLVMInitializeAMDGPUTargetMC() {
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for (Target *T : {&TheAMDGPUTarget, &TheGCNTarget}) {
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RegisterMCAsmInfo<AMDGPUMCAsmInfo> X(*T);
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TargetRegistry::RegisterMCInstrInfo(*T, createAMDGPUMCInstrInfo);
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TargetRegistry::RegisterMCRegInfo(*T, createAMDGPUMCRegisterInfo);
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TargetRegistry::RegisterMCSubtargetInfo(*T, createAMDGPUMCSubtargetInfo);
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TargetRegistry::RegisterMCInstPrinter(*T, createAMDGPUMCInstPrinter);
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TargetRegistry::RegisterMCAsmBackend(*T, createAMDGPUAsmBackend);
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TargetRegistry::RegisterELFStreamer(*T, createMCStreamer);
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}
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// R600 specific registration
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TargetRegistry::RegisterMCCodeEmitter(TheAMDGPUTarget,
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createR600MCCodeEmitter);
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// GCN specific registration
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TargetRegistry::RegisterMCCodeEmitter(TheGCNTarget, createSIMCCodeEmitter);
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TargetRegistry::RegisterAsmTargetStreamer(TheGCNTarget,
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createAMDGPUAsmTargetStreamer);
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TargetRegistry::RegisterObjectTargetStreamer(TheGCNTarget,
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createAMDGPUObjectTargetStreamer);
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}
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