64 lines
1.9 KiB
C++
64 lines
1.9 KiB
C++
//===-- AMDGPUMCTargetDesc.h - AMDGPU Target Descriptions -----*- C++ -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
/// \file
|
|
/// \brief Provides AMDGPU specific target descriptions.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
|
|
#ifndef LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUMCTARGETDESC_H
|
|
#define LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUMCTARGETDESC_H
|
|
|
|
#include "llvm/Support/DataTypes.h"
|
|
|
|
namespace llvm {
|
|
class StringRef;
|
|
class MCAsmBackend;
|
|
class MCCodeEmitter;
|
|
class MCContext;
|
|
class MCInstrInfo;
|
|
class MCObjectWriter;
|
|
class MCRegisterInfo;
|
|
class MCSubtargetInfo;
|
|
class Target;
|
|
class Triple;
|
|
class raw_pwrite_stream;
|
|
class raw_ostream;
|
|
|
|
extern Target TheAMDGPUTarget;
|
|
extern Target TheGCNTarget;
|
|
|
|
MCCodeEmitter *createR600MCCodeEmitter(const MCInstrInfo &MCII,
|
|
const MCRegisterInfo &MRI,
|
|
MCContext &Ctx);
|
|
|
|
MCCodeEmitter *createSIMCCodeEmitter(const MCInstrInfo &MCII,
|
|
const MCRegisterInfo &MRI,
|
|
MCContext &Ctx);
|
|
|
|
MCAsmBackend *createAMDGPUAsmBackend(const Target &T, const MCRegisterInfo &MRI,
|
|
const Triple &TT, StringRef CPU);
|
|
|
|
MCObjectWriter *createAMDGPUELFObjectWriter(bool Is64Bit,
|
|
bool HasRelocationAddend,
|
|
raw_pwrite_stream &OS);
|
|
} // End llvm namespace
|
|
|
|
#define GET_REGINFO_ENUM
|
|
#include "AMDGPUGenRegisterInfo.inc"
|
|
|
|
#define GET_INSTRINFO_ENUM
|
|
#include "AMDGPUGenInstrInfo.inc"
|
|
|
|
#define GET_SUBTARGETINFO_ENUM
|
|
#include "AMDGPUGenSubtargetInfo.inc"
|
|
|
|
#endif
|