428 lines
15 KiB
C++
428 lines
15 KiB
C++
/*
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* Copyright (C) 2017-2018 NXP Semiconductors
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef NCILXDEBUGDECODER_H_
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#define NCILXDEBUGDECODER_H_
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#include "phOsal_Adaptation.h"
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#include <string>
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using namespace std;
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#ifdef __cplusplus
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extern "C" { /* Assume C declarations for C++ */
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#endif /* __cplusplus */
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#define MAX_TLV 15
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/*
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typedef struct timeStamp {
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uint16_t timeStampMs; //millisec elapsed after last RF
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On Event. Tells Raw RSSI values in case of RSSI debug mode uint16_t timeStampUs;
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//microsec elapsed after last RF On Event. Insignificant values in case of RSSI
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debug mode } stimeStamp_t, *pstimeStamp_t;
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typedef struct cliffState {
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uint8_t cliffStateTriggerType; //L1 or L2 or Felica Event Name
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uint8_t cliffStateTriggerTypeDirection; //Either Tx or Rx
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uint8_t cliffStateRFTechNMode; //CLIFF RF Technology and Mode
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} scliffState_t, *pscliffState_t;
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typedef struct rssiValues {
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uint8_t rawRSSIADC; //When RSSI debug mode is enabled
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uint8_t rawRSSIAGC; //When RSSI debug mode is enabled
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uint16_t intrpltdRSSI; //When RSSI debug mode is enabled
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} srssiValues_t, *psrssiValues_t;
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typedef struct apcValues {
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uint16_t APC; //In case of Tx event
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uint8_t residualCarrier;
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uint8_t numDriver;
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float vtxAmp;
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float vtxLDO;
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uint16_t txVpp;
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} sapcValues_t, *psapcValues_t;
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typedef struct felicaInfo {
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string felicaCmdCode;
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string felicaSysCode;
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string felicaRspCode;
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uint8_t felicaRspCodeStatusFlags[2];
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string felicaMisc;
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string eddFelica;
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} sfelicaInfo_t, *psfelicaInfo_t;
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typedef struct extraDbgData {
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uint8_t eddL1Error;
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uint8_t eddL1RxNak;
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uint8_t eddL1TxErr;
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uint16_t eddL178164RetCode;
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uint8_t eddL2WUP;
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uint8_t eddFelica;
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} sextraDbgData_t, *psextraDbgData_t;
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*/
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typedef struct {
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uint16_t timeStampMs; // millisec elapsed after last RF On Event. Tells Raw
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// RSSI values in case of RSSI debug mode
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uint16_t timeStampUs; // microsec elapsed after last RF On Event.
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// Insignificant values in case of RSSI debug mode
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uint8_t* pCliffStateTriggerType; // L1 or L2 or Felica Event Name
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uint8_t* pCliffStateTriggerTypeDirection; // Either Tx or Rx
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uint8_t* pCliffStateRFTechNMode; // CLIFF RF Technology and Mode
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uint8_t rawRSSIADC; // When RSSI debug mode is enabled
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uint8_t rawRSSIAGC; // When RSSI debug mode is enabled
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uint8_t intrpltdRSSI[2]; // When RSSI debug mode is enabled
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uint8_t APC[2]; // In case of Tx event
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uint8_t* pEddL1Error;
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uint8_t* pEddL1RxNak;
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uint8_t* pEddL1TxErr;
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uint8_t eddL178164RetCode[2];
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uint8_t* pEddL2WUP;
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uint8_t felicaCmdCode;
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uint8_t felicaSysCode[2];
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uint8_t felicaRspCode;
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uint8_t felicaRspCodeStatusFlags[2];
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uint8_t* pFelicaMisc;
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uint8_t eddFelica;
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uint8_t residualCarrier;
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uint8_t numDriver;
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int16_t vtxAmp;
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float vtxLDO;
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uint16_t txVpp;
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} sDecodedInfo_t, *psDecodedInfo_t;
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typedef struct {
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uint8_t* pLxNtf;
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uint16_t LxNtfLen;
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} sLxNtfCoded_t, *psLxNtfCoded_t;
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typedef struct {
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uint8_t baseIndex;
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uint8_t milliSecOffset;
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uint8_t microSecOffset; // Not significant in case of RSSI debug mode
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uint8_t rawRSSIOffset; // In case of RSSI debug enabled
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uint8_t intrpltdRSSIOffset;
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uint8_t apcOffset;
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uint8_t cliffStateTriggerTypeOffset;
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uint8_t cliffStateRFTechModeOffset;
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uint8_t retCode78164Offset;
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uint8_t felicaCmdOffset;
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uint8_t felicaSysCodeOffset;
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uint8_t felicaRspCodeOffset;
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uint8_t felicaRspStatusFlagsOffset;
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uint8_t felicaMiscOffset;
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uint8_t eddOffset;
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uint8_t eddFelicaOffset;
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} sLxNtfDecodingInfo_t, *psLxNtfDecodingInfo_t;
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typedef struct {
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sDecodedInfo_t sInfo;
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} sL1NtfDecoded_t, *psL1NtfDecoded_t;
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typedef struct {
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uint8_t tlvCount;
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sDecodedInfo_t sTlvInfo[MAX_TLV];
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} sL2NtfDecoded_t, *psL2NtfDecoded_t;
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typedef struct {
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uint8_t level;
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psL1NtfDecoded_t psL1NtfDecoded;
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psL2NtfDecoded_t psL2NtfDecoded;
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} sLxNtfDecoded_t, *psLxNtfDecoded_t;
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class NCI_LxDebug_Decoder {
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private:
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static NCI_LxDebug_Decoder* mLxDbgDecoder;
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uint8_t mL2DebugMode; // bit:0 Byte0
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uint8_t mFelicaRFDebugMode; // bit:1 Byte0
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uint8_t mFelicaSCDebugMode; // bit:2 Byte0
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uint8_t mL1DebugMode; // bit:4 Byte0
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uint8_t m7816DebugMode; // bit:6 Byte0
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uint8_t mRssiDebugMode; // bit:0 Byte1
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float mLOOKUP_VTXLDO[5] = {3.0, 3.3, 3.6, 4.5, 4.7}; // in Volts
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int16_t mLOOKUP_VTXAMP[4] = {-150, -250, -500, -1000}; // in mVolts
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uint8_t mLOOKUP_NUMDRIVER[2] = {1, 2};
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uint8_t mLOOKUP_RESCARRIER[32] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
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11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21,
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22, 23, 24, 25, 26, 27, 28, 29, 30, 31};
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uint16_t mLOOKUP_VTXLDO_BITMASK = 0x0700;
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uint16_t mLOOKUP_VTXAMP_BITMASK = 0x00C0;
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uint16_t mLOOKUP_NUMDRIVER_BITMASK = 0x0020;
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uint16_t mLOOKUP_RESCARRIER_BITMASK = 0x001F;
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uint8_t mCLF_EVT_DIRECTION[2][11] = {"CLF_EVT_RX", "CLF_EVT_TX"};
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uint8_t mCLF_STAT_L1_TRIG_TYPE[15][27] = {
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"CLF_L1_EVT_RFU", "CLF_L1_EVT_ACTIVATED",
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"CLF_L1_EVT_DATA_RX", "CLF_L1_EVT_RX_DESELECT",
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"CLF_L1_EVT_RX_WTX", "CLF_L1_EVT_ERROR",
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"CLF_L1_EVT_RX_ACK", "CLF_L1_EVT_RX_NACK",
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"CLF_L1_EVT_DATA_TX", "CLF_L1_EVT_WTX_AND_DATA_TX",
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"CLF_L1_EVT_TX_DESELECT", "CLF_L1_EVT_TX_WTX",
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"CLF_L1_EVT_TX_ACK", "CLF_L1_EVT_TX_NAK",
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"CLF_L1_EVT_EXTENDED"};
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uint8_t mCLF_STAT_L2_TRIG_TYPE[12][31] = {
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"CLF_L2_EVT_RFU", "CLF_L2_EVT_MODULATION_DETECTED", "CLF_L2_EVT_DATA_RX",
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"CLF_L2_EVT_TIMEOUT",
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"CLF_L2_EVT_ACTIVE_ISO14443_3", // Internal to card Layer3 activation
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"CLF_L2_EVT_ERROR", "CLF_L2_EVT_SENSING",
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"CLF_L2_EVT_ACTIVE_ISO14443_4", // APC, Because Layer4 activation sent to
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// reader as Tx
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"CLF_L2_EVT_RFON", "CLF_L2_EVT_RFOFF", "CLF_L2_EVT_DATA_TX",
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"CLF_L2_EVT_WUP_IOT_RECONFIG" // APC
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};
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uint8_t mCLF_STAT_RF_TECH_MODE[14][42] = {
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"CLF_STATE_TECH_RFU",
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"CLF_STATE_TECH_CE_A",
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"CLF_STATE_TECH_CE_B",
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"CLF_STATE_TECH_CE_F",
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"CLF_STATE_TECH_NFCIP1_TARGET_PASSIVE_A",
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"CLF_STATE_TECH_NFCIP1_TARGET_PASSIVE_F",
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"CLF_STATE_TECH_NFCIP1_TARGET_ACTIVE_A",
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"CLF_STATE_TECH_NFCIP1_TARGET_ACTIVE_F",
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"CLF_STATE_TECH_RM_A",
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"CLF_STATE_TECH_RM_B",
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"CLF_STATE_TECH_RM_F",
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"CLF_STATE_TECH_NFCIP1_INITIATOR_PASSIVE_A",
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"CLF_STATE_TECH_NFCIP1_INITIATOR_PASSIVE_B",
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"CLF_STATE_TECH_NFCIP1_INITIATOR_PASSIVE_F"};
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uint8_t mEDD_L1_ERROR[8][34] = {
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"L1_ERROR_EDD_RF_TIMEOUT", "L1_ERROR_EDD_RF_CRC_ERROR",
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"L1_ERROR_EDD_RF_COLLISION", "L1_ERROR_EDD_RX_DATA_OVERFLOW",
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"L1_ERROR_EDD_RX_PROTOCOL_ERROR", "L1_ERROR_EDD_TX_NO_DATA_ERROR",
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"L1_ERROR_EDD_EXTERNAL_FIELD_ERROR", "L1_ERROR_EDD_RXDATA_LENGTH_ERROR"};
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uint8_t mEDD_L1_TX_ERROR[28] = "L1_TX_EVT_EDD_DPLL_UNLOCKED";
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uint8_t mEDD_L1_RX_NAK[5][26] = {
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"L1_RX_NACK_EDD_IOT_STAGE1", "L1_RX_NACK_EDD_IOT_STAGE2",
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"L1_RX_NACK_EDD_IOT_STAGE3", "L1_RX_NACK_EDD_IOT_STAGE4",
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"L1_RX_NACK_EDD_IOT_STAGE5"};
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uint8_t mEDD_L2_WUP[5][22] = {
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"L2_EDD_WUP_IOT_STAGE1", "L2_EDD_WUP_IOT_STAGE2", "L2_EDD_WUP_IOT_STAGE3",
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"L2_EDD_WUP_IOT_STAGE4", "L2_EDD_WUP_IOT_STAGE5"};
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uint8_t mFELICA_MISC_EVT[5][34] = {
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"FLC_MISC_EVT_RFU", "FLC_MISC_EVT_GENERIC_ERROR",
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"FLC_MISC_EVT_EMPTY_FRAME_FROM_ESE", "FLC_MISC_EVT_BUFFER_OVERFLOW",
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"FLC_MISC_EVT_RF_ERROR"};
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typedef enum {
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CLF_L1_EVT_RFU = 0x00,
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CLF_L1_EVT_ACTIVATED = 0x01, // APC
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CLF_L1_EVT_DATA_RX = 0x02,
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CLF_L1_EVT_RX_DESLECT = 0x03,
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CLF_L1_EVT_RX_WTX = 0x04,
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CLF_L1_EVT_ERROR = 0x05,
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CLF_L1_EVT_RX_ACK = 0x06,
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CLF_L1_EVT_RX_NACK = 0x07,
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CLF_L1_EVT_DATA_TX = 0x08, // APC
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CLF_L1_EVT_WTX_AND_DATA_TX = 0x09, // APC
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CLF_L1_EVT_TX_DESELECT = 0x0A, // APC
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CLF_L1_EVT_TX_WTX = 0x0B, // APC
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CLF_L1_EVT_TX_ACK = 0x0C, // APC
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CLF_L1_EVT_TX_NAK = 0x0D, // APC
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CLF_L1_EVT_EXTENDED = 0x0E // APC
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} CliffStateL1EventType_t;
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typedef enum {
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CLF_L2_EVT_RFU = 0x00,
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CLF_L2_EVT_MODULATION_DETECTED = 0x01,
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CLF_L2_EVT_DATA_RX = 0x02,
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CLF_L2_EVT_TIMEOUT = 0x03,
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CLF_L2_EVT_ACTIVE_ISO14443_3 = 0x04, // Internal to card Layer3 activation
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CLF_L2_EVT_ERROR = 0x05,
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CLF_L2_EVT_SENSING = 0x06,
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CLF_L2_EVT_ACTIVE_ISO14443_4 =
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0x07, // APC, Because Layer4 activation sent to reader as Tx
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CLF_L2_EVT_RFON = 0x08,
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CLF_L2_EVT_RFOFF = 0x09,
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CLF_L2_EVT_DATA_TX = 0x0A, // APC
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CLF_L2_EVT_WUP_IOT_RECONFIG = 0x0B
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} CliffStateL2EventType_t;
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typedef enum {
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SYSTEM_DEBUG_STATE_L1_MESSAGE =
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0x35, // RF Exchanges & Events after Activation of NFC-DEP/ISO-DEP
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SYSTEM_DEBUG_STATE_L2_MESSAGE =
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0x36 // RF Exchanges & Events before Activation
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} LxDebugNtfType_t;
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typedef enum {
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L1_EVT_LEN = 0x07,
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L1_EVT_EXTRA_DBG_LEN = 0x08,
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L1_EVT_7816_RET_CODE_LEN = 0x0A
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} L1DebugNtfLen_t;
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typedef enum {
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L2_EVT_TAG_ID = 0x10,
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L2_EVT_FELICA_CMD_TAG_ID = 0x20,
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L2_EVT_FELICA_SYS_CODE_TAG_ID = 0x30,
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L2_EVT_FELICA_RSP_CODE_TAG_ID = 0x40,
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L2_EVT_FELICA_MISC_TAG_ID = 0x50
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} L2DebugNtfTLVTagId_t;
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typedef enum {
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L2_EVT_TAG_ID_LEN = 0x07,
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L2_EVT_TAG_ID_EXTRA_DBG_LEN = 0x08,
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L2_EVT_FELICA_CMD_TAG_ID_LEN = 0x07,
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L2_EVT_FELICA_CMD_TAG_ID_EXTRA_DBG_LEN = 0x08,
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L2_EVT_FELICA_SYS_CODE_TAG_ID_LEN = 0x06,
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L2_EVT_FELICA_RSP_CODE_TAG_ID_LEN = 0x09,
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L2_EVT_FELICA_RSP_CODE_TAG_ID_EXTRA_DBG_LEN = 0x0A,
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L2_EVT_FELICA_MISC_TAG_ID_LEN = 0x05,
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L2_EVT_FELICA_MISC_TAG_ID_EXTRA_DBG_LEN = 0x06
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} L2DebugNtfTLVLength_t;
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typedef enum {
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FLC_RM_EVT_RFU = 0x00,
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FLC_RM_EVT_ACTIVATED = 0x01,
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FLC_RM_EVT_DATA_RX,
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FLC_RM_EVT_RX_READ,
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FLC_RM_EVT_RX_WRITE,
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FLC_RM_EVT_ERROR,
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FLC_RM_EVT_DATA_TX,
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FLC_RM_EVT_TX_READ,
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FLC_RM_EVT_TX_WRITE
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} FelicaRMEvents_t;
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typedef enum {
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CLF_STATE_TECH_RFU = 0x00,
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CLF_STATE_TECH_CE_A = 0x10,
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CLF_STATE_TECH_CE_B = 0x20,
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CLF_STATE_TECH_CE_F = 0x30,
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CLF_STATE_TECH_NFCIP1_TARGET_PASSIVE_A = 0x40,
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CLF_STATE_TECH_NFCIP1_TARGET_PASSIVE_F = 0x50,
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CLF_STATE_TECH_NFCIP1_TARGET_ACTIVE_A = 0x60,
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CLF_STATE_TECH_NFCIP1_TARGET_ACTIVE_F = 0x70,
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CLF_STATE_TECH_RM_A = 0x80,
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CLF_STATE_TECH_RM_B = 0x90,
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CLF_STATE_TECH_RM_F = 0xA0,
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CLF_STATE_TECH_NFCIP1_INITIATOR_PASSIVE_A = 0xC0,
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CLF_STATE_TECH_NFCIP1_INITIATOR_PASSIVE_B = 0xD0,
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CLF_STATE_TECH_NFCIP1_INITIATOR_PASSIVE_F = 0xE0
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} CliffStateTechType_t;
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typedef enum {
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L1_ERROR_EDD_RF_TIMEOUT = 0x01,
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L1_ERROR_EDD_RF_CRC_ERROR = 0x02,
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L1_ERROR_EDD_RF_COLLISION = 0x04,
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L1_ERROR_EDD_RX_DATA_OVERFLOW = 0x05,
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L1_ERROR_EDD_RX_PROTOCOL_ERROR = 0x06,
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L1_ERROR_EDD_TX_NO_DATA_ERROR = 0x07,
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L1_ERROR_EDD_EXTERNAL_FIELD_ERROR = 0x0A,
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L1_ERROR_EDD_RXDATA_LENGTH_ERROR = 0x80
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} ExtraDebugDataforL1_ERROR_t;
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typedef enum {
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L1_TX_EVT_EDD_DPLL_UNLOCKED = 0x84
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} ExtraDebugData_L1_ALL_TX_EVENTS_t;
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typedef enum {
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L1_RX_NACK_EDD_IOT_STAGE1 = 0x85,
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L1_RX_NACK_EDD_IOT_STAGE2 = 0x86,
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L1_RX_NACK_EDD_IOT_STAGE3 = 0x87,
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L1_RX_NACK_EDD_IOT_STAGE4 = 0x88,
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L1_RX_NACK_EDD_IOT_STAGE5 = 0x89
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} ExtraDebugData_L1_RX_NACK_t;
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typedef enum {
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L2_EDD_WUP_IOT_STAGE1 = 0x01,
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L2_EDD_WUP_IOT_STAGE2 = 0x02,
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L2_EDD_WUP_IOT_STAGE3 = 0x03,
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L2_EDD_WUP_IOT_STAGE4 = 0x04,
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L2_EDD_WUP_IOT_STAGE5 = 0x05,
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} ExtraDebugData_CLF_L2_EVT_WUP_IOT_RECONFIG_t;
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typedef enum {
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L2_EDD_FLC_CMD_CODE = 0x01,
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L2_EDD_FLC_RSP_CODE = 0x02,
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L2_EDD_FLC_MISC = 0x03
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} ExtraDebugData_Felica_t;
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typedef enum {
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FLC_MISC_EVT_RFU = 0x00,
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FLC_MISC_EVT_GENERIC_ERROR = 0x01,
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FLC_MISC_EVT_EMPTY_FRAME_FROM_ESE,
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FLC_MISC_EVT_BUFFER_OVERFLOW,
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FLC_MISC_EVT_RF_ERROR = 0x05
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} FelicaMiscEventType_t;
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NCI_LxDebug_Decoder();
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void setLxDebugModes(uint8_t* pNciPkt, uint16_t pktLen);
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void parseL1DbgNtf(psLxNtfCoded_t psLxNtfCoded,
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psLxNtfDecoded_t psLxNtfDecoded);
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void parseL2DbgNtf(psLxNtfCoded_t psLxNtfCoded,
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psLxNtfDecoded_t psLxNtfDecoded);
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void decodeTimeStamp(psLxNtfCoded_t psLxNtfCoded,
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psLxNtfDecodingInfo_t psLxNtfDecodingInfo,
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psLxNtfDecoded_t psLxNtfDecoded);
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void decodeAPCTable(psLxNtfCoded_t psLxNtfCoded,
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psLxNtfDecodingInfo_t psLxNtfDecodingInfo,
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psLxNtfDecoded_t psLxNtfDecoded);
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void decodeRSSIValues(psLxNtfCoded_t psLxNtfCoded,
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psLxNtfDecodingInfo_t psLxNtfDecodingInfo,
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psLxNtfDecoded_t psLxNtfDecoded);
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void decodeCLIFFState(psLxNtfCoded_t psLxNtfCoded,
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psLxNtfDecodingInfo_t psLxNtfDecodingInfo,
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psLxNtfDecoded_t psLxNtfDecoded);
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void decodeRFTechMode(psLxNtfCoded_t psLxNtfCoded,
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psLxNtfDecodingInfo_t psLxNtfDecodingInfo,
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psLxNtfDecoded_t psLxNtfDecoded);
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void decodeTriggerType(psLxNtfCoded_t psLxNtfCoded,
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psLxNtfDecodingInfo_t psLxNtfDecodingInfo,
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psLxNtfDecoded_t psLxNtfDecoded);
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void decode78164RetCode(psLxNtfCoded_t psLxNtfCoded,
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psLxNtfDecodingInfo_t psLxNtfDecodingInfo,
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psLxNtfDecoded_t psLxNtfDecoded);
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void decodeFelicaCmdCode(psLxNtfCoded_t psLxNtfCoded,
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psLxNtfDecodingInfo_t psLxNtfDecodingInfo,
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psLxNtfDecoded_t psLxNtfDecoded);
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void decodeFelicaSystemCode(psLxNtfCoded_t psLxNtfCoded,
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psLxNtfDecodingInfo_t psLxNtfDecodingInfo,
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psLxNtfDecoded_t psLxNtfDecoded);
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void decodeFelicaRspCode(psLxNtfCoded_t psLxNtfCoded,
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psLxNtfDecodingInfo_t psLxNtfDecodingInfo,
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psLxNtfDecoded_t psLxNtfDecoded);
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void decodeFelicaMiscCode(psLxNtfCoded_t psLxNtfCoded,
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psLxNtfDecodingInfo_t psLxNtfDecodingInfo,
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psLxNtfDecoded_t psLxNtfDecoded);
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void decodeExtraDbgData(psLxNtfCoded_t psLxNtfCoded,
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psLxNtfDecodingInfo_t psLxNtfDecodingInfo,
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psLxNtfDecoded_t psLxNtfDecoded);
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void calculateTxVpp(psLxNtfDecoded_t psLxNtfDecoded);
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void printLxDebugInfo(psLxNtfDecoded_t psLxNtfDecoded);
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public:
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~NCI_LxDebug_Decoder();
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static NCI_LxDebug_Decoder& getInstance();
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void processLxDbgNciPkt(uint8_t* pNciPkt, uint16_t pktLen);
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};
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#ifdef __cplusplus
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} /* Assume C declarations for C++ */
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#endif /* __cplusplus */
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#endif /* NCILXDEBUGDECODER_H_ */
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