256 lines
6.1 KiB
C
256 lines
6.1 KiB
C
/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <mt_gic_v3.h>
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#include <lib/mmio.h>
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#include <platform_def.h>
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#include <pmic.h>
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#include <spm.h>
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#include <uart.h>
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#define SPM_SYSCLK_SETTLE 99
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#define WAKE_SRC_FOR_SUSPEND \
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(WAKE_SRC_R12_PCM_TIMER | \
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WAKE_SRC_R12_SSPM_WDT_EVENT_B | \
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WAKE_SRC_R12_KP_IRQ_B | \
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WAKE_SRC_R12_CONN2AP_SPM_WAKEUP_B | \
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WAKE_SRC_R12_EINT_EVENT_B | \
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WAKE_SRC_R12_CONN_WDT_IRQ_B | \
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WAKE_SRC_R12_CCIF0_EVENT_B | \
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WAKE_SRC_R12_SSPM_SPM_IRQ_B | \
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WAKE_SRC_R12_SCP_SPM_IRQ_B | \
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WAKE_SRC_R12_SCP_WDT_EVENT_B | \
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WAKE_SRC_R12_USB_CDSC_B | \
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WAKE_SRC_R12_USB_POWERDWN_B | \
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WAKE_SRC_R12_SYS_TIMER_EVENT_B | \
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WAKE_SRC_R12_EINT_EVENT_SECURE_B | \
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WAKE_SRC_R12_CCIF1_EVENT_B | \
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WAKE_SRC_R12_MD2AP_PEER_EVENT_B | \
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WAKE_SRC_R12_MD1_WDT_B | \
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WAKE_SRC_R12_CLDMA_EVENT_B | \
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WAKE_SRC_R12_SEJ_WDT_GPT_B)
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#define SLP_PCM_FLAGS \
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(SPM_FLAG_DIS_VCORE_DVS | SPM_FLAG_DIS_VCORE_DFS | \
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SPM_FLAG_DIS_ATF_ABORT | SPM_FLAG_DISABLE_MMSYS_DVFS | \
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SPM_FLAG_DIS_INFRA_PDN | SPM_FLAG_SUSPEND_OPTION)
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#define SLP_PCM_FLAGS1 \
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(SPM_FLAG1_DISABLE_MCDSR)
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static const struct pwr_ctrl suspend_ctrl = {
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.wake_src = WAKE_SRC_FOR_SUSPEND,
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.pcm_flags = SLP_PCM_FLAGS,
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.pcm_flags1 = SLP_PCM_FLAGS1,
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/* SPM_AP_STANDBY_CON */
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.wfi_op = 0x1,
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.mp0_cputop_idle_mask = 0,
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.mp1_cputop_idle_mask = 0,
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.mcusys_idle_mask = 0,
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.mm_mask_b = 0,
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.md_ddr_en_0_dbc_en = 0x1,
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.md_ddr_en_1_dbc_en = 0,
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.md_mask_b = 0x1,
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.sspm_mask_b = 0x1,
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.scp_mask_b = 0x1,
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.srcclkeni_mask_b = 0x1,
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.md_apsrc_1_sel = 0,
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.md_apsrc_0_sel = 0,
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.conn_ddr_en_dbc_en = 0x1,
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.conn_mask_b = 0x1,
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.conn_apsrc_sel = 0,
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/* SPM_SRC_REQ */
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.spm_apsrc_req = 0,
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.spm_f26m_req = 0,
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.spm_infra_req = 0,
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.spm_vrf18_req = 0,
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.spm_ddren_req = 0,
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.spm_rsv_src_req = 0,
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.spm_ddren_2_req = 0,
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.cpu_md_dvfs_sop_force_on = 0,
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/* SPM_SRC_MASK */
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.csyspwreq_mask = 0x1,
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.ccif0_md_event_mask_b = 0x1,
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.ccif0_ap_event_mask_b = 0x1,
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.ccif1_md_event_mask_b = 0x1,
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.ccif1_ap_event_mask_b = 0x1,
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.ccif2_md_event_mask_b = 0x1,
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.ccif2_ap_event_mask_b = 0x1,
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.ccif3_md_event_mask_b = 0x1,
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.ccif3_ap_event_mask_b = 0x1,
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.md_srcclkena_0_infra_mask_b = 0x1,
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.md_srcclkena_1_infra_mask_b = 0,
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.conn_srcclkena_infra_mask_b = 0,
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.ufs_infra_req_mask_b = 0,
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.srcclkeni_infra_mask_b = 0,
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.md_apsrc_req_0_infra_mask_b = 0x1,
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.md_apsrc_req_1_infra_mask_b = 0x1,
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.conn_apsrcreq_infra_mask_b = 0x1,
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.ufs_srcclkena_mask_b = 0,
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.md_vrf18_req_0_mask_b = 0,
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.md_vrf18_req_1_mask_b = 0,
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.ufs_vrf18_req_mask_b = 0,
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.gce_vrf18_req_mask_b = 0,
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.conn_infra_req_mask_b = 0x1,
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.gce_apsrc_req_mask_b = 0,
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.disp0_apsrc_req_mask_b = 0,
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.disp1_apsrc_req_mask_b = 0,
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.mfg_req_mask_b = 0,
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.vdec_req_mask_b = 0,
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/* SPM_SRC2_MASK */
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.md_ddr_en_0_mask_b = 0x1,
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.md_ddr_en_1_mask_b = 0,
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.conn_ddr_en_mask_b = 0x1,
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.ddren_sspm_apsrc_req_mask_b = 0x1,
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.ddren_scp_apsrc_req_mask_b = 0x1,
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.disp0_ddren_mask_b = 0x1,
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.disp1_ddren_mask_b = 0x1,
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.gce_ddren_mask_b = 0x1,
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.ddren_emi_self_refresh_ch0_mask_b = 0,
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.ddren_emi_self_refresh_ch1_mask_b = 0,
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/* SPM_WAKEUP_EVENT_MASK */
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.spm_wakeup_event_mask = 0xF1782218,
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/* SPM_WAKEUP_EVENT_EXT_MASK */
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.spm_wakeup_event_ext_mask = 0xFFFFFFFF,
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/* SPM_SRC3_MASK */
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.md_ddr_en_2_0_mask_b = 0x1,
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.md_ddr_en_2_1_mask_b = 0,
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.conn_ddr_en_2_mask_b = 0x1,
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.ddren2_sspm_apsrc_req_mask_b = 0x1,
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.ddren2_scp_apsrc_req_mask_b = 0x1,
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.disp0_ddren2_mask_b = 0,
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.disp1_ddren2_mask_b = 0,
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.gce_ddren2_mask_b = 0,
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.ddren2_emi_self_refresh_ch0_mask_b = 0,
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.ddren2_emi_self_refresh_ch1_mask_b = 0,
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.mp0_cpu0_wfi_en = 0x1,
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.mp0_cpu1_wfi_en = 0x1,
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.mp0_cpu2_wfi_en = 0x1,
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.mp0_cpu3_wfi_en = 0x1,
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.mp1_cpu0_wfi_en = 0x1,
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.mp1_cpu1_wfi_en = 0x1,
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.mp1_cpu2_wfi_en = 0x1,
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.mp1_cpu3_wfi_en = 0x1
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};
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static uint32_t spm_set_sysclk_settle(void)
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{
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mmio_write_32(SPM_CLK_SETTLE, SPM_SYSCLK_SETTLE);
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return mmio_read_32(SPM_CLK_SETTLE);
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}
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void go_to_sleep_before_wfi(void)
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{
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int cpu = MPIDR_AFFLVL0_VAL(read_mpidr());
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uint32_t settle;
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settle = spm_set_sysclk_settle();
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spm_set_cpu_status(cpu);
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spm_set_power_control(&suspend_ctrl);
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spm_set_wakeup_event(&suspend_ctrl);
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spm_set_pcm_flags(&suspend_ctrl);
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spm_send_cpu_wakeup_event();
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spm_set_pcm_wdt(0);
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spm_disable_pcm_timer();
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if (is_infra_pdn(suspend_ctrl.pcm_flags))
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mt_uart_save();
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if (!mt_console_uart_cg_status())
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console_switch_state(CONSOLE_FLAG_BOOT);
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INFO("cpu%d: \"%s\", wakesrc = 0x%x, pcm_con1 = 0x%x\n",
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cpu, spm_get_firmware_version(), suspend_ctrl.wake_src,
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mmio_read_32(PCM_CON1));
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INFO("settle = %u, sec = %u, sw_flag = 0x%x 0x%x, src_req = 0x%x\n",
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settle, mmio_read_32(PCM_TIMER_VAL) / 32768,
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suspend_ctrl.pcm_flags, suspend_ctrl.pcm_flags1,
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mmio_read_32(SPM_SRC_REQ));
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if (!mt_console_uart_cg_status())
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console_switch_state(CONSOLE_FLAG_RUNTIME);
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}
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static void go_to_sleep_after_wfi(void)
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{
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struct wake_status spm_wakesta;
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if (is_infra_pdn(suspend_ctrl.pcm_flags))
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mt_uart_restore();
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spm_set_pcm_wdt(0);
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spm_get_wakeup_status(&spm_wakesta);
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spm_clean_after_wakeup();
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if (!mt_console_uart_cg_status())
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console_switch_state(CONSOLE_FLAG_BOOT);
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spm_output_wake_reason(&spm_wakesta, "suspend");
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if (!mt_console_uart_cg_status())
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console_switch_state(CONSOLE_FLAG_RUNTIME);
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}
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static void spm_enable_armpll_l(void)
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{
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/* power on */
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mmio_setbits_32(ARMPLL_L_PWR_CON0, 0x1);
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/* clear isolation */
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mmio_clrbits_32(ARMPLL_L_PWR_CON0, 0x2);
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/* enable pll */
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mmio_setbits_32(ARMPLL_L_CON0, 0x1);
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/* Add 20us delay for turning on PLL */
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udelay(20);
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}
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static void spm_disable_armpll_l(void)
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{
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/* disable pll */
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mmio_clrbits_32(ARMPLL_L_CON0, 0x1);
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/* isolation */
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mmio_setbits_32(ARMPLL_L_PWR_CON0, 0x2);
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/* power off */
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mmio_clrbits_32(ARMPLL_L_PWR_CON0, 0x1);
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}
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void spm_system_suspend(void)
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{
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spm_disable_armpll_l();
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bcpu_enable(0);
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bcpu_sram_enable(0);
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spm_lock_get();
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go_to_sleep_before_wfi();
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spm_lock_release();
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}
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void spm_system_suspend_finish(void)
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{
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spm_lock_get();
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go_to_sleep_after_wfi();
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spm_lock_release();
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spm_enable_armpll_l();
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bcpu_sram_enable(1);
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bcpu_enable(1);
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}
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