140 lines
3.7 KiB
C
140 lines
3.7 KiB
C
/*
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* Copyright (c) 2021, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include <mtk_sip_svc.h>
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#include <plat_dfd.h>
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static bool dfd_enabled;
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static uint64_t dfd_base_addr;
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static uint64_t dfd_chain_length;
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static uint64_t dfd_cache_dump;
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static void dfd_setup(uint64_t base_addr, uint64_t chain_length,
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uint64_t cache_dump)
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{
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/* bit[0]: rg_rw_dfd_internal_dump_en -> 1 */
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/* bit[2]: rg_rw_dfd_clock_stop_en -> 1 */
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sync_writel(DFD_INTERNAL_CTL, 0x5);
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/* bit[13]: xreset_b_update_disable */
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mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 13);
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/*
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* bit[10:3]: DFD trigger selection mask
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* bit[3]: rg_rw_dfd_trigger_sel[0] = 1(enable wdt trigger)
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* bit[4]: rg_rw_dfd_trigger_sel[1] = 1(enable HW trigger)
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* bit[5]: rg_rw_dfd_trigger_sel[2] = 1(enable SW trigger)
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* bit[6]: rg_rw_dfd_trigger_sel[3] = 1(enable SW non-security trigger)
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* bit[7]: rg_rw_dfd_trigger_sel[4] = 1(enable timer trigger)
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*/
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mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 3);
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/* bit[20:19]: rg_dfd_armpll_div_mux_sel switch to PLL2 for DFD */
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mmio_setbits_32(DFD_INTERNAL_CTL, 0x3 << 19);
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/*
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* bit[0]: rg_rw_dfd_auto_power_on = 1
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* bit[2:1]: rg_rw_dfd_auto_power_on_dely = 1(10us)
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* bit[4:2]: rg_rw_dfd_power_on_wait_time = 1(20us)
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*/
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mmio_write_32(DFD_INTERNAL_PWR_ON, 0xB);
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/* longest scan chain length */
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mmio_write_32(DFD_CHAIN_LENGTH0, chain_length);
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/* bit[1:0]: rg_rw_dfd_shift_clock_ratio */
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mmio_write_32(DFD_INTERNAL_SHIFT_CLK_RATIO, 0x0);
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/* rg_dfd_test_so_over_64 */
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mmio_write_32(DFD_INTERNAL_TEST_SO_OVER_64, 0x1);
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/* DFD3.0 */
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mmio_write_32(DFD_TEST_SI_0, DFD_TEST_SI_0_CACHE_DIS_VAL);
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mmio_write_32(DFD_TEST_SI_1, DFD_TEST_SI_1_VAL);
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mmio_write_32(DFD_TEST_SI_2, DFD_TEST_SI_2_VAL);
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mmio_write_32(DFD_TEST_SI_3, DFD_TEST_SI_3_VAL);
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/* for iLDO feature */
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sync_writel(DFD_POWER_CTL, 0xF9);
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/* set base address */
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mmio_write_32(DFD_O_SET_BASEADDR_REG, base_addr >> 24);
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/*
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* disable sleep protect of DFD
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* 10001220[8]: protect_en_reg[8]
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* 10001a3c[2]: infra_mcu_pwr_ctl_mask[2]
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*/
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mmio_clrbits_32(DFD_O_PROTECT_EN_REG, 1 << 8);
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mmio_clrbits_32(DFD_O_INTRF_MCU_PWR_CTL_MASK, 1 << 2);
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/* clean DFD trigger status */
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sync_writel(DFD_CLEAN_STATUS, 0x1);
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sync_writel(DFD_CLEAN_STATUS, 0x0);
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/* DFD-3.0 */
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sync_writel(DFD_V30_CTL, 0x1);
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/* setup global variables for suspend and resume */
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dfd_enabled = true;
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dfd_base_addr = base_addr;
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dfd_chain_length = chain_length;
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dfd_cache_dump = cache_dump;
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if ((cache_dump & DFD_CACHE_DUMP_ENABLE) != 0UL) {
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/* DFD3.5 */
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mmio_write_32(DFD_TEST_SI_0, DFD_TEST_SI_0_CACHE_EN_VAL);
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sync_writel(DFD_V35_ENALBE, 0x1);
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sync_writel(DFD_V35_TAP_NUMBER, 0xB);
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sync_writel(DFD_V35_TAP_EN, DFD_V35_TAP_EN_VAL);
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sync_writel(DFD_V35_SEQ0_0, DFD_V35_SEQ0_0_VAL);
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if (cache_dump & DFD_PARITY_ERR_TRIGGER) {
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sync_writel(DFD_HW_TRIGGER_MASK, 0xC);
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mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 4);
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}
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}
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dsbsy();
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}
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void dfd_resume(void)
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{
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if (dfd_enabled == true) {
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dfd_setup(dfd_base_addr, dfd_chain_length, dfd_cache_dump);
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}
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}
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uint64_t dfd_smc_dispatcher(uint64_t arg0, uint64_t arg1,
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uint64_t arg2, uint64_t arg3)
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{
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uint64_t ret = 0L;
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switch (arg0) {
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case PLAT_MTK_DFD_SETUP_MAGIC:
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dfd_setup(arg1, arg2, arg3);
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break;
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case PLAT_MTK_DFD_READ_MAGIC:
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/* only allow to access DFD register base + 0x200 */
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if (arg1 <= 0x200) {
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ret = mmio_read_32(MISC1_CFG_BASE + arg1);
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}
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break;
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case PLAT_MTK_DFD_WRITE_MAGIC:
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/* only allow to access DFD register base + 0x200 */
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if (arg1 <= 0x200) {
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sync_writel(MISC1_CFG_BASE + arg1, arg2);
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}
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break;
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default:
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ret = MTK_SIP_E_INVALID_PARAM;
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break;
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}
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return ret;
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}
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