105 lines
2.6 KiB
C
105 lines
2.6 KiB
C
/*
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* Copyright (c) 2020, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stddef.h>
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#include <string.h>
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#include <common/debug.h>
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#include <lib/bakery_lock.h>
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#include <lib/mmio.h>
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#include <mt_lp_rm.h>
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#include <mt_spm.h>
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#include <mt_spm_cond.h>
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#include <mt_spm_conservation.h>
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#include <mt_spm_constraint.h>
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#include <mt_spm_idle.h>
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#include <mt_spm_internal.h>
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#include <mt_spm_pmic_wrap.h>
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#include <mt_spm_rc_internal.h>
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#include <mt_spm_reg.h>
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#include <mt_spm_resource_req.h>
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#include <mt_spm_suspend.h>
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#include <mtk_plat_common.h>
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#include <plat_mtk_lpm.h>
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#include <plat_pm.h>
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#include <platform_def.h>
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#include <sleep_def.h>
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#ifdef MT_SPM_USING_BAKERY_LOCK
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DEFINE_BAKERY_LOCK(spm_lock);
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#define plat_spm_lock_init() bakery_lock_init(&spm_lock)
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#else
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spinlock_t spm_lock;
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#define plat_spm_lock_init()
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#endif
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/* CLK_SCP_CFG_0 */
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#define CLK_SCP_CFG_0 (TOPCKGEN_BASE + 0x200)
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#define SPM_CK_CONTROL_EN 0x3FF
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/* CLK_SCP_CFG_1 */
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#define CLK_SCP_CFG_1 (TOPCKGEN_BASE + 0x210)
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#define CLK_SCP_CFG_1_MASK 0x100C
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#define CLK_SCP_CFG_1_SPM 0x3
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struct mt_resource_constraint plat_constraint_bus26m = {
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.is_valid = spm_is_valid_rc_bus26m,
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.update = spm_update_rc_bus26m,
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.allow = spm_allow_rc_bus26m,
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.run = spm_run_rc_bus26m,
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.reset = spm_reset_rc_bus26m,
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};
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struct mt_resource_constraint plat_constraint_syspll = {
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.is_valid = spm_is_valid_rc_syspll,
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.update = spm_update_rc_syspll,
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.allow = spm_allow_rc_syspll,
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.run = spm_run_rc_syspll,
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.reset = spm_reset_rc_syspll,
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};
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struct mt_resource_constraint plat_constraint_dram = {
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.is_valid = spm_is_valid_rc_dram,
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.update = spm_update_rc_dram,
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.allow = spm_allow_rc_dram,
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.run = spm_run_rc_dram,
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.reset = spm_reset_rc_dram,
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};
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struct mt_resource_constraint plat_constraint_cpu = {
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.is_valid = spm_is_valid_rc_cpu_buck_ldo,
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.update = NULL,
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.allow = spm_allow_rc_cpu_buck_ldo,
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.run = spm_run_rc_cpu_buck_ldo,
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.reset = spm_reset_rc_cpu_buck_ldo,
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};
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struct mt_resource_constraint *plat_constraints[] = {
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&plat_constraint_bus26m,
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&plat_constraint_syspll,
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&plat_constraint_dram,
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&plat_constraint_cpu,
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NULL,
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};
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struct mt_resource_manager plat_mt8192_rm = {
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.update = mt_spm_cond_update,
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.consts = plat_constraints,
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};
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void spm_boot_init(void)
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{
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/* switch ck_off/axi_26m control to SPM */
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mmio_setbits_32(CLK_SCP_CFG_0, SPM_CK_CONTROL_EN);
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mmio_clrsetbits_32(CLK_SCP_CFG_1, CLK_SCP_CFG_1_MASK,
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CLK_SCP_CFG_1_SPM);
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plat_spm_lock_init();
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mt_spm_pmic_wrap_set_phase(PMIC_WRAP_PHASE_ALLINONE);
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mt_lp_rm_register(&plat_mt8192_rm);
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mt_spm_idle_generic_init();
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mt_spm_suspend_init();
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}
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