178 lines
		
	
	
		
			4.5 KiB
		
	
	
	
		
			C
		
	
	
	
			
		
		
	
	
			178 lines
		
	
	
		
			4.5 KiB
		
	
	
	
		
			C
		
	
	
	
/*
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 * Copyright (c) 2020, MediaTek Inc. All rights reserved.
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 *
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 * SPDX-License-Identifier: BSD-3-Clause
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 */
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#include <assert.h>
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#include <mcucfg.h>
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#include <mtspmc.h>
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#include <mtspmc_private.h>
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void mcucfg_disable_gic_wakeup(uint32_t cluster, uint32_t cpu)
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{
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	mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(cpu));
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}
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void mcucfg_enable_gic_wakeup(uint32_t cluster, uint32_t cpu)
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{
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	mmio_clrbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(cpu));
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}
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void mcucfg_set_bootaddr(uint32_t cluster, uint32_t cpu, uintptr_t bootaddr)
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{
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	assert(cluster == 0U);
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	mmio_write_32(per_cpu(cluster, cpu, MCUCFG_BOOTADDR), bootaddr);
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}
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uintptr_t mcucfg_get_bootaddr(uint32_t cluster, uint32_t cpu)
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{
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	assert(cluster == 0U);
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	return (uintptr_t)mmio_read_32(per_cpu(cluster, cpu, MCUCFG_BOOTADDR));
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}
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void mcucfg_init_archstate(uint32_t cluster, uint32_t cpu, bool arm64)
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{
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	uint32_t reg;
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	assert(cluster == 0U);
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	reg = per_cluster(cluster, MCUCFG_INITARCH);
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	if (arm64) {
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		mmio_setbits_32(reg, MCUCFG_INITARCH_CPU_BIT(cpu));
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	} else {
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		mmio_clrbits_32(reg, MCUCFG_INITARCH_CPU_BIT(cpu));
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	}
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}
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/**
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 * Return subsystem's power state.
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 *
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 * @mask: mask to SPM_CPU_PWR_STATUS to query the power state
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 *        of one subsystem.
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 * RETURNS:
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 * 0 (the subsys was powered off)
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 * 1 (the subsys was powered on)
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 */
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bool spm_get_powerstate(uint32_t mask)
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{
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	return (mmio_read_32(SPM_CPU_PWR_STATUS) & mask) != 0U;
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}
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bool spm_get_cluster_powerstate(uint32_t cluster)
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{
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	assert(cluster == 0U);
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	return spm_get_powerstate(MP0_CPUTOP);
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}
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bool spm_get_cpu_powerstate(uint32_t cluster, uint32_t cpu)
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{
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	uint32_t mask = BIT(cpu);
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	assert(cluster == 0U);
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	return spm_get_powerstate(mask);
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}
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int spmc_init(void)
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{
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	INFO("SPM: enable CPC mode\n");
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	mmio_write_32(SPM_POWERON_CONFIG_EN, PROJECT_CODE | BCLK_CG_EN);
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	mmio_setbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWR_RST_B);
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	mmio_setbits_32(per_cpu(0, 2, SPM_CPU_PWR), PWR_RST_B);
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	mmio_setbits_32(per_cpu(0, 3, SPM_CPU_PWR), PWR_RST_B);
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	mmio_setbits_32(per_cpu(0, 4, SPM_CPU_PWR), PWR_RST_B);
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	mmio_setbits_32(per_cpu(0, 5, SPM_CPU_PWR), PWR_RST_B);
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	mmio_setbits_32(per_cpu(0, 6, SPM_CPU_PWR), PWR_RST_B);
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	mmio_setbits_32(per_cpu(0, 7, SPM_CPU_PWR), PWR_RST_B);
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	mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(1));
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	mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(2));
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	mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(3));
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	mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(4));
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	mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(5));
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	mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(6));
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	mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(7));
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	mmio_clrbits_32(SPM_MCUSYS_PWR_CON, RESETPWRON_CONFIG);
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	mmio_clrbits_32(SPM_MP0_CPUTOP_PWR_CON, RESETPWRON_CONFIG);
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	mmio_clrbits_32(per_cpu(0, 0, SPM_CPU_PWR), RESETPWRON_CONFIG);
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	mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, CPC_CTRL_ENABLE);
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	return 0;
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}
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/**
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 * Power on a core with specified cluster and core index
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 *
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 * @cluster: the cluster ID of the CPU which to be powered on
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 * @cpu: the CPU ID of the CPU which to be powered on
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 */
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void spm_poweron_cpu(uint32_t cluster, uint32_t cpu)
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{
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	/* set to 0 after BIG VPROC bulk on & before B-core power on seq. */
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	if (cpu >= 4U) {
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		mmio_write_32(DREQ20_BIG_VPROC_ISO, 0U);
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	}
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	mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, SSPM_ALL_PWR_CTRL_EN);
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	mmio_setbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWR_ON);
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	while (!spm_get_cpu_powerstate(cluster, cpu)) {
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	}
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	mmio_clrbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, SSPM_ALL_PWR_CTRL_EN);
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	/* Enable Big CPU Last PC */
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	if (cpu >= 4U) {
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		mmio_clrbits_32(LAST_PC_REG(cpu), BIT(3));
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	}
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}
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/**
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 * Power off a core with specified cluster and core index
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 *
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 * @cluster: the cluster ID of the CPU which to be powered off
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 * @cpu: the CPU ID of the CPU which to be powered off
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 */
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void spm_poweroff_cpu(uint32_t cluster, uint32_t cpu)
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{
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	/* Set mp0_spmc_pwr_on_cpuX = 0 */
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	mmio_clrbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWR_ON);
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}
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/**
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 * Power off a cluster with specified index
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 *
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 * @cluster: the cluster index which to be powered off
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 */
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void spm_poweroff_cluster(uint32_t cluster)
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{
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	/* No need to power on/off cluster on single cluster platform */
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	assert(false);
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}
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/**
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 * Power on a cluster with specified index
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 *
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 * @cluster: the cluster index which to be powered on
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 */
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void spm_poweron_cluster(uint32_t cluster)
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{
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	/* No need to power on/off cluster on single cluster platform */
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	assert(false);
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}
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