185 lines
5.7 KiB
C
185 lines
5.7 KiB
C
/*
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* Copyright (c) 2020, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MTSPMC_PRIVATE_H
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#define MTSPMC_PRIVATE_H
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#include <lib/utils_def.h>
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#include <platform_def.h>
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unsigned long read_cpuectlr(void);
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void write_cpuectlr(unsigned long cpuectlr);
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unsigned long read_cpupwrctlr_el1(void);
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void write_cpupwrctlr_el1(unsigned long cpuectlr);
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/*
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* per_cpu/cluster helper
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*/
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struct per_cpu_reg {
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unsigned int cluster_addr;
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unsigned int cpu_stride;
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};
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#define per_cpu(cluster, cpu, reg) \
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(reg[cluster].cluster_addr + (cpu << reg[cluster].cpu_stride))
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#define per_cluster(cluster, reg) (reg[cluster].cluster_addr)
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#define SPM_REG(ofs) (uint32_t)(SPM_BASE + (ofs))
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#define MCUCFG_REG(ofs) (uint32_t)(MCUCFG_BASE + (ofs))
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#define INFRACFG_AO_REG(ofs) (uint32_t)(INFRACFG_AO_BASE + (ofs))
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/* === SPMC related registers */
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#define SPM_POWERON_CONFIG_EN SPM_REG(0x000)
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/* bit-fields of SPM_POWERON_CONFIG_EN */
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#define PROJECT_CODE (U(0xb16) << 16)
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#define BCLK_CG_EN BIT(0)
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#define SPM_PWR_STATUS SPM_REG(0x16c)
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#define SPM_PWR_STATUS_2ND SPM_REG(0x170)
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#define SPM_CPU_PWR_STATUS SPM_REG(0x174)
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/* bit-fields of SPM_PWR_STATUS */
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#define MD BIT(0)
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#define CONN BIT(1)
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#define DDRPHY BIT(2)
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#define DISP BIT(3)
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#define MFG BIT(4)
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#define ISP BIT(5)
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#define INFRA BIT(6)
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#define VDEC BIT(7)
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#define MP0_CPUTOP BIT(8)
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#define MP0_CPU0 BIT(9)
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#define MP0_CPU1 BIT(10)
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#define MP0_CPU2 BIT(11)
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#define MP0_CPU3 BIT(12)
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#define MCUSYS BIT(14)
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#define MP0_CPU4 BIT(15)
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#define MP0_CPU5 BIT(16)
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#define MP0_CPU6 BIT(17)
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#define MP0_CPU7 BIT(18)
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#define VEN BIT(21)
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/* === SPMC related registers */
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#define SPM_MCUSYS_PWR_CON MCUCFG_REG(0xd200)
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#define SPM_MP0_CPUTOP_PWR_CON MCUCFG_REG(0xd204)
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#define SPM_MP0_CPU0_PWR_CON MCUCFG_REG(0xd208)
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#define SPM_MP0_CPU1_PWR_CON MCUCFG_REG(0xd20c)
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#define SPM_MP0_CPU2_PWR_CON MCUCFG_REG(0xd210)
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#define SPM_MP0_CPU3_PWR_CON MCUCFG_REG(0xd214)
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#define SPM_MP0_CPU4_PWR_CON MCUCFG_REG(0xd218)
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#define SPM_MP0_CPU5_PWR_CON MCUCFG_REG(0xd21c)
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#define SPM_MP0_CPU6_PWR_CON MCUCFG_REG(0xd220)
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#define SPM_MP0_CPU7_PWR_CON MCUCFG_REG(0xd224)
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/* bit fields of SPM_*_PWR_CON */
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#define PWR_ON_ACK BIT(31)
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#define VPROC_EXT_OFF BIT(7)
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#define DORMANT_EN BIT(6)
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#define RESETPWRON_CONFIG BIT(5)
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#define PWR_CLK_DIS BIT(4)
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#define PWR_ON BIT(2)
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#define PWR_RST_B BIT(0)
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/**** per_cpu registers for SPM_MP0_CPU?_PWR_CON */
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static const struct per_cpu_reg SPM_CPU_PWR[] = {
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{ .cluster_addr = SPM_MP0_CPU0_PWR_CON, .cpu_stride = 2U }
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};
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/**** per_cluster registers for SPM_MP0_CPUTOP_PWR_CON */
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static const struct per_cpu_reg SPM_CLUSTER_PWR[] = {
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{ .cluster_addr = SPM_MP0_CPUTOP_PWR_CON, .cpu_stride = 0U }
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};
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/* === MCUCFG related registers */
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/* aa64naa32 */
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#define MCUCFG_MP0_CLUSTER_CFG5 MCUCFG_REG(0xc8e4)
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/* reset vectors */
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#define MCUCFG_MP0_CLUSTER_CFG8 MCUCFG_REG(0xc900)
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#define MCUCFG_MP0_CLUSTER_CFG10 MCUCFG_REG(0xc908)
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#define MCUCFG_MP0_CLUSTER_CFG12 MCUCFG_REG(0xc910)
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#define MCUCFG_MP0_CLUSTER_CFG14 MCUCFG_REG(0xc918)
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#define MCUCFG_MP0_CLUSTER_CFG16 MCUCFG_REG(0xc920)
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#define MCUCFG_MP0_CLUSTER_CFG18 MCUCFG_REG(0xc928)
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#define MCUCFG_MP0_CLUSTER_CFG20 MCUCFG_REG(0xc930)
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#define MCUCFG_MP0_CLUSTER_CFG22 MCUCFG_REG(0xc938)
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/* MCUSYS DREQ BIG VPROC ISO control */
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#define DREQ20_BIG_VPROC_ISO MCUCFG_REG(0xad8c)
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/**** per_cpu registers for MCUCFG_MP0_CLUSTER_CFG? */
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static const struct per_cpu_reg MCUCFG_BOOTADDR[] = {
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{ .cluster_addr = MCUCFG_MP0_CLUSTER_CFG8, .cpu_stride = 3U }
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};
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/**** per_cpu registers for MCUCFG_MP0_CLUSTER_CFG5 */
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static const struct per_cpu_reg MCUCFG_INITARCH[] = {
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{ .cluster_addr = MCUCFG_MP0_CLUSTER_CFG5, .cpu_stride = 0U }
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};
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#define MCUCFG_INITARCH_CPU_BIT(cpu) BIT(16U + cpu)
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#define LAST_PC_REG(cpu) (MCUCFG_REG(0x308) + (cpu * 0x800))
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/* === CPC control */
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#define MCUCFG_CPC_FLOW_CTRL_CFG MCUCFG_REG(0xa814)
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#define MCUCFG_CPC_SPMC_PWR_STATUS MCUCFG_REG(0xa840)
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/* bit fields of CPC_FLOW_CTRL_CFG */
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#define CPC_CTRL_ENABLE BIT(16)
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#define SSPM_ALL_PWR_CTRL_EN BIT(13) /* for cpu-hotplug */
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#define GIC_WAKEUP_IGNORE(cpu) BIT(21 + cpu)
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/* bit fields of CPC_SPMC_PWR_STATUS */
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#define CORE_SPMC_PWR_ON_ACK GENMASK(15, 0)
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/* === APB Module infracfg_ao */
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#define INFRA_TOPAXI_PROTECTEN INFRACFG_AO_REG(0x0220)
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#define INFRA_TOPAXI_PROTECTEN_STA0 INFRACFG_AO_REG(0x0224)
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#define INFRA_TOPAXI_PROTECTEN_STA1 INFRACFG_AO_REG(0x0228)
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#define INFRA_TOPAXI_PROTECTEN_SET INFRACFG_AO_REG(0x02a0)
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#define INFRA_TOPAXI_PROTECTEN_CLR INFRACFG_AO_REG(0x02a4)
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#define INFRA_TOPAXI_PROTECTEN_1 INFRACFG_AO_REG(0x0250)
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#define INFRA_TOPAXI_PROTECTEN_STA0_1 INFRACFG_AO_REG(0x0254)
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#define INFRA_TOPAXI_PROTECTEN_STA1_1 INFRACFG_AO_REG(0x0258)
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#define INFRA_TOPAXI_PROTECTEN_1_SET INFRACFG_AO_REG(0x02a8)
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#define INFRA_TOPAXI_PROTECTEN_1_CLR INFRACFG_AO_REG(0x02ac)
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/* bit fields of INFRA_TOPAXI_PROTECTEN */
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#define MP0_SPMC_PROT_STEP1_0_MASK BIT(12)
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#define MP0_SPMC_PROT_STEP1_1_MASK (BIT(26) | BIT(12))
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/* === SPARK */
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#define VOLTAGE_04 U(0x40)
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#define VOLTAGE_05 U(0x60)
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#define PTP3_CPU0_SPMC_SW_CFG MCUCFG_REG(0x200)
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#define CPU0_ILDO_CONTROL5 MCUCFG_REG(0x334)
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#define CPU0_ILDO_CONTROL8 MCUCFG_REG(0x340)
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/* bit fields of CPU0_ILDO_CONTROL5 */
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#define ILDO_RET_VOSEL GENMASK(7, 0)
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/* bit fields of PTP3_CPU_SPMC_SW_CFG */
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#define SW_SPARK_EN BIT(0)
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/* bit fields of CPU0_ILDO_CONTROL8 */
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#define ILDO_BYPASS_B BIT(0)
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static const struct per_cpu_reg MCUCFG_SPARK[] = {
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{ .cluster_addr = PTP3_CPU0_SPMC_SW_CFG, .cpu_stride = 11U }
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};
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static const struct per_cpu_reg ILDO_CONTROL5[] = {
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{ .cluster_addr = CPU0_ILDO_CONTROL5, .cpu_stride = 11U }
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};
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static const struct per_cpu_reg ILDO_CONTROL8[] = {
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{ .cluster_addr = CPU0_ILDO_CONTROL8, .cpu_stride = 11U }
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};
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#endif /* MTSPMC_PRIVATE_H */
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