159 lines
5.1 KiB
C
159 lines
5.1 KiB
C
/*
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <platform_def.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/console.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#include <ddr_parameter.h>
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#include <plat_private.h>
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#include <rk3328_def.h>
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#include <soc.h>
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/* Table of regions to map using the MMU. */
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const mmap_region_t plat_rk_mmap[] = {
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MAP_REGION_FLAT(UART0_BASE, UART0_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(UART1_BASE, UART1_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(UART2_BASE, UART2_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(PMU_BASE, PMU_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(SGRF_BASE, SGRF_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(GPIO0_BASE, GPIO0_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(GPIO1_BASE, GPIO1_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(GPIO2_BASE, GPIO2_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(GPIO3_BASE, GPIO3_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(CRU_BASE, CRU_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(GRF_BASE, GRF_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(FIREWALL_DDR_BASE, FIREWALL_DDR_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(FIREWALL_CFG_BASE, FIREWALL_CFG_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(STIME_BASE, STIME_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(GIC400_BASE, GIC400_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(PMUSRAM_BASE, PMUSRAM_SIZE,
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MT_MEMORY | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(SHARE_MEM_BASE, SHARE_MEM_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(DDR_GRF_BASE, DDR_GRF_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(DDR_UPCTL_BASE, DDR_UPCTL_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(PWM_BASE, PWM_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(DDR_PARAM_BASE, DDR_PARAM_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(EFUSE8_BASE, EFUSE8_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(EFUSE32_BASE, EFUSE32_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(DDR_PHY_BASE, DDR_PHY_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(SERVER_MSCH_BASE, SERVER_MSCH_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(DDR_MONITOR_BASE, DDR_MONITOR_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(VOP_BASE, VOP_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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{ 0 }
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};
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/* The RockChip power domain tree descriptor */
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const unsigned char rockchip_power_domain_tree_desc[] = {
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/* No of root nodes */
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PLATFORM_SYSTEM_COUNT,
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/* No of children for the root node */
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PLATFORM_CLUSTER_COUNT,
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/* No of children for the first cluster node */
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PLATFORM_CLUSTER0_CORE_COUNT,
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};
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void secure_timer_init(void)
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{
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mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOADE_COUNT0, 0xffffffff);
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mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOADE_COUNT1, 0xffffffff);
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/* auto reload & enable the timer */
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mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG, TIMER_EN);
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}
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void sgrf_init(void)
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{
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#ifdef PLAT_RK_SECURE_DDR_MINILOADER
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uint32_t i, val;
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struct param_ddr_usage usg;
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/* general secure regions */
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usg = ddr_region_usage_parse(DDR_PARAM_BASE,
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PLAT_MAX_DDR_CAPACITY_MB);
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for (i = 0; i < usg.s_nr; i++) {
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/* enable secure */
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val = mmio_read_32(FIREWALL_DDR_BASE +
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FIREWALL_DDR_FW_DDR_CON_REG);
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val |= BIT(7 - i);
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mmio_write_32(FIREWALL_DDR_BASE +
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FIREWALL_DDR_FW_DDR_CON_REG, val);
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/* map top and base */
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mmio_write_32(FIREWALL_DDR_BASE +
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FIREWALL_DDR_FW_DDR_RGN(7 - i),
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RG_MAP_SECURE(usg.s_top[i], usg.s_base[i]));
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}
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#endif
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/* set ddr rgn0_top and rga0_top as 0 */
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mmio_write_32(FIREWALL_DDR_BASE + FIREWALL_DDR_FW_DDR_RGN(0), 0x0);
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/* set all slave ip into no-secure, except stimer */
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mmio_write_32(FIREWALL_CFG_BASE + FIREWALL_CFG_FW_SYS_CON(0),
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SGRF_SLV_S_ALL_NS);
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mmio_write_32(FIREWALL_CFG_BASE + FIREWALL_CFG_FW_SYS_CON(1),
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SGRF_SLV_S_ALL_NS);
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mmio_write_32(FIREWALL_CFG_BASE + FIREWALL_CFG_FW_SYS_CON(2),
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SGRF_SLV_S_ALL_NS | STIMER_S);
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mmio_write_32(FIREWALL_CFG_BASE + FIREWALL_CFG_FW_SYS_CON(3),
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SGRF_SLV_S_ALL_NS);
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/* set all master ip into no-secure */
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mmio_write_32(SGRF_BASE + SGRF_SOC_CON(2), 0xf0000000);
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mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), SGRF_MST_S_ALL_NS);
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mmio_write_32(SGRF_BASE + SGRF_SOC_CON(4), SGRF_MST_S_ALL_NS);
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/* set DMAC into no-secure */
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mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(3), DMA_IRQ_BOOT_NS);
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mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(4), DMA_PERI_CH_NS_15_0);
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mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(5), DMA_PERI_CH_NS_19_16);
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mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(5), DMA_MANAGER_BOOT_NS);
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/* soft reset dma before use */
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mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(3), DMA_SOFTRST_REQ);
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udelay(5);
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mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(3), DMA_SOFTRST_RLS);
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}
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void plat_rockchip_soc_init(void)
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{
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secure_timer_init();
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sgrf_init();
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NOTICE("BL31:Rockchip release version: v%d.%d\n",
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MAJOR_VERSION, MINOR_VERSION);
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}
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