112 lines
3.5 KiB
C
112 lines
3.5 KiB
C
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SOC_H
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#define SOC_H
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/******************************* stimer ***************************************/
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#define TIMER_LOADE_COUNT0 0x00
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#define TIMER_LOADE_COUNT1 0x04
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#define TIMER_CURRENT_VALUE0 0x08
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#define TIMER_CURRENT_VALUE1 0x0C
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#define TIMER_CONTROL_REG 0x10
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#define TIMER_INTSTATUS 0x18
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#define TIMER_EN 0x1
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/**************************** read/write **************************************/
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#ifndef BITS_WMSK
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#define BITS_WMSK(msk, shift) ((msk) << (shift + REG_MSK_SHIFT))
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#endif
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/**************************** cru *********************************************/
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enum plls_id {
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APLL_ID = 0,
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DPLL_ID,
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CPLL_ID,
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GPLL_ID,
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REVERVE,
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NPLL_ID,
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MAX_PLL,
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};
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#define CRU_CRU_MODE 0x0080
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#define CRU_CRU_MISC 0x0084
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#define CRU_GLB_SRST_FST 0x009c
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#define CRU_GLB_SRST_FST_VALUE 0xfdb9
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#define PLL_CONS(id, i) (0x020 * (id) + ((i) * 4))
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#define CRU_CLKSEL_CON(i) (0x100 + ((i) * 4))
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#define CRU_CLKSEL_NUMS 53
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#define CRU_CLKGATE_CON(i) (0x200 + ((i) * 4))
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#define CRU_CLKGATE_NUMS 29
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#define CRU_SOFTRSTS_CON(n) (0x300 + ((n) * 4))
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#define CRU_SOFTRSTS_NUMS 12
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#define CRU_PLL_CON_NUMS 5
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/* PLLn_CON1 */
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#define PLL_IS_LOCKED BIT(10)
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/* PLLn_CON0 */
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#define PLL_BYPASS BITS_WITH_WMASK(1, 0x1, 15)
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#define PLL_NO_BYPASS BITS_WITH_WMASK(0, 0x1, 15)
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/* CRU_MODE */
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#define PLL_SLOW_MODE(id) ((id) == NPLL_ID) ? \
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BITS_WITH_WMASK(0, 0x1, 1) : \
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BITS_WITH_WMASK(0, 0x1, ((id) * 4))
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#define PLL_NORM_MODE(id) ((id) == NPLL_ID) ? \
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BITS_WITH_WMASK(1, 0x1, 1) : \
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BITS_WITH_WMASK(1, 0x1, ((id) * 4))
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#define CRU_GATEID_CONS(ID) (0x200 + (ID / 16) * 4)
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#define CRU_CONS_GATEID(i) (16 * (i))
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#define GATE_ID(reg, bit) ((reg * 16) + bit)
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#define PLL_LOCKED_TIMEOUT 600000U
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#define STIMER_CHN_BASE(n) (STIME_BASE + 0x20 * (n))
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/************************** config regs ***************************************/
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#define FIREWALL_CFG_FW_SYS_CON(n) (0x000 + (n) * 4)
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#define FIREWALL_DDR_FW_DDR_RGN(n) (0x000 + (n) * 4)
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#define FIREWALL_DDR_FW_DDR_MST(n) (0x020 + (n) * 4)
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#define FIREWALL_DDR_FW_DDR_CON_REG (0x040)
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#define GRF_SOC_CON(n) (0x400 + (n) * 4)
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#define GRF_SOC_STATUS(n) (0x480 + (n) * 4)
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#define GRF_CPU_STATUS(n) (0x520 + (n) * 4)
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#define GRF_OS_REG(n) (0x5c8 + (n) * 4)
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#define DDRGRF_SOC_CON(n) (0x000 + (n) * 4)
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#define DDRGRF_SOC_STATUS(n) (0x100 + (n) * 4)
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#define SGRF_SOC_CON(n) (0x000 + (n) * 4)
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#define SGRF_DMAC_CON(n) (0x100 + (n) * 4)
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#define SGRF_HDCP_KEY_CON(n) (0x280 + (n) * 4)
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#define DDR_PCTL2_PWRCTL 0x30
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/************************** regs func *****************************************/
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#define STIMER_S BIT(23)
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#define SGRF_SLV_S_ALL_NS 0x0
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#define SGRF_MST_S_ALL_NS 0xffffffff
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#define DMA_IRQ_BOOT_NS 0xffffffff
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#define DMA_MANAGER_BOOT_NS 0x80008000
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#define DMA_PERI_CH_NS_15_0 0xffffffff
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#define DMA_PERI_CH_NS_19_16 0x000f000f
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#define DMA_SOFTRST_REQ 0x01000100
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#define DMA_SOFTRST_RLS 0x01000000
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#define SELFREF_EN BIT(0)
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/************************** cpu ***********************************************/
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#define CPU_BOOT_ADDR_WMASK 0xffff0000
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#define CPU_BOOT_ADDR_ALIGN 16
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/************************** ddr secure region *********************************/
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#define PLAT_MAX_DDR_CAPACITY_MB 4096
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#define RG_MAP_SECURE(top, base) ((((top) - 1) << 16) | (base))
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/************************** gpio2_d2 ******************************************/
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#define SWPORTA_DR 0x00
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#define SWPORTA_DDR 0x04
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#define GPIO2_D2 BIT(26)
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#define GPIO2_D2_GPIO_MODE 0x30
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#define GRF_GPIO2D_IOMUX 0x34
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#endif /* SOC_H */
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