118 lines
3.9 KiB
C
118 lines
3.9 KiB
C
/*
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <arch.h>
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#include <plat/common/common_def.h>
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#include <rk3328_def.h>
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/*******************************************************************************
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* Platform binary types for linking
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******************************************************************************/
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#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
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#define PLATFORM_LINKER_ARCH aarch64
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/*******************************************************************************
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* Generic platform constants
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******************************************************************************/
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/* Size of cacheable stacks */
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#if defined(IMAGE_BL1)
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#define PLATFORM_STACK_SIZE 0x440
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#elif defined(IMAGE_BL2)
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#define PLATFORM_STACK_SIZE 0x400
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#elif defined(IMAGE_BL31)
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#define PLATFORM_STACK_SIZE 0x800
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#elif defined(IMAGE_BL32)
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#define PLATFORM_STACK_SIZE 0x440
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#endif
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#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
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#define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2
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#define PLATFORM_SYSTEM_COUNT 1
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#define PLATFORM_CLUSTER_COUNT U(1)
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#define PLATFORM_CLUSTER0_CORE_COUNT U(4)
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#define PLATFORM_CLUSTER1_CORE_COUNT U(0)
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \
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PLATFORM_CLUSTER0_CORE_COUNT)
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#define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \
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PLATFORM_CLUSTER_COUNT + \
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PLATFORM_CORE_COUNT)
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#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
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#define PLAT_RK_CLST_TO_CPUID_SHIFT 6
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/*
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* This macro defines the deepest retention state possible. A higher state
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* id will represent an invalid or a power down state.
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*/
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#define PLAT_MAX_RET_STATE U(1)
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/*
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* This macro defines the deepest power down states possible. Any state ID
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* higher than this is invalid.
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*/
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#define PLAT_MAX_OFF_STATE U(2)
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/*******************************************************************************
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* Platform memory map related constants
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******************************************************************************/
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/* TF text, ro, rw, Size: 1MB */
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#define TZRAM_BASE (0x0)
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#define TZRAM_SIZE (0x100000)
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/*******************************************************************************
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* BL31 specific defines.
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******************************************************************************/
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/*
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* Put BL3-1 at the top of the Trusted RAM
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*/
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#define BL31_BASE (TZRAM_BASE + 0x40000)
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#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
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/*******************************************************************************
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* Platform specific page table and MMU setup constants
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******************************************************************************/
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
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#define MAX_XLAT_TABLES 9
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#define MAX_MMAP_REGIONS 33
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/*******************************************************************************
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* Declarations and constants to access the mailboxes safely. Each mailbox is
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* aligned on the biggest cache line size in the platform. This is known only
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* to the platform as it might have a combination of integrated and external
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* caches. Such alignment ensures that two maiboxes do not sit on the same cache
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* line at any cache level. They could belong to different cpus/clusters &
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* get written while being protected by different locks causing corruption of
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* a valid mailbox address.
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******************************************************************************/
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#define CACHE_WRITEBACK_SHIFT 6
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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/*
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* Define GICD and GICC and GICR base
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*/
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#define PLAT_RK_GICD_BASE RK3328_GICD_BASE
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#define PLAT_RK_GICC_BASE RK3328_GICC_BASE
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#define PLAT_RK_UART_BASE UART2_BASE
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#define PLAT_RK_UART_CLOCK RK3328_UART_CLOCK
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#define PLAT_RK_UART_BAUDRATE RK3328_BAUDRATE
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#define PLAT_RK_PRIMARY_CPU 0x0
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#define PSRAM_DO_DDR_RESUME 0
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#define PSRAM_CHECK_WAKEUP_CPU 0
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#endif /* PLATFORM_DEF_H */
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