143 lines
3.6 KiB
C
143 lines
3.6 KiB
C
// Copyright 2015, VIXL authors
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// * Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// * Neither the name of ARM Limited nor the names of its contributors may be
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// used to endorse or promote products derived from this software without
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// specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
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// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ---------------------------------------------------------------------
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// This file is auto generated using tools/generate_simulator_traces.py.
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//
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// PLEASE DO NOT EDIT.
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// ---------------------------------------------------------------------
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#ifndef VIXL_SIM_FCVTNS_XH_TRACE_AARCH64_H_
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#define VIXL_SIM_FCVTNS_XH_TRACE_AARCH64_H_
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const int64_t kExpected_fcvtns_xh[] = {
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INT64_C(0),
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INT64_C(0),
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INT64_C(0),
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INT64_C(0),
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INT64_C(1),
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INT64_C(1),
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INT64_C(1),
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INT64_C(1),
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INT64_C(2),
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INT64_C(10),
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INT64_C(65504),
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INT64_C(9223372036854775807),
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INT64_C(0),
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INT64_C(0),
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INT64_C(0),
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INT64_C(0),
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INT64_C(0),
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INT64_C(0),
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INT64_C(0),
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INT64_C(0),
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INT64_C(0),
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INT64_C(0),
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INT64_C(0),
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-INT64_C(1),
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-INT64_C(1),
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-INT64_C(1),
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-INT64_C(1),
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-INT64_C(2),
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-INT64_C(10),
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-INT64_C(65504),
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-INT64_C(9223372036854775807) - 1,
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INT64_C(0),
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INT64_C(0),
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INT64_C(0),
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INT64_C(0),
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INT64_C(0),
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INT64_C(0),
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INT64_C(0),
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INT64_C(1024),
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INT64_C(1025),
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INT64_C(1026),
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INT64_C(1027),
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INT64_C(1347),
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INT64_C(2044),
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INT64_C(2045),
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INT64_C(2046),
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INT64_C(2047),
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INT64_C(512),
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INT64_C(512),
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INT64_C(513),
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INT64_C(514),
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INT64_C(912),
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INT64_C(1022),
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INT64_C(1022),
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INT64_C(1023),
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INT64_C(1024),
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INT64_C(256),
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INT64_C(256),
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INT64_C(256),
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INT64_C(257),
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INT64_C(332),
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INT64_C(511),
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INT64_C(511),
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INT64_C(512),
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INT64_C(512),
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-INT64_C(1024),
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-INT64_C(1025),
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-INT64_C(1026),
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-INT64_C(1027),
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-INT64_C(1347),
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-INT64_C(2044),
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-INT64_C(2045),
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-INT64_C(2046),
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-INT64_C(2047),
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-INT64_C(512),
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-INT64_C(512),
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-INT64_C(513),
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-INT64_C(514),
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-INT64_C(912),
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-INT64_C(1022),
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-INT64_C(1022),
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-INT64_C(1023),
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-INT64_C(1024),
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-INT64_C(256),
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-INT64_C(256),
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-INT64_C(256),
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-INT64_C(257),
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-INT64_C(332),
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-INT64_C(511),
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-INT64_C(511),
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-INT64_C(512),
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-INT64_C(512),
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INT64_C(0),
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INT64_C(0),
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INT64_C(0),
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INT64_C(0),
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INT64_C(0),
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INT64_C(0),
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INT64_C(0),
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INT64_C(0),
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INT64_C(0),
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};
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const unsigned kExpectedCount_fcvtns_xh = 101;
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#endif // VIXL_SIM_FCVTNS_XH_TRACE_AARCH64_H_
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