717 lines
17 KiB
Plaintext
717 lines
17 KiB
Plaintext
/*
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* (C) Copyright 2016 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/rv1108-cru.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/media/rockchip_mipi_dsi.h>
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#include <linux/media-bus-format.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "rockchip,rv1108";
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interrupt-parent = <&gic>;
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aliases {
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i2c0 = &i2c0;
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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spi0 = &sfc;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@f00 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0xf00>;
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};
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};
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arm-pmu {
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compatible = "arm,cortex-a7-pmu";
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interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
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};
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display_subsystem: display-subsystem {
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compatible = "rockchip,display-subsystem";
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ports = <&vop_out>;
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status = "disabled";
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route {
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route_dsi: route-dsi {
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status = "okay";
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logo,uboot = "logo.bmp";
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logo,kernel = "logo_kernel.bmp";
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logo,mode = "center";
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charge_logo,mode = "center";
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connect = <&vop_out_mipi>;
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};
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};
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};
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mipi_dphy: mipi-dphy@0x20228000 {
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compatible = "rockchip,rv1108-mipi-dphy";
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reg = <0x20228000 0x8000>;
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clock-output-names = "mipi_dphy_pll";
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#clock-cells = <0>;
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resets = <&cru PRST_MIPI_DSI_PHY>;
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reset-names = "apb";
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#phy-cells = <0>;
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status = "disabled";
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};
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dsi: dsi@300e0000 {
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compatible = "rockchip,rv1108-mipi-dsi";
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reg = <0x300e0000 0x10000>;
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_MIPI_DSI>, <&mipi_dphy>;
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clock-names = "pclk", "hs_clk";
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resets = <&cru 127>;
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reset-names = "apb";
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phys = <&mipi_dphy>;
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phy-names = "mipi_dphy";
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rockchip,grf = <&grf>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&lcdc_mipi_data>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi_in_vop: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&vop_out_mipi>;
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};
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};
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
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clock-frequency = <24000000>;
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};
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xin24m: oscillator {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "xin24m";
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#clock-cells = <0>;
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};
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amba {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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pdma: pdma@102a0000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x102a0000 0x4000>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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arm,pl330-broken-no-flushp;
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clocks = <&cru ACLK_DMAC>;
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clock-names = "apb_pclk";
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};
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};
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bus_intmem@10080000 {
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compatible = "mmio-sram";
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reg = <0x10080000 0x2000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x10080000 0x2000>;
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};
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uart2: serial@10210000 {
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compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
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reg = <0x10210000 0x100>;
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clock-frequency = <24000000>;
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clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
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clock-names = "baudclk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&uart2m0_xfer>;
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status = "disabled";
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};
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uart1: serial@10220000 {
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compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
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reg = <0x10220000 0x100>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clock-frequency = <24000000>;
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clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
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clock-names = "baudclk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_xfer>;
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status = "disabled";
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};
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uart0: serial@10230000 {
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compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
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reg = <0x10230000 0x100>;
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clock-frequency = <24000000>;
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clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
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clock-names = "baudclk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
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status = "disabled";
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};
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grf: syscon@10300000 {
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compatible = "rockchip,rv1108-grf", "syscon";
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reg = <0x10300000 0x1000>;
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};
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u2phy: usb2-phy@10300100 {
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compatible = "rockchip,rv1108-usb2phy";
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reg = <0x100 0x0c>;
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rockchip,grf = <&grf>;
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#phy-cells = <1>;
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status = "disabled";
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u2phy_otg: otg-port {
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interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "otg-mux";
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#phy-cells = <0>;
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status = "disabled";
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};
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u2phy_host: host-port {
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interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "linestate";
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#phy-cells = <0>;
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status = "disabled";
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};
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};
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saradc: saradc@1038c000 {
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compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc";
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reg = <0x1038c000 0x100>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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#io-channel-cells = <1>;
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clock-frequency = <1000000>;
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clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
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clock-names = "saradc", "apb_pclk";
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status = "disabled";
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};
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pwm0: pwm@20040000 {
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compatible = "rockchip,rk1108-pwm", "rockchip,rk3328-pwm";
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reg = <0x20040000 0x10>;
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
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#pwm-cells = <3>;
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pinctrl-names = "active";
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pinctrl-0 = <&pwm0_pin>;
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clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
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clock-names = "pwm", "pclk";
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status = "disabled";
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};
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pmugrf: syscon@20060000 {
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compatible = "rockchip,rv1108-pmugrf", "syscon";
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reg = <0x20060000 0x1000>;
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};
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cru: clock-controller@20200000 {
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compatible = "rockchip,rv1108-cru";
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reg = <0x20200000 0x1000>;
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rockchip,grf = <&grf>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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i2c0: i2c@20000000 {
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compatible = "rockchip,rv1108-i2c";
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reg = <0x20000000 0x1000>;
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interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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rockchip,grf = <&grf>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&cru SCLK_I2C0_PMU>, <&cru PCLK_I2C0_PMU>;
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clock-names = "i2c", "pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_xfer>;
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status = "disabled";
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};
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usbgrf: syscon@202a0000 {
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compatible = "rockchip,rv1108-usbgrf", "syscon";
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reg = <0x202a0000 0x1000>;
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};
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nandc: nandc@30100000 {
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compatible = "rockchip,rk-nandc";
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reg = <0x30100000 0x1000>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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nandc_id = <0>;
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clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>;
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clock-names = "clk_nandc", "hclk_nandc";
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status = "disabled";
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};
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emmc: dwmmc@30110000 {
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compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
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clock-freq-min-max = <400000 150000000>;
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clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
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<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
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clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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fifo-depth = <0x100>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x30110000 0x4000>;
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status = "disabled";
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};
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sdio: dwmmc@30120000 {
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compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
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clock-freq-min-max = <400000 150000000>;
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clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
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<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
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clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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fifo-depth = <0x100>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x30120000 0x4000>;
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status = "disabled";
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};
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sdmmc: dwmmc@30130000 {
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compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
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clock-freq-min-max = <400000 100000000>;
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clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
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<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
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clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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cd-gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
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fifo-depth = <0x100>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x30130000 0x4000>;
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status = "disabled";
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};
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usb_host_ehci: usb@30140000 {
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compatible = "generic-ehci";
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reg = <0x30140000 0x20000>;
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&u2phy_host>;
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phy-names = "usb";
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status = "disabled";
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};
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usb_host_ohci: usb@30160000 {
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compatible = "generic-ohci";
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reg = <0x30160000 0x20000>;
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&u2phy_host>;
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phy-names = "usb";
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status = "disabled";
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};
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usb20_otg: usb@30180000 {
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compatible = "rockchip,rv1108-usb", "rockchip,rk3288-usb",
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"snps,dwc2";
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reg = <0x30180000 0x40000>;
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
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hnp-srp-disable;
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dr_mode = "otg";
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phys = <&u2phy_otg>;
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phy-names = "usb";
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status = "disabled";
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};
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sfc: sfc@301c0000 {
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compatible = "rockchip,sfc";
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reg = <0x301c0000 0x200>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
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clock-names = "clk_sfc", "hclk_sfc";
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pinctrl-0 = <&sfc_pins>;
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pinctrl-names = "default";
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status = "disabled";
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};
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gmac: ethernet@30200000 {
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compatible = "rockchip,rv1108-gmac";
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reg = <0x30200000 0x10000>;
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interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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rockchip,grf = <&grf>;
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clocks = <&cru SCLK_MAC>,
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<&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
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<&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>,
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<&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
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clock-names = "stmmaceth",
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"mac_clk_rx", "mac_clk_tx",
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"clk_mac_ref", "clk_mac_refout",
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"aclk_mac", "pclk_mac";
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pinctrl-names = "default";
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pinctrl-0 = <&rmii_pins>;
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phy-mode = "rmii";
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max-speed = <100>;
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status = "disabled";
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};
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gic: interrupt-controller@32010000 {
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compatible = "arm,gic-400";
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interrupt-controller;
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#interrupt-cells = <3>;
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#address-cells = <0>;
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reg = <0x32011000 0x1000>,
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<0x32012000 0x1000>,
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<0x32014000 0x2000>,
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<0x32016000 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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pinctrl: pinctrl {
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compatible = "rockchip,rv1108-pinctrl";
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rockchip,grf = <&grf>;
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rockchip,pmu = <&pmugrf>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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gpio0: gpio0@20030000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x20030000 0x100>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&xin24m>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio1: gpio1@10310000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x10310000 0x100>;
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interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&xin24m>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio2: gpio2@10320000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x10320000 0x100>;
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interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&xin24m>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio3: gpio3@10330000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x10330000 0x100>;
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interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&xin24m>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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pcfg_pull_up: pcfg-pull-up {
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bias-pull-up;
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};
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pcfg_pull_down: pcfg-pull-down {
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bias-pull-down;
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};
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pcfg_pull_none: pcfg-pull-none {
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bias-disable;
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};
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pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
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drive-strength = <8>;
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};
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pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
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drive-strength = <12>;
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};
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pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
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bias-pull-up;
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drive-strength = <8>;
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};
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pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
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drive-strength = <4>;
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};
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pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
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bias-pull-up;
|
|
drive-strength = <4>;
|
|
};
|
|
|
|
pcfg_pull_none_smt: pcfg-pull-none-smt {
|
|
bias-disable;
|
|
input-schmitt-enable;
|
|
};
|
|
|
|
pcfg_output_high: pcfg-output-high {
|
|
output-high;
|
|
};
|
|
|
|
pcfg_output_low: pcfg-output-low {
|
|
output-low;
|
|
};
|
|
|
|
pcfg_input_high: pcfg-input-high {
|
|
bias-pull-up;
|
|
input-enable;
|
|
};
|
|
|
|
pwm0 {
|
|
pwm0_pin: pwm0-pin {
|
|
rockchip,pins = <0 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
gmac {
|
|
rmii_pins: rmii-pins {
|
|
rockchip,pins = <1 RK_PC5 RK_FUNC_2 &pcfg_pull_none>,
|
|
<1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>,
|
|
<1 RK_PC4 RK_FUNC_2 &pcfg_pull_none>,
|
|
<1 RK_PB2 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
|
|
<1 RK_PB3 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
|
|
<1 RK_PB4 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
|
|
<1 RK_PB5 RK_FUNC_3 &pcfg_pull_none>,
|
|
<1 RK_PB6 RK_FUNC_3 &pcfg_pull_none>,
|
|
<1 RK_PB7 RK_FUNC_3 &pcfg_pull_none>,
|
|
<1 RK_PC2 RK_FUNC_3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
gpio1_lcdc {
|
|
lcdc_mipi_data: lcdc-mipi_data {
|
|
rockchip,pins = <1 RK_PA0 RK_FUNC_1 &pcfg_pull_none>, /* DSI_CLKP */
|
|
<1 RK_PA1 RK_FUNC_1 &pcfg_pull_none>, /* DSI_CLKN */
|
|
<1 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, /* D0P */
|
|
<1 RK_PA3 RK_FUNC_1 &pcfg_pull_none>, /* D0N */
|
|
<1 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, /* D1P */
|
|
<1 RK_PA5 RK_FUNC_1 &pcfg_pull_none>, /* D1N */
|
|
<1 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, /* D2P */
|
|
<1 RK_PA7 RK_FUNC_1 &pcfg_pull_none>, /* D2N */
|
|
<1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, /* D3P */
|
|
<1 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, /* D3N */
|
|
<1 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, /* D10 */
|
|
<1 RK_PC0 RK_FUNC_1 &pcfg_pull_none>; /* D11 */
|
|
};
|
|
};
|
|
|
|
i2c0 {
|
|
i2c0_xfer: i2c0-xfer {
|
|
rockchip,pins = <0 RK_PB1 RK_FUNC_1 &pcfg_pull_none_smt>,
|
|
<0 RK_PB2 RK_FUNC_1 &pcfg_pull_none_smt>;
|
|
};
|
|
};
|
|
|
|
i2c1 {
|
|
i2c1_xfer: i2c1-xfer {
|
|
rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
|
|
<2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
i2c2m1 {
|
|
i2c2m1_xfer: i2c2m1-xfer {
|
|
rockchip,pins = <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>,
|
|
<0 RK_PC6 RK_FUNC_3 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2c2m1_gpio: i2c2m1-gpio {
|
|
rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
|
|
<0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c2m05v {
|
|
i2c2m05v_xfer: i2c2m05v-xfer {
|
|
rockchip,pins = <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>,
|
|
<1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2c2m05v_gpio: i2c2m05v-gpio {
|
|
rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
|
|
<1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c3 {
|
|
i2c3_xfer: i2c3-xfer {
|
|
rockchip,pins = <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
|
|
<0 RK_PC4 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
sfc {
|
|
sfc_pins: sfc-pins {
|
|
rockchip,pins = <2 RK_PA3 RK_FUNC_3 &pcfg_pull_none>,
|
|
<2 RK_PA2 RK_FUNC_3 &pcfg_pull_none>,
|
|
<2 RK_PA1 RK_FUNC_3 &pcfg_pull_none>,
|
|
<2 RK_PA0 RK_FUNC_3 &pcfg_pull_none>,
|
|
<2 RK_PB7 RK_FUNC_2 &pcfg_pull_none>,
|
|
<2 RK_PB4 RK_FUNC_3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
sdmmc {
|
|
sdmmc_clk: sdmmc-clk {
|
|
rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
|
|
};
|
|
|
|
sdmmc_cmd: sdmmc-cmd {
|
|
rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
|
|
};
|
|
|
|
sdmmc_cd: sdmmc-cd {
|
|
rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
|
|
};
|
|
|
|
sdmmc_bus1: sdmmc-bus1 {
|
|
rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
|
|
};
|
|
|
|
sdmmc_bus4: sdmmc-bus4 {
|
|
rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
|
|
<3 RK_PC2 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
|
|
<3 RK_PC1 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
|
|
<3 RK_PC0 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
|
|
};
|
|
};
|
|
|
|
uart0 {
|
|
uart0_xfer: uart0-xfer {
|
|
rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>,
|
|
<3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart0_cts: uart0-cts {
|
|
rockchip,pins = <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart0_rts: uart0-rts {
|
|
rockchip,pins = <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart0_rts_gpio: uart0-rts-gpio {
|
|
rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart1 {
|
|
uart1_xfer: uart1-xfer {
|
|
rockchip,pins = <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
|
|
<1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart1_cts: uart1-cts {
|
|
rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart01rts: uart1-rts {
|
|
rockchip,pins = <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart2m0 {
|
|
uart2m0_xfer: uart2m0-xfer {
|
|
rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>,
|
|
<2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart2m1 {
|
|
uart2m1_xfer: uart2m1-xfer {
|
|
rockchip,pins = <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up>,
|
|
<3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart2_5v {
|
|
uart2_5v_cts: uart2_5v-cts {
|
|
rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart2_5v_rts: uart2_5v-rts {
|
|
rockchip,pins = <1 RK_PD5 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
};
|
|
|
|
dmc: dmc@202b0000 {
|
|
compatible = "rockchip,rv1108-dmc";
|
|
reg = <0x202b0000 0x400
|
|
0x20210000 0x400
|
|
0x31070000 0x40
|
|
0x10300000 0xf94
|
|
0x20060000 0x38c
|
|
0x20200000 0x1f0
|
|
0x20010000 0x78>;
|
|
};
|
|
|
|
vop: vop@30040000 {
|
|
compatible = "rockchip,rv1108-vop";
|
|
reg = <0x30040000 0xe00>;
|
|
reg-names = "regs";
|
|
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>,
|
|
<&cru HCLK_VOP>;
|
|
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
|
|
status = "disabled";
|
|
|
|
vop_out: port {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
vop_out_mipi: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&mipi_in_vop>;
|
|
};
|
|
};
|
|
};
|
|
};
|