1748 lines
44 KiB
C
1748 lines
44 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
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*/
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#include <common.h>
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#include <bitfield.h>
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#include <thermal.h>
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#include <dm.h>
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#include <dm/pinctrl.h>
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#include <div64.h>
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#include <errno.h>
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#include <syscon.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/hardware.h>
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#include <asm/io.h>
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#include <dm/lists.h>
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#include <clk.h>
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#include <clk-uclass.h>
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#include <reset.h>
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DECLARE_GLOBAL_DATA_PTR;
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/**
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* If the temperature over a period of time High,
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* the resulting TSHUT gave CRU module,let it reset the entire chip,
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* or via GPIO give PMIC.
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*/
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enum tshut_mode {
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TSHUT_MODE_CRU = 0,
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TSHUT_MODE_GPIO,
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};
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/**
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* The system Temperature Sensors tshut(tshut) polarity
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* the bit 8 is tshut polarity.
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* 0: low active, 1: high active
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*/
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enum tshut_polarity {
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TSHUT_LOW_ACTIVE = 0,
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TSHUT_HIGH_ACTIVE,
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};
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/**
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* The conversion table has the adc value and temperature.
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* ADC_DECREMENT: the adc value is of diminishing.(e.g. rk3288_code_table)
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* ADC_INCREMENT: the adc value is incremental.(e.g. rk3368_code_table)
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*/
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enum adc_sort_mode {
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ADC_DECREMENT = 0,
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ADC_INCREMENT,
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};
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#define SOC_MAX_SENSORS 7
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#define TSADCV2_USER_CON 0x00
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#define TSADCV2_AUTO_CON 0x04
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#define TSADCV2_INT_EN 0x08
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#define TSADCV2_INT_PD 0x0c
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#define TSADCV3_AUTO_SRC_CON 0x0c
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#define TSADCV3_HT_INT_EN 0x14
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#define TSADCV3_HSHUT_GPIO_INT_EN 0x18
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#define TSADCV3_HSHUT_CRU_INT_EN 0x1c
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#define TSADCV3_INT_PD 0x24
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#define TSADCV3_HSHUT_PD 0x28
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#define TSADCV2_DATA(chn) (0x20 + (chn) * 0x04)
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#define TSADCV2_COMP_INT(chn) (0x30 + (chn) * 0x04)
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#define TSADCV2_COMP_SHUT(chn) (0x40 + (chn) * 0x04)
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#define TSADCV3_DATA(chn) (0x2c + (chn) * 0x04)
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#define TSADCV3_COMP_INT(chn) (0x6c + (chn) * 0x04)
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#define TSADCV3_COMP_SHUT(chn) (0x10c + (chn) * 0x04)
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#define TSADCV2_HIGHT_INT_DEBOUNCE 0x60
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#define TSADCV2_HIGHT_TSHUT_DEBOUNCE 0x64
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#define TSADCV3_HIGHT_INT_DEBOUNCE 0x14c
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#define TSADCV3_HIGHT_TSHUT_DEBOUNCE 0x150
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#define TSADCV2_AUTO_PERIOD 0x68
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#define TSADCV2_AUTO_PERIOD_HT 0x6c
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#define TSADCV3_AUTO_PERIOD 0x154
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#define TSADCV3_AUTO_PERIOD_HT 0x158
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#define TSADCV3_Q_MAX 0x210
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#define TSADCV2_AUTO_EN BIT(0)
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#define TSADCV2_AUTO_EN_MASK BIT(16)
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#define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn))
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#define TSADCV3_AUTO_SRC_EN(chn) BIT(chn)
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#define TSADCV3_AUTO_SRC_EN_MASK(chn) BIT(16 + (chn))
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#define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8)
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#define TSADCV2_AUTO_TSHUT_POLARITY_MASK BIT(24)
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#define TSADCV3_AUTO_Q_SEL_EN BIT(1)
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#define TSADCV3_AUTO_Q_SEL_EN_MASK BIT(17)
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#define TSADCV2_INT_SRC_EN(chn) BIT(chn)
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#define TSADCV2_INT_SRC_EN_MASK(chn) BIT(16 + (chn))
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#define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn))
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#define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn))
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#define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8)
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#define TSADCV3_INT_PD_CLEAR_MASK ~BIT(16)
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#define TSADCV4_INT_PD_CLEAR_MASK 0xffffffff
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#define TSADCV2_DATA_MASK 0xfff
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#define TSADCV3_DATA_MASK 0x3ff
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#define TSADCV4_DATA_MASK 0x1ff
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#define TSADCV5_DATA_MASK 0x7ff
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#define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4
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#define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4
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#define TSADCV2_AUTO_PERIOD_TIME 250
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#define TSADCV2_AUTO_PERIOD_HT_TIME 50
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#define TSADCV3_AUTO_PERIOD_TIME 1875
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#define TSADCV3_AUTO_PERIOD_HT_TIME 1875
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#define TSADCV5_AUTO_PERIOD_TIME 1622 /* 2.5ms */
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#define TSADCV5_AUTO_PERIOD_HT_TIME 1622 /* 2.5ms */
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#define TSADCV6_AUTO_PERIOD_TIME 5000 /* 2.5ms */
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#define TSADCV6_AUTO_PERIOD_HT_TIME 5000 /* 2.5ms */
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#define TSADCV7_AUTO_PERIOD_TIME 3000 /* 2.5ms */
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#define TSADCV7_AUTO_PERIOD_HT_TIME 3000 /* 2.5ms */
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#define TSADCV3_Q_MAX_VAL 0x7ff /* 11bit 2047 */
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#define TSADCV12_AUTO_PERIOD_TIME 3000 /* 2.5ms */
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#define TSADCV12_AUTO_PERIOD_HT_TIME 3000 /* 2.5ms */
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#define TSADCV12_Q_MAX_VAL 0xfff /* 12bit 4095 */
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#define TSADCV9_Q_MAX 0x210
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#define TSADCV9_Q_MAX_VAL (0xffff0400 << 0)
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#define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */
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#define TSADCV5_USER_INTER_PD_SOC 0xfc0 /* 97us, at least 90us */
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#define GRF_SARADC_TESTBIT 0x0e644
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#define GRF_TSADC_TESTBIT_L 0x0e648
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#define GRF_TSADC_TESTBIT_H 0x0e64c
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#define PX30_GRF_SOC_CON0 0x0400
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#define PX30_GRF_SOC_CON2 0x0408
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#define RK3562_GRF_TSADC_CON 0x0580
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#define RK3568_GRF_TSADC_CON 0x0600
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#define RK3528_GRF_TSADC_CON 0x40030
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#define RK3568_GRF_TSADC_ANA_REG0 (0x10001 << 0)
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#define RK3568_GRF_TSADC_ANA_REG1 (0x10001 << 1)
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#define RK3568_GRF_TSADC_ANA_REG2 (0x10001 << 2)
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#define RK3568_GRF_TSADC_TSEN (0x10001 << 8)
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#define GRF_SARADC_TESTBIT_ON (0x10001 << 2)
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#define GRF_TSADC_TESTBIT_H_ON (0x10001 << 2)
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#define GRF_TSADC_VCM_EN_L (0x10001 << 7)
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#define GRF_TSADC_VCM_EN_H (0x10001 << 7)
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#define GRF_CON_TSADC_CH_INV (0x10001 << 1)
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#define PX30S_TSADC_TDC_MODE (0x10001 << 4)
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/* -40 to 125 is reliable, outside the range existed unreliability */
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#define MIN_TEMP (-60000)
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#define LOWEST_TEMP (-273000)
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#define MAX_TEMP (180000)
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#define MAX_ENV_TEMP (85000)
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#define BASE (1024)
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#define BASE_SHIFT (10)
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#define START_DEBOUNCE_COUNT (100)
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#define HIGHER_DEBOUNCE_TEMP (30000)
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#define LOWER_DEBOUNCE_TEMP (15000)
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/**
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* struct tsadc_table - hold information about code and temp mapping
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* @code: raw code from tsadc ip
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* @temp: the mapping temperature
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*/
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struct tsadc_table {
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unsigned long code;
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int temp;
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};
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struct chip_tsadc_table {
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const struct tsadc_table *id;
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unsigned int length;
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u32 data_mask;
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/* Tsadc is linear, using linear parameters */
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int knum;
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int bnum;
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enum adc_sort_mode mode;
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};
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enum sensor_id {
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SENSOR_CPU = 0,
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SENSOR_GPU,
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};
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struct rockchip_tsadc_chip {
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/* The sensor id of chip correspond to the ADC channel */
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int chn_id[SOC_MAX_SENSORS];
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int chn_num;
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fdt_addr_t base;
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fdt_addr_t grf;
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/* The hardware-controlled tshut property */
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int tshut_temp;
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enum tshut_mode tshut_mode;
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enum tshut_polarity tshut_polarity;
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void (*tsadc_control)(struct udevice *dev, bool enable);
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void (*tsadc_init)(struct udevice *dev);
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int (*tsadc_get_temp)(struct udevice *dev, int chn,
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int *temp);
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void (*irq_ack)(struct udevice *dev);
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void (*set_alarm_temp)(struct udevice *dev,
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int chn, int temp);
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void (*set_tshut_temp)(struct udevice *dev,
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int chn, int temp);
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void (*set_tshut_mode)(struct udevice *dev, int chn, enum tshut_mode m);
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struct chip_tsadc_table table;
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};
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struct rockchip_thermal_priv {
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void *base;
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void *grf;
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enum tshut_mode tshut_mode;
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enum tshut_polarity tshut_polarity;
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const struct rockchip_tsadc_chip *data;
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};
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static const struct tsadc_table rk1808_code_table[] = {
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{0, MIN_TEMP},
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{3423, MIN_TEMP},
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{3455, -40000},
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{3463, -35000},
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{3471, -30000},
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{3479, -25000},
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{3487, -20000},
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{3495, -15000},
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{3503, -10000},
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{3511, -5000},
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{3519, 0},
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{3527, 5000},
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{3535, 10000},
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{3543, 15000},
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{3551, 20000},
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{3559, 25000},
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{3567, 30000},
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{3576, 35000},
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{3584, 40000},
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{3592, 45000},
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{3600, 50000},
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{3609, 55000},
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{3617, 60000},
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{3625, 65000},
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{3633, 70000},
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{3642, 75000},
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{3650, 80000},
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{3659, 85000},
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{3667, 90000},
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{3675, 95000},
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{3684, 100000},
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{3692, 105000},
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{3701, 110000},
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{3709, 115000},
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{3718, 120000},
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{3726, 125000},
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{3820, MAX_TEMP},
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{TSADCV2_DATA_MASK, MAX_TEMP},
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};
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static const struct tsadc_table rk3228_code_table[] = {
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{0, MIN_TEMP},
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{568, MIN_TEMP},
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{588, -40000},
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{593, -35000},
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{598, -30000},
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{603, -25000},
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{608, -20000},
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{613, -15000},
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{618, -10000},
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{623, -5000},
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{629, 0},
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{634, 5000},
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{639, 10000},
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{644, 15000},
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{649, 20000},
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{654, 25000},
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{660, 30000},
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{665, 35000},
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{670, 40000},
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{675, 45000},
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{681, 50000},
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{686, 55000},
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{691, 60000},
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{696, 65000},
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{702, 70000},
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{707, 75000},
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{712, 80000},
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{717, 85000},
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{723, 90000},
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{728, 95000},
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{733, 100000},
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{738, 105000},
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{744, 110000},
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{749, 115000},
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{754, 120000},
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{760, 125000},
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{821, MAX_TEMP},
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{TSADCV2_DATA_MASK, MAX_TEMP},
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};
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static const struct tsadc_table rk3288_code_table[] = {
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{TSADCV2_DATA_MASK, MIN_TEMP},
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{3833, MIN_TEMP},
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{3800, -40000},
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{3792, -35000},
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{3783, -30000},
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{3774, -25000},
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{3765, -20000},
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{3756, -15000},
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{3747, -10000},
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{3737, -5000},
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{3728, 0},
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{3718, 5000},
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{3708, 10000},
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{3698, 15000},
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{3688, 20000},
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{3678, 25000},
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{3667, 30000},
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{3656, 35000},
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{3645, 40000},
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{3634, 45000},
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{3623, 50000},
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{3611, 55000},
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{3600, 60000},
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{3588, 65000},
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{3575, 70000},
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{3563, 75000},
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{3550, 80000},
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{3537, 85000},
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{3524, 90000},
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{3510, 95000},
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{3496, 100000},
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{3482, 105000},
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{3467, 110000},
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{3452, 115000},
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{3437, 120000},
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{3421, 125000},
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{3350, 145000},
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{3270, 165000},
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{3195, MAX_TEMP},
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{0, MAX_TEMP},
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};
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static const struct tsadc_table rk3328_code_table[] = {
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{0, MIN_TEMP},
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{261, MIN_TEMP},
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{296, -40000},
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{304, -35000},
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{313, -30000},
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{331, -20000},
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{340, -15000},
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{349, -10000},
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{359, -5000},
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{368, 0},
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{378, 5000},
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{388, 10000},
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{398, 15000},
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{408, 20000},
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{418, 25000},
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{429, 30000},
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{440, 35000},
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{451, 40000},
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{462, 45000},
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{473, 50000},
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{485, 55000},
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{496, 60000},
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{508, 65000},
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{521, 70000},
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{533, 75000},
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{546, 80000},
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{559, 85000},
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{572, 90000},
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{586, 95000},
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{600, 100000},
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{614, 105000},
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{629, 110000},
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{644, 115000},
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{659, 120000},
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{675, 125000},
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{745, 145000},
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{825, 165000},
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{900, MAX_TEMP},
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{TSADCV2_DATA_MASK, MAX_TEMP},
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};
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static const struct tsadc_table rk3368_code_table[] = {
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{0, MIN_TEMP},
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{98, MIN_TEMP},
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{106, -40000},
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{108, -35000},
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{110, -30000},
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{112, -25000},
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{114, -20000},
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{116, -15000},
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{118, -10000},
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{120, -5000},
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{122, 0},
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{124, 5000},
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{126, 10000},
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{128, 15000},
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{130, 20000},
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{132, 25000},
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{134, 30000},
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{136, 35000},
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{138, 40000},
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{140, 45000},
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{142, 50000},
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{144, 55000},
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{146, 60000},
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{148, 65000},
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{150, 70000},
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{152, 75000},
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{154, 80000},
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{156, 85000},
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{158, 90000},
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{160, 95000},
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{162, 100000},
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{163, 105000},
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{165, 110000},
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{167, 115000},
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{169, 120000},
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{171, 125000},
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{193, MAX_TEMP},
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{TSADCV3_DATA_MASK, MAX_TEMP},
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};
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static const struct tsadc_table rk3399_code_table[] = {
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{0, MIN_TEMP},
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{368, MIN_TEMP},
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{402, -40000},
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{410, -35000},
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{419, -30000},
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{427, -25000},
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{436, -20000},
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{444, -15000},
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{453, -10000},
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{461, -5000},
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{470, 0},
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{478, 5000},
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{487, 10000},
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{496, 15000},
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{504, 20000},
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{513, 25000},
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{521, 30000},
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{530, 35000},
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{538, 40000},
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{547, 45000},
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{555, 50000},
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{564, 55000},
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{573, 60000},
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{581, 65000},
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{590, 70000},
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{599, 75000},
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{607, 80000},
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{616, 85000},
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{624, 90000},
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{633, 95000},
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{642, 100000},
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{650, 105000},
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{659, 110000},
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{668, 115000},
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{677, 120000},
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{685, 125000},
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{782, MAX_TEMP},
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{TSADCV3_DATA_MASK, MAX_TEMP},
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};
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static const struct tsadc_table rk3528_code_table[] = {
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{0, MIN_TEMP},
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{1386, MIN_TEMP},
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{1419, -40000},
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{1427, -35000},
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{1435, -30000},
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{1443, -25000},
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{1452, -20000},
|
|
{1460, -15000},
|
|
{1468, -10000},
|
|
{1477, -5000},
|
|
{1486, 0},
|
|
{1494, 5000},
|
|
{1502, 10000},
|
|
{1510, 15000},
|
|
{1519, 20000},
|
|
{1527, 25000},
|
|
{1535, 30000},
|
|
{1544, 35000},
|
|
{1552, 40000},
|
|
{1561, 45000},
|
|
{1569, 50000},
|
|
{1578, 55000},
|
|
{1586, 60000},
|
|
{1594, 65000},
|
|
{1603, 70000},
|
|
{1612, 75000},
|
|
{1620, 80000},
|
|
{1628, 85000},
|
|
{1637, 90000},
|
|
{1646, 95000},
|
|
{1654, 100000},
|
|
{1662, 105000},
|
|
{1671, 110000},
|
|
{1679, 115000},
|
|
{1688, 120000},
|
|
{1696, 125000},
|
|
{1790, MAX_TEMP},
|
|
{TSADCV5_DATA_MASK, MAX_TEMP},
|
|
};
|
|
|
|
static const struct tsadc_table rk3562_code_table[] = {
|
|
{0, MIN_TEMP},
|
|
{1385, MIN_TEMP},
|
|
{1419, -40000},
|
|
{1428, -35000},
|
|
{1436, -30000},
|
|
{1445, -25000},
|
|
{1453, -20000},
|
|
{1462, -15000},
|
|
{1470, -10000},
|
|
{1479, -5000},
|
|
{1487, 0},
|
|
{1496, 5000},
|
|
{1504, 10000},
|
|
{1512, 15000},
|
|
{1521, 20000},
|
|
{1529, 25000},
|
|
{1538, 30000},
|
|
{1546, 35000},
|
|
{1555, 40000},
|
|
{1563, 45000},
|
|
{1572, 50000},
|
|
{1580, 55000},
|
|
{1589, 60000},
|
|
{1598, 65000},
|
|
{1606, 70000},
|
|
{1615, 75000},
|
|
{1623, 80000},
|
|
{1632, 85000},
|
|
{1640, 90000},
|
|
{1648, 95000},
|
|
{1657, 100000},
|
|
{1666, 105000},
|
|
{1674, 110000},
|
|
{1682, 115000},
|
|
{1691, 120000},
|
|
{1699, 125000},
|
|
{1793, MAX_TEMP},
|
|
{TSADCV2_DATA_MASK, MAX_TEMP},
|
|
};
|
|
|
|
static const struct tsadc_table rk3568_code_table[] = {
|
|
{0, MIN_TEMP},
|
|
{1448, MIN_TEMP},
|
|
{1584, -40000},
|
|
{1620, -35000},
|
|
{1652, -30000},
|
|
{1688, -25000},
|
|
{1720, -20000},
|
|
{1756, -15000},
|
|
{1788, -10000},
|
|
{1824, -5000},
|
|
{1856, 0},
|
|
{1892, 5000},
|
|
{1924, 10000},
|
|
{1956, 15000},
|
|
{1992, 20000},
|
|
{2024, 25000},
|
|
{2060, 30000},
|
|
{2092, 35000},
|
|
{2128, 40000},
|
|
{2160, 45000},
|
|
{2196, 50000},
|
|
{2228, 55000},
|
|
{2264, 60000},
|
|
{2300, 65000},
|
|
{2332, 70000},
|
|
{2368, 75000},
|
|
{2400, 80000},
|
|
{2436, 85000},
|
|
{2468, 90000},
|
|
{2500, 95000},
|
|
{2536, 100000},
|
|
{2572, 105000},
|
|
{2604, 110000},
|
|
{2636, 115000},
|
|
{2672, 120000},
|
|
{2704, 125000},
|
|
{3076, MAX_TEMP},
|
|
{TSADCV2_DATA_MASK, MAX_TEMP},
|
|
};
|
|
|
|
static const struct tsadc_table rk3588_code_table[] = {
|
|
{0, MIN_TEMP},
|
|
{194, MIN_TEMP},
|
|
{215, -40000},
|
|
{285, 25000},
|
|
{350, 85000},
|
|
{395, 125000},
|
|
{455, MAX_TEMP},
|
|
{TSADCV4_DATA_MASK, MAX_TEMP},
|
|
};
|
|
|
|
/*
|
|
* Struct used for matching a device
|
|
*/
|
|
struct of_device_id {
|
|
char compatible[32];
|
|
const void *data;
|
|
};
|
|
|
|
static int tsadc_code_to_temp(struct chip_tsadc_table *table, u32 code,
|
|
int *temp)
|
|
{
|
|
unsigned int low = 1;
|
|
unsigned int high = table->length - 1;
|
|
unsigned int mid = (low + high) / 2;
|
|
unsigned int num;
|
|
unsigned long denom;
|
|
|
|
if (table->knum) {
|
|
*temp = (((int)code - table->bnum) * 10000 / table->knum) * 100;
|
|
if (*temp < MIN_TEMP || *temp > MAX_TEMP)
|
|
return -EAGAIN;
|
|
return 0;
|
|
}
|
|
|
|
switch (table->mode) {
|
|
case ADC_DECREMENT:
|
|
code &= table->data_mask;
|
|
if (code < table->id[high].code)
|
|
return -EAGAIN; /* Incorrect reading */
|
|
|
|
while (low <= high) {
|
|
if (code >= table->id[mid].code &&
|
|
code < table->id[mid - 1].code)
|
|
break;
|
|
else if (code < table->id[mid].code)
|
|
low = mid + 1;
|
|
else
|
|
high = mid - 1;
|
|
|
|
mid = (low + high) / 2;
|
|
}
|
|
break;
|
|
case ADC_INCREMENT:
|
|
code &= table->data_mask;
|
|
if (code < table->id[low].code)
|
|
return -EAGAIN; /* Incorrect reading */
|
|
|
|
while (low <= high) {
|
|
if (code <= table->id[mid].code &&
|
|
code > table->id[mid - 1].code)
|
|
break;
|
|
else if (code > table->id[mid].code)
|
|
low = mid + 1;
|
|
else
|
|
high = mid - 1;
|
|
|
|
mid = (low + high) / 2;
|
|
}
|
|
break;
|
|
default:
|
|
printf("%s: Invalid the conversion table mode=%d\n",
|
|
__func__, table->mode);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/*
|
|
* The 5C granularity provided by the table is too much. Let's
|
|
* assume that the relationship between sensor readings and
|
|
* temperature between 2 table entries is linear and interpolate
|
|
* to produce less granular result.
|
|
*/
|
|
num = table->id[mid].temp - table->id[mid - 1].temp;
|
|
num *= abs(table->id[mid - 1].code - code);
|
|
denom = abs(table->id[mid - 1].code - table->id[mid].code);
|
|
*temp = table->id[mid - 1].temp + (num / denom);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static u32 tsadc_temp_to_code_v2(struct chip_tsadc_table table,
|
|
int temp)
|
|
{
|
|
int high, low, mid;
|
|
unsigned long num;
|
|
unsigned int denom;
|
|
u32 error = table.data_mask;
|
|
|
|
if (table.knum)
|
|
return (((temp / 1000) * table.knum) / 1000 + table.bnum);
|
|
|
|
low = 0;
|
|
high = table.length - 1;
|
|
mid = (high + low) / 2;
|
|
|
|
/* Return mask code data when the temp is over table range */
|
|
if (temp < table.id[low].temp || temp > table.id[high].temp)
|
|
goto exit;
|
|
|
|
while (low <= high) {
|
|
if (temp == table.id[mid].temp)
|
|
return table.id[mid].code;
|
|
else if (temp < table.id[mid].temp)
|
|
high = mid - 1;
|
|
else
|
|
low = mid + 1;
|
|
mid = (low + high) / 2;
|
|
}
|
|
|
|
num = abs(table.id[mid + 1].code - table.id[mid].code);
|
|
num *= temp - table.id[mid].temp;
|
|
denom = table.id[mid + 1].temp - table.id[mid].temp;
|
|
|
|
switch (table.mode) {
|
|
case ADC_DECREMENT:
|
|
return table.id[mid].code - (num / denom);
|
|
case ADC_INCREMENT:
|
|
return table.id[mid].code + (num / denom);
|
|
default:
|
|
pr_err("%s: unknown table mode: %d\n", __func__, table.mode);
|
|
return error;
|
|
}
|
|
|
|
exit:
|
|
pr_err("%s: Invalid conversion table: code=%d, temperature=%d\n",
|
|
__func__, error, temp);
|
|
|
|
return error;
|
|
}
|
|
|
|
static void tsadc_irq_ack_v2(struct udevice *dev)
|
|
{
|
|
struct rockchip_thermal_priv *priv = dev_get_priv(dev);
|
|
u32 val;
|
|
|
|
val = readl(priv->base + TSADCV2_INT_PD);
|
|
writel(val & TSADCV2_INT_PD_CLEAR_MASK, priv->base + TSADCV2_INT_PD);
|
|
}
|
|
|
|
static void tsadc_irq_ack_v3(struct udevice *dev)
|
|
{
|
|
struct rockchip_thermal_priv *priv = dev_get_priv(dev);
|
|
u32 val;
|
|
|
|
val = readl(priv->base + TSADCV2_INT_PD);
|
|
writel(val & TSADCV3_INT_PD_CLEAR_MASK, priv->base + TSADCV2_INT_PD);
|
|
}
|
|
|
|
static void tsadc_irq_ack_v4(struct udevice *dev)
|
|
{
|
|
struct rockchip_thermal_priv *priv = dev_get_priv(dev);
|
|
u32 val;
|
|
|
|
val = readl(priv->base + TSADCV3_INT_PD);
|
|
writel(val & TSADCV4_INT_PD_CLEAR_MASK, priv->base + TSADCV3_INT_PD);
|
|
val = readl(priv->base + TSADCV3_HSHUT_PD);
|
|
writel(val & TSADCV3_INT_PD_CLEAR_MASK, priv->base + TSADCV3_HSHUT_PD);
|
|
}
|
|
|
|
static void tsadc_control_v2(struct udevice *dev, bool enable)
|
|
{
|
|
struct rockchip_thermal_priv *priv = dev_get_priv(dev);
|
|
u32 val;
|
|
|
|
val = readl(priv->base + TSADCV2_AUTO_CON);
|
|
if (enable)
|
|
val |= TSADCV2_AUTO_EN;
|
|
else
|
|
val &= ~TSADCV2_AUTO_EN;
|
|
|
|
writel(val, priv->base + TSADCV2_AUTO_CON);
|
|
}
|
|
|
|
static void tsadc_control_v3(struct udevice *dev, bool enable)
|
|
{
|
|
struct rockchip_thermal_priv *priv = dev_get_priv(dev);
|
|
u32 val;
|
|
|
|
val = readl(priv->base + TSADCV2_AUTO_CON);
|
|
if (enable)
|
|
val |= TSADCV2_AUTO_EN | TSADCV3_AUTO_Q_SEL_EN;
|
|
else
|
|
val &= ~TSADCV2_AUTO_EN;
|
|
|
|
writel(val, priv->base + TSADCV2_AUTO_CON);
|
|
}
|
|
|
|
static void tsadc_control_v4(struct udevice *dev, bool enable)
|
|
{
|
|
struct rockchip_thermal_priv *priv = dev_get_priv(dev);
|
|
u32 val;
|
|
|
|
if (enable)
|
|
val = TSADCV2_AUTO_EN | TSADCV2_AUTO_EN_MASK;
|
|
else
|
|
val = TSADCV2_AUTO_EN_MASK;
|
|
|
|
writel(val, priv->base + TSADCV2_AUTO_CON);
|
|
}
|
|
|
|
static void tsadc_init_v2(struct udevice *dev)
|
|
{
|
|
struct rockchip_thermal_priv *priv = dev_get_priv(dev);
|
|
|
|
writel(TSADCV2_AUTO_PERIOD_TIME,
|
|
priv->base + TSADCV2_AUTO_PERIOD);
|
|
writel(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
|
|
priv->base + TSADCV2_HIGHT_INT_DEBOUNCE);
|
|
writel(TSADCV2_AUTO_PERIOD_HT_TIME,
|
|
priv->base + TSADCV2_AUTO_PERIOD_HT);
|
|
writel(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
|
|
priv->base + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
|
|
|
|
if (priv->tshut_polarity == TSHUT_HIGH_ACTIVE)
|
|
writel(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
|
|
priv->base + TSADCV2_AUTO_CON);
|
|
else
|
|
writel(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
|
|
priv->base + TSADCV2_AUTO_CON);
|
|
}
|
|
|
|
static void tsadc_init_v3(struct udevice *dev)
|
|
{
|
|
struct rockchip_thermal_priv *priv = dev_get_priv(dev);
|
|
|
|
if (!IS_ERR(priv->grf)) {
|
|
writel(GRF_TSADC_VCM_EN_L, priv->grf + GRF_TSADC_TESTBIT_L);
|
|
writel(GRF_TSADC_VCM_EN_H, priv->grf + GRF_TSADC_TESTBIT_H);
|
|
|
|
udelay(100);/* The spec note says at least 15 us */
|
|
writel(GRF_SARADC_TESTBIT_ON, priv->grf + GRF_SARADC_TESTBIT);
|
|
writel(GRF_TSADC_TESTBIT_H_ON, priv->grf + GRF_TSADC_TESTBIT_H);
|
|
udelay(200);/* The spec note says at least 90 us */
|
|
}
|
|
tsadc_init_v2(dev);
|
|
}
|
|
|
|
static void __maybe_unused tsadc_init_v5(struct udevice *dev)
|
|
{
|
|
struct rockchip_thermal_priv *priv = dev_get_priv(dev);
|
|
|
|
/* Set interleave value to workround ic time sync issue */
|
|
writel(TSADCV2_USER_INTER_PD_SOC, priv->base +
|
|
TSADCV2_USER_CON);
|
|
tsadc_init_v2(dev);
|
|
}
|
|
|
|
static void tsadc_init_v4(struct udevice *dev)
|
|
{
|
|
struct rockchip_thermal_priv *priv = dev_get_priv(dev);
|
|
|
|
tsadc_init_v2(dev);
|
|
if (!IS_ERR(priv->grf))
|
|
writel(GRF_CON_TSADC_CH_INV, priv->grf + PX30_GRF_SOC_CON2);
|
|
}
|
|
|
|
static void tsadc_init_v7(struct udevice *dev)
|
|
{
|
|
struct rockchip_thermal_priv *priv = dev_get_priv(dev);
|
|
|
|
writel(TSADCV5_USER_INTER_PD_SOC,
|
|
priv->base + TSADCV2_USER_CON);
|
|
writel(TSADCV5_AUTO_PERIOD_TIME,
|
|
priv->base + TSADCV2_AUTO_PERIOD);
|
|
writel(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
|
|
priv->base + TSADCV2_HIGHT_INT_DEBOUNCE);
|
|
writel(TSADCV5_AUTO_PERIOD_HT_TIME,
|
|
priv->base + TSADCV2_AUTO_PERIOD_HT);
|
|
writel(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
|
|
priv->base + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
|
|
|
|
if (priv->tshut_polarity == TSHUT_HIGH_ACTIVE)
|
|
writel(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
|
|
priv->base + TSADCV2_AUTO_CON);
|
|
else
|
|
writel(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
|
|
priv->base + TSADCV2_AUTO_CON);
|
|
|
|
if (!IS_ERR(priv->grf)) {
|
|
writel(RK3568_GRF_TSADC_TSEN,
|
|
priv->grf + RK3568_GRF_TSADC_CON);
|
|
udelay(15);
|
|
writel(RK3568_GRF_TSADC_ANA_REG0,
|
|
priv->grf + RK3568_GRF_TSADC_CON);
|
|
writel(RK3568_GRF_TSADC_ANA_REG1,
|
|
priv->grf + RK3568_GRF_TSADC_CON);
|
|
writel(RK3568_GRF_TSADC_ANA_REG2,
|
|
priv->grf + RK3568_GRF_TSADC_CON);
|
|
udelay(200);
|
|
}
|
|
}
|
|
|
|
static void tsadc_init_v8(struct udevice *dev)
|
|
{
|
|
struct rockchip_thermal_priv *priv = dev_get_priv(dev);
|
|
|
|
writel(TSADCV6_AUTO_PERIOD_TIME, priv->base + TSADCV3_AUTO_PERIOD);
|
|
writel(TSADCV6_AUTO_PERIOD_HT_TIME,
|
|
priv->base + TSADCV3_AUTO_PERIOD_HT);
|
|
writel(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
|
|
priv->base + TSADCV3_HIGHT_INT_DEBOUNCE);
|
|
writel(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
|
|
priv->base + TSADCV3_HIGHT_TSHUT_DEBOUNCE);
|
|
|
|
if (priv->tshut_polarity == TSHUT_HIGH_ACTIVE)
|
|
writel(TSADCV2_AUTO_TSHUT_POLARITY_HIGH |
|
|
TSADCV2_AUTO_TSHUT_POLARITY_MASK,
|
|
priv->base + TSADCV2_AUTO_CON);
|
|
else
|
|
writel(TSADCV2_AUTO_TSHUT_POLARITY_MASK,
|
|
priv->base + TSADCV2_AUTO_CON);
|
|
};
|
|
|
|
static void tsadc_init_v9(struct udevice *dev)
|
|
{
|
|
struct rockchip_thermal_priv *priv = dev_get_priv(dev);
|
|
|
|
tsadc_init_v2(dev);
|
|
if (!IS_ERR(priv->grf))
|
|
writel(PX30S_TSADC_TDC_MODE, priv->grf + PX30_GRF_SOC_CON0);
|
|
}
|
|
|
|
static void tsadc_init_v11(struct udevice *dev)
|
|
{
|
|
struct rockchip_thermal_priv *priv = dev_get_priv(dev);
|
|
|
|
writel(TSADCV7_AUTO_PERIOD_TIME, priv->base + TSADCV3_AUTO_PERIOD);
|
|
writel(TSADCV7_AUTO_PERIOD_HT_TIME,
|
|
priv->base + TSADCV3_AUTO_PERIOD_HT);
|
|
writel(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
|
|
priv->base + TSADCV3_HIGHT_INT_DEBOUNCE);
|
|
writel(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
|
|
priv->base + TSADCV3_HIGHT_TSHUT_DEBOUNCE);
|
|
writel(TSADCV3_Q_MAX_VAL, priv->base + TSADCV3_Q_MAX);
|
|
writel(TSADCV3_AUTO_Q_SEL_EN | TSADCV3_AUTO_Q_SEL_EN_MASK,
|
|
priv->base + TSADCV2_AUTO_CON);
|
|
|
|
if (priv->tshut_polarity == TSHUT_HIGH_ACTIVE)
|
|
writel(TSADCV2_AUTO_TSHUT_POLARITY_HIGH |
|
|
TSADCV2_AUTO_TSHUT_POLARITY_MASK,
|
|
priv->base + TSADCV2_AUTO_CON);
|
|
else
|
|
writel(TSADCV2_AUTO_TSHUT_POLARITY_MASK,
|
|
priv->base + TSADCV2_AUTO_CON);
|
|
|
|
if (!IS_ERR(priv->grf)) {
|
|
writel(RK3568_GRF_TSADC_TSEN,
|
|
priv->grf + RK3528_GRF_TSADC_CON);
|
|
udelay(15);
|
|
writel(RK3568_GRF_TSADC_ANA_REG0,
|
|
priv->grf + RK3528_GRF_TSADC_CON);
|
|
writel(RK3568_GRF_TSADC_ANA_REG1,
|
|
priv->grf + RK3528_GRF_TSADC_CON);
|
|
writel(RK3568_GRF_TSADC_ANA_REG2,
|
|
priv->grf + RK3528_GRF_TSADC_CON);
|
|
udelay(200);
|
|
}
|
|
}
|
|
|
|
static void tsadc_init_v12(struct udevice *dev)
|
|
{
|
|
struct rockchip_thermal_priv *priv = dev_get_priv(dev);
|
|
|
|
writel(TSADCV12_AUTO_PERIOD_TIME,
|
|
priv->base + TSADCV3_AUTO_PERIOD);
|
|
writel(TSADCV12_AUTO_PERIOD_HT_TIME,
|
|
priv->base + TSADCV3_AUTO_PERIOD_HT);
|
|
writel(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
|
|
priv->base + TSADCV3_HIGHT_INT_DEBOUNCE);
|
|
writel(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
|
|
priv->base + TSADCV3_HIGHT_TSHUT_DEBOUNCE);
|
|
writel(TSADCV12_Q_MAX_VAL,
|
|
priv->base + TSADCV9_Q_MAX);
|
|
writel(TSADCV3_AUTO_Q_SEL_EN | TSADCV3_AUTO_Q_SEL_EN_MASK,
|
|
priv->base + TSADCV2_AUTO_CON);
|
|
if (priv->tshut_polarity == TSHUT_HIGH_ACTIVE)
|
|
writel(TSADCV2_AUTO_TSHUT_POLARITY_HIGH |
|
|
TSADCV2_AUTO_TSHUT_POLARITY_MASK,
|
|
priv->base + TSADCV2_AUTO_CON);
|
|
else
|
|
writel(TSADCV2_AUTO_TSHUT_POLARITY_MASK,
|
|
priv->base + TSADCV2_AUTO_CON);
|
|
|
|
if (!IS_ERR(priv->grf)) {
|
|
writel(RK3568_GRF_TSADC_TSEN,
|
|
priv->grf + RK3562_GRF_TSADC_CON);
|
|
udelay(15);
|
|
writel(RK3568_GRF_TSADC_ANA_REG0,
|
|
priv->grf + RK3562_GRF_TSADC_CON);
|
|
writel(RK3568_GRF_TSADC_ANA_REG1,
|
|
priv->grf + RK3562_GRF_TSADC_CON);
|
|
writel(RK3568_GRF_TSADC_ANA_REG2,
|
|
priv->grf + RK3562_GRF_TSADC_CON);
|
|
udelay(200);
|
|
}
|
|
}
|
|
|
|
static int tsadc_get_temp_v2(struct udevice *dev,
|
|
int chn, int *temp)
|
|
{
|
|
struct rockchip_thermal_priv *priv = dev_get_priv(dev);
|
|
struct chip_tsadc_table table = priv->data->table;
|
|
u32 val;
|
|
|
|
val = readl(priv->base + TSADCV2_DATA(chn));
|
|
|
|
return tsadc_code_to_temp(&table, val, temp);
|
|
}
|
|
|
|
static int predict_temp(int temp)
|
|
{
|
|
/*
|
|
* The deviation of prediction. the temperature will not change rapidly,
|
|
* so this cov_q is small
|
|
*/
|
|
int cov_q = 18;
|
|
/*
|
|
* The deviation of tsadc's reading, deviation of tsadc is very big when
|
|
* abnormal temperature is get
|
|
*/
|
|
int cov_r = 542;
|
|
|
|
int gain;
|
|
int temp_mid;
|
|
int temp_now;
|
|
int prob_mid;
|
|
int prob_now;
|
|
static int temp_last = LOWEST_TEMP;
|
|
static int prob_last = 160;
|
|
static int bounding_cnt;
|
|
|
|
/*
|
|
* init temp_last with a more suitable value, which mostly equals to
|
|
* temp reading from tsadc, but not higher than MAX_ENV_TEMP. If the
|
|
* temp is higher than MAX_ENV_TEMP, it is assumed to be abnormal
|
|
* value and temp_last is adjusted to MAX_ENV_TEMP.
|
|
*/
|
|
if (temp_last == LOWEST_TEMP)
|
|
temp_last = min(temp, MAX_ENV_TEMP);
|
|
|
|
/*
|
|
* Before START_DEBOUNCE_COUNT's samples of temperature, we consider
|
|
* tsadc is stable, i.e. after that, the temperature may be not stable
|
|
* and may have abnormal reading, so we set a bounding temperature. If
|
|
* the reading from tsadc is too big, we set the delta temperature of
|
|
* DEBOUNCE_TEMP/3 comparing to the last temperature.
|
|
*/
|
|
|
|
if (bounding_cnt++ > START_DEBOUNCE_COUNT) {
|
|
bounding_cnt = START_DEBOUNCE_COUNT;
|
|
if (temp - temp_last > HIGHER_DEBOUNCE_TEMP)
|
|
temp = temp_last + HIGHER_DEBOUNCE_TEMP / 3;
|
|
if (temp_last - temp > LOWER_DEBOUNCE_TEMP)
|
|
temp = temp_last - LOWER_DEBOUNCE_TEMP / 3;
|
|
}
|
|
|
|
temp_mid = temp_last;
|
|
|
|
/* calculate the probability of this time's prediction */
|
|
prob_mid = prob_last + cov_q;
|
|
|
|
/* calculate the Kalman Gain */
|
|
gain = (prob_mid * BASE) / (prob_mid + cov_r);
|
|
|
|
/* calculate the prediction of temperature */
|
|
temp_now = (temp_mid * BASE + gain * (temp - temp_mid)) >> BASE_SHIFT;
|
|
|
|
/*
|
|
* Base on this time's Kalman Gain, ajust our probability of prediction
|
|
* for next time calculation
|
|
*/
|
|
prob_now = ((BASE - gain) * prob_mid) >> BASE_SHIFT;
|
|
|
|
prob_last = prob_now;
|
|
temp_last = temp_now;
|
|
|
|
return temp_last;
|
|
}
|
|
|
|
static int tsadc_get_temp_v3(struct udevice *dev,
|
|
int chn, int *temp)
|
|
{
|
|
int ret;
|
|
|
|
ret = tsadc_get_temp_v2(dev, chn, temp);
|
|
if (!ret)
|
|
*temp = predict_temp(*temp);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int tsadc_get_temp_v4(struct udevice *dev, int chn, int *temp)
|
|
{
|
|
struct rockchip_thermal_priv *priv = dev_get_priv(dev);
|
|
struct chip_tsadc_table table = priv->data->table;
|
|
u32 val;
|
|
|
|
val = readl(priv->base + TSADCV3_DATA(chn));
|
|
|
|
return tsadc_code_to_temp(&table, val, temp);
|
|
}
|
|
|
|
static void tsadc_alarm_temp_v2(struct udevice *dev,
|
|
int chn, int temp)
|
|
{
|
|
struct rockchip_thermal_priv *priv = dev_get_priv(dev);
|
|
struct chip_tsadc_table table = priv->data->table;
|
|
u32 alarm_value, int_en;
|
|
|
|
alarm_value = tsadc_temp_to_code_v2(table, temp);
|
|
if (alarm_value == table.data_mask)
|
|
return;
|
|
|
|
writel(alarm_value, priv->base + TSADCV2_COMP_INT(chn));
|
|
|
|
int_en = readl(priv->base + TSADCV2_INT_EN);
|
|
int_en |= TSADCV2_INT_SRC_EN(chn);
|
|
writel(int_en, priv->base + TSADCV2_INT_EN);
|
|
}
|
|
|
|
static void tsadc_alarm_temp_v3(struct udevice *dev, int chn, int temp)
|
|
{
|
|
struct rockchip_thermal_priv *priv = dev_get_priv(dev);
|
|
struct chip_tsadc_table table = priv->data->table;
|
|
u32 alarm_value;
|
|
|
|
alarm_value = tsadc_temp_to_code_v2(table, temp);
|
|
if (alarm_value == table.data_mask)
|
|
return;
|
|
|
|
writel(alarm_value, priv->base + TSADCV3_COMP_INT(chn));
|
|
writel(TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn),
|
|
priv->base + TSADCV3_HT_INT_EN);
|
|
}
|
|
|
|
static void tsadc_tshut_temp_v2(struct udevice *dev,
|
|
int chn, int temp)
|
|
{
|
|
struct rockchip_thermal_priv *priv = dev_get_priv(dev);
|
|
struct chip_tsadc_table table = priv->data->table;
|
|
u32 tshut_value, val;
|
|
|
|
tshut_value = tsadc_temp_to_code_v2(table, temp);
|
|
if (tshut_value == table.data_mask)
|
|
return;
|
|
|
|
writel(tshut_value, priv->base + TSADCV2_COMP_SHUT(chn));
|
|
|
|
/* TSHUT will be valid */
|
|
val = readl(priv->base + TSADCV2_AUTO_CON);
|
|
writel(val | TSADCV2_AUTO_SRC_EN(chn), priv->base + TSADCV2_AUTO_CON);
|
|
}
|
|
|
|
static void tsadc_tshut_temp_v3(struct udevice *dev, int chn, int temp)
|
|
{
|
|
struct rockchip_thermal_priv *priv = dev_get_priv(dev);
|
|
struct chip_tsadc_table table = priv->data->table;
|
|
u32 tshut_value;
|
|
|
|
tshut_value = tsadc_temp_to_code_v2(table, temp);
|
|
if (tshut_value == table.data_mask)
|
|
return;
|
|
|
|
writel(tshut_value, priv->base + TSADCV3_COMP_SHUT(chn));
|
|
writel(TSADCV3_AUTO_SRC_EN(chn) | TSADCV3_AUTO_SRC_EN_MASK(chn),
|
|
priv->base + TSADCV3_AUTO_SRC_CON);
|
|
}
|
|
|
|
static void tsadc_tshut_mode_v2(struct udevice *dev, int chn,
|
|
enum tshut_mode mode)
|
|
{
|
|
struct rockchip_thermal_priv *priv = dev_get_priv(dev);
|
|
u32 val;
|
|
|
|
val = readl(priv->base + TSADCV2_INT_EN);
|
|
if (mode == TSHUT_MODE_GPIO) {
|
|
val &= ~TSADCV2_SHUT_2CRU_SRC_EN(chn);
|
|
val |= TSADCV2_SHUT_2GPIO_SRC_EN(chn);
|
|
} else {
|
|
val &= ~TSADCV2_SHUT_2GPIO_SRC_EN(chn);
|
|
val |= TSADCV2_SHUT_2CRU_SRC_EN(chn);
|
|
}
|
|
|
|
writel(val, priv->base + TSADCV2_INT_EN);
|
|
}
|
|
|
|
static void tsadc_tshut_mode_v4(struct udevice *dev, int chn,
|
|
enum tshut_mode mode)
|
|
{
|
|
struct rockchip_thermal_priv *priv = dev_get_priv(dev);
|
|
u32 val_gpio, val_cru;
|
|
|
|
if (mode == TSHUT_MODE_GPIO) {
|
|
val_gpio = TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn);
|
|
val_cru = TSADCV2_INT_SRC_EN_MASK(chn);
|
|
} else {
|
|
val_cru = TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn);
|
|
val_gpio = TSADCV2_INT_SRC_EN_MASK(chn);
|
|
}
|
|
writel(val_gpio, priv->base + TSADCV3_HSHUT_GPIO_INT_EN);
|
|
writel(val_cru, priv->base + TSADCV3_HSHUT_CRU_INT_EN);
|
|
}
|
|
|
|
int rockchip_thermal_get_temp(struct udevice *dev, int *temp)
|
|
{
|
|
struct rockchip_thermal_priv *priv = dev_get_priv(dev);
|
|
|
|
priv->data->tsadc_get_temp(dev, 0, temp);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dm_thermal_ops rockchip_thermal_ops = {
|
|
.get_temp = rockchip_thermal_get_temp,
|
|
};
|
|
|
|
static const struct rockchip_tsadc_chip px30s_tsadc_data = {
|
|
.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
|
|
.chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
|
|
.chn_num = 2, /* 2 channels for tsadc */
|
|
|
|
.tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
|
|
.tshut_temp = 95000,
|
|
|
|
.tsadc_init = tsadc_init_v9,
|
|
.tsadc_control = tsadc_control_v2,
|
|
.tsadc_get_temp = tsadc_get_temp_v2,
|
|
.irq_ack = tsadc_irq_ack_v3,
|
|
.set_alarm_temp = tsadc_alarm_temp_v2,
|
|
.set_tshut_temp = tsadc_tshut_temp_v2,
|
|
.set_tshut_mode = tsadc_tshut_mode_v2,
|
|
|
|
.table = {
|
|
.knum = 2699,
|
|
.bnum = 2796,
|
|
.data_mask = TSADCV2_DATA_MASK,
|
|
.mode = ADC_INCREMENT,
|
|
},
|
|
};
|
|
|
|
static const struct rockchip_tsadc_chip rk3308bs_tsadc_data = {
|
|
.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
|
|
.chn_num = 1, /* 1 channels for tsadc */
|
|
|
|
.tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
|
|
.tshut_temp = 95000,
|
|
|
|
.tsadc_init = tsadc_init_v2,
|
|
.tsadc_control = tsadc_control_v2,
|
|
.tsadc_get_temp = tsadc_get_temp_v2,
|
|
.irq_ack = tsadc_irq_ack_v3,
|
|
.set_alarm_temp = tsadc_alarm_temp_v2,
|
|
.set_tshut_temp = tsadc_tshut_temp_v2,
|
|
.set_tshut_mode = tsadc_tshut_mode_v2,
|
|
|
|
.table = {
|
|
.knum = 2699,
|
|
.bnum = 2796,
|
|
.data_mask = TSADCV2_DATA_MASK,
|
|
.mode = ADC_INCREMENT,
|
|
},
|
|
};
|
|
|
|
static int rockchip_thermal_probe(struct udevice *dev)
|
|
{
|
|
struct rockchip_thermal_priv *priv = dev_get_priv(dev);
|
|
struct rockchip_tsadc_chip *tsadc;
|
|
struct clk clk;
|
|
int ret, i, shut_temp;
|
|
|
|
/* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */
|
|
ret = clk_set_defaults(dev);
|
|
if (ret)
|
|
printf("%s clk_set_defaults failed %d\n", __func__, ret);
|
|
|
|
if (soc_is_rk3308bs() || soc_is_px30s()) {
|
|
ret = clk_get_by_name(dev, "tsadc", &clk);
|
|
if (ret) {
|
|
printf("%s get tsadc clk fail\n", __func__);
|
|
return -EINVAL;
|
|
}
|
|
ret = clk_set_rate(&clk, 4000000);
|
|
if (ret < 0) {
|
|
printf("%s: failed to set tsadc clk rate for %s\n",
|
|
__func__, dev_read_name(dev));
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
if (soc_is_rk3308bs())
|
|
tsadc = (struct rockchip_tsadc_chip *)&rk3308bs_tsadc_data;
|
|
else if (soc_is_px30s())
|
|
tsadc = (struct rockchip_tsadc_chip *)&px30s_tsadc_data;
|
|
else
|
|
tsadc = (struct rockchip_tsadc_chip *)dev_get_driver_data(dev);
|
|
|
|
priv->data = tsadc;
|
|
|
|
priv->tshut_mode = dev_read_u32_default(dev,
|
|
"rockchip,hw-tshut-mode",
|
|
-1);
|
|
if (priv->tshut_mode < 0)
|
|
priv->tshut_mode = priv->data->tshut_mode;
|
|
|
|
priv->tshut_polarity = dev_read_u32_default(dev,
|
|
"rockchip,hw-tshut-polarity",
|
|
-1);
|
|
if (priv->tshut_polarity < 0)
|
|
priv->tshut_polarity = tsadc->tshut_polarity;
|
|
|
|
if (priv->tshut_mode == TSHUT_MODE_GPIO)
|
|
pinctrl_select_state(dev, "otpout");
|
|
else if (soc_is_rk3308())
|
|
pinctrl_select_state(dev, "gpio");
|
|
|
|
tsadc->tsadc_init(dev);
|
|
tsadc->irq_ack(dev);
|
|
|
|
shut_temp = dev_read_u32_default(dev, "rockchip,hw-tshut-temp", -1);
|
|
if (shut_temp < 0)
|
|
shut_temp = 120000;
|
|
|
|
for (i = 0; i < tsadc->chn_num; i++) {
|
|
tsadc->set_alarm_temp(dev, i, tsadc->tshut_temp);
|
|
tsadc->set_tshut_temp(dev, i, shut_temp);
|
|
if (priv->tshut_mode == TSHUT_MODE_GPIO)
|
|
tsadc->set_tshut_mode(dev, i, TSHUT_MODE_GPIO);
|
|
else
|
|
tsadc->set_tshut_mode(dev, i, TSHUT_MODE_CRU);
|
|
}
|
|
|
|
tsadc->tsadc_control(dev, true);
|
|
if (soc_is_rk3308bs() || soc_is_px30s())
|
|
mdelay(3);
|
|
else
|
|
udelay(1000);
|
|
|
|
debug("tsadc probed successfully\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rockchip_thermal_ofdata_to_platdata(struct udevice *dev)
|
|
{
|
|
struct rockchip_thermal_priv *priv = dev_get_priv(dev);
|
|
|
|
priv->base = dev_read_addr_ptr(dev);
|
|
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct rockchip_tsadc_chip rk1808_tsadc_data = {
|
|
.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
|
|
.chn_num = 1, /* one channel for tsadc */
|
|
|
|
.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
|
|
.tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
|
|
.tshut_temp = 95000,
|
|
|
|
.tsadc_init = tsadc_init_v2,
|
|
.tsadc_control = tsadc_control_v3,
|
|
.tsadc_get_temp = tsadc_get_temp_v2,
|
|
.irq_ack = tsadc_irq_ack_v3,
|
|
.set_alarm_temp = tsadc_alarm_temp_v2,
|
|
.set_tshut_temp = tsadc_tshut_temp_v2,
|
|
.set_tshut_mode = tsadc_tshut_mode_v2,
|
|
|
|
.table = {
|
|
.id = rk1808_code_table,
|
|
.length = ARRAY_SIZE(rk1808_code_table),
|
|
.data_mask = TSADCV2_DATA_MASK,
|
|
.mode = ADC_INCREMENT,
|
|
},
|
|
};
|
|
|
|
static const struct rockchip_tsadc_chip rk3228_tsadc_data = {
|
|
.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
|
|
.chn_num = 1, /* one channel for tsadc */
|
|
|
|
.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
|
|
.tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
|
|
.tshut_temp = 95000,
|
|
|
|
.tsadc_init = tsadc_init_v2,
|
|
.tsadc_control = tsadc_control_v3,
|
|
.tsadc_get_temp = tsadc_get_temp_v2,
|
|
.irq_ack = tsadc_irq_ack_v3,
|
|
.set_alarm_temp = tsadc_alarm_temp_v2,
|
|
.set_tshut_temp = tsadc_tshut_temp_v2,
|
|
.set_tshut_mode = tsadc_tshut_mode_v2,
|
|
|
|
.table = {
|
|
.id = rk3228_code_table,
|
|
.length = ARRAY_SIZE(rk3228_code_table),
|
|
.data_mask = TSADCV3_DATA_MASK,
|
|
.mode = ADC_INCREMENT,
|
|
},
|
|
};
|
|
|
|
static const struct rockchip_tsadc_chip rk3288_tsadc_data = {
|
|
.chn_id[SENSOR_CPU] = 1, /* cpu sensor is channel 1 */
|
|
.chn_id[SENSOR_GPU] = 2, /* gpu sensor is channel 2 */
|
|
.chn_num = 2, /* two channels for tsadc */
|
|
|
|
.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
|
|
.tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
|
|
.tshut_temp = 95000,
|
|
|
|
.tsadc_init = tsadc_init_v2,
|
|
.tsadc_control = tsadc_control_v2,
|
|
.tsadc_get_temp = tsadc_get_temp_v3,
|
|
.irq_ack = tsadc_irq_ack_v2,
|
|
.set_alarm_temp = tsadc_alarm_temp_v2,
|
|
.set_tshut_temp = tsadc_tshut_temp_v2,
|
|
.set_tshut_mode = tsadc_tshut_mode_v2,
|
|
|
|
.table = {
|
|
.id = rk3288_code_table,
|
|
.length = ARRAY_SIZE(rk3288_code_table),
|
|
.data_mask = TSADCV2_DATA_MASK,
|
|
.mode = ADC_DECREMENT,
|
|
},
|
|
};
|
|
|
|
static const struct rockchip_tsadc_chip rk3308_tsadc_data = {
|
|
.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
|
|
.chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
|
|
.chn_num = 2, /* 2 channels for tsadc */
|
|
|
|
.tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
|
|
.tshut_temp = 95000,
|
|
|
|
.tsadc_init = tsadc_init_v4,
|
|
.tsadc_control = tsadc_control_v3,
|
|
.tsadc_get_temp = tsadc_get_temp_v2,
|
|
.irq_ack = tsadc_irq_ack_v3,
|
|
.set_alarm_temp = tsadc_alarm_temp_v2,
|
|
.set_tshut_temp = tsadc_tshut_temp_v2,
|
|
.set_tshut_mode = tsadc_tshut_mode_v2,
|
|
|
|
.table = {
|
|
.id = rk3328_code_table,
|
|
.length = ARRAY_SIZE(rk3328_code_table),
|
|
.data_mask = TSADCV2_DATA_MASK,
|
|
.mode = ADC_INCREMENT,
|
|
},
|
|
};
|
|
|
|
static const struct rockchip_tsadc_chip px30_tsadc_data = {
|
|
.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
|
|
.chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
|
|
.chn_num = 2, /* 2 channels for tsadc */
|
|
|
|
.tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
|
|
.tshut_temp = 95000,
|
|
|
|
.tsadc_init = tsadc_init_v4,
|
|
.tsadc_control = tsadc_control_v3,
|
|
.tsadc_get_temp = tsadc_get_temp_v2,
|
|
.irq_ack = tsadc_irq_ack_v3,
|
|
.set_alarm_temp = tsadc_alarm_temp_v2,
|
|
.set_tshut_temp = tsadc_tshut_temp_v2,
|
|
.set_tshut_mode = tsadc_tshut_mode_v2,
|
|
|
|
.table = {
|
|
.id = rk3328_code_table,
|
|
.length = ARRAY_SIZE(rk3328_code_table),
|
|
.data_mask = TSADCV2_DATA_MASK,
|
|
.mode = ADC_INCREMENT,
|
|
},
|
|
};
|
|
|
|
static const struct rockchip_tsadc_chip rk3328_tsadc_data = {
|
|
.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
|
|
.chn_num = 1, /* one channels for tsadc */
|
|
|
|
.tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
|
|
.tshut_temp = 95000,
|
|
|
|
.tsadc_init = tsadc_init_v2,
|
|
.tsadc_control = tsadc_control_v3,
|
|
.tsadc_get_temp = tsadc_get_temp_v2,
|
|
.irq_ack = tsadc_irq_ack_v3,
|
|
.set_alarm_temp = tsadc_alarm_temp_v2,
|
|
.set_tshut_temp = tsadc_tshut_temp_v2,
|
|
.set_tshut_mode = tsadc_tshut_mode_v2,
|
|
|
|
.table = {
|
|
.id = rk3328_code_table,
|
|
.length = ARRAY_SIZE(rk3328_code_table),
|
|
.data_mask = TSADCV2_DATA_MASK,
|
|
.mode = ADC_INCREMENT,
|
|
},
|
|
};
|
|
|
|
static const struct rockchip_tsadc_chip rk3366_tsadc_data = {
|
|
.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
|
|
.chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
|
|
.chn_num = 2, /* two channels for tsadc */
|
|
|
|
.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
|
|
.tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
|
|
.tshut_temp = 95000,
|
|
|
|
.tsadc_init = tsadc_init_v3,
|
|
.tsadc_control = tsadc_control_v3,
|
|
.tsadc_get_temp = tsadc_get_temp_v2,
|
|
.irq_ack = tsadc_irq_ack_v3,
|
|
.set_alarm_temp = tsadc_alarm_temp_v2,
|
|
.set_tshut_temp = tsadc_tshut_temp_v2,
|
|
.set_tshut_mode = tsadc_tshut_mode_v2,
|
|
|
|
.table = {
|
|
.id = rk3228_code_table,
|
|
.length = ARRAY_SIZE(rk3228_code_table),
|
|
.data_mask = TSADCV3_DATA_MASK,
|
|
.mode = ADC_INCREMENT,
|
|
},
|
|
};
|
|
|
|
static const struct rockchip_tsadc_chip rk3368_tsadc_data = {
|
|
.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
|
|
.chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
|
|
.chn_num = 2, /* two channels for tsadc */
|
|
|
|
.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
|
|
.tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
|
|
.tshut_temp = 95000,
|
|
|
|
.tsadc_init = tsadc_init_v2,
|
|
.tsadc_control = tsadc_control_v2,
|
|
.tsadc_get_temp = tsadc_get_temp_v2,
|
|
.irq_ack = tsadc_irq_ack_v2,
|
|
.set_alarm_temp = tsadc_alarm_temp_v2,
|
|
.set_tshut_temp = tsadc_tshut_temp_v2,
|
|
.set_tshut_mode = tsadc_tshut_mode_v2,
|
|
|
|
.table = {
|
|
.id = rk3368_code_table,
|
|
.length = ARRAY_SIZE(rk3368_code_table),
|
|
.data_mask = TSADCV3_DATA_MASK,
|
|
.mode = ADC_INCREMENT,
|
|
},
|
|
};
|
|
|
|
static const struct rockchip_tsadc_chip rk3399_tsadc_data = {
|
|
.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
|
|
.chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
|
|
.chn_num = 2, /* two channels for tsadc */
|
|
|
|
.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
|
|
.tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
|
|
.tshut_temp = 95000,
|
|
|
|
.tsadc_init = tsadc_init_v3,
|
|
.tsadc_control = tsadc_control_v3,
|
|
.tsadc_get_temp = tsadc_get_temp_v2,
|
|
.irq_ack = tsadc_irq_ack_v3,
|
|
.set_alarm_temp = tsadc_alarm_temp_v2,
|
|
.set_tshut_temp = tsadc_tshut_temp_v2,
|
|
.set_tshut_mode = tsadc_tshut_mode_v2,
|
|
|
|
.table = {
|
|
.id = rk3399_code_table,
|
|
.length = ARRAY_SIZE(rk3399_code_table),
|
|
.data_mask = TSADCV3_DATA_MASK,
|
|
.mode = ADC_INCREMENT,
|
|
},
|
|
};
|
|
|
|
static const struct rockchip_tsadc_chip rk3528_tsadc_data = {
|
|
.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
|
|
.chn_num = 1, /* one channels for tsadc */
|
|
|
|
.tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via GPIO give PMIC */
|
|
.tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
|
|
.tshut_temp = 95000,
|
|
|
|
.tsadc_init = tsadc_init_v11,
|
|
.tsadc_control = tsadc_control_v4,
|
|
.tsadc_get_temp = tsadc_get_temp_v4,
|
|
.irq_ack = tsadc_irq_ack_v4,
|
|
.set_alarm_temp = tsadc_alarm_temp_v3,
|
|
.set_tshut_temp = tsadc_tshut_temp_v3,
|
|
.set_tshut_mode = tsadc_tshut_mode_v4,
|
|
|
|
.table = {
|
|
.id = rk3528_code_table,
|
|
.length = ARRAY_SIZE(rk3528_code_table),
|
|
.data_mask = TSADCV2_DATA_MASK,
|
|
.mode = ADC_INCREMENT,
|
|
},
|
|
};
|
|
|
|
static const struct rockchip_tsadc_chip rk3562_tsadc_data = {
|
|
.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
|
|
.chn_num = 1, /* one channels for tsadc */
|
|
|
|
.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
|
|
.tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
|
|
.tshut_temp = 95000,
|
|
|
|
.tsadc_init = tsadc_init_v12,
|
|
.tsadc_control = tsadc_control_v4,
|
|
.tsadc_get_temp = tsadc_get_temp_v4,
|
|
.irq_ack = tsadc_irq_ack_v4,
|
|
.set_alarm_temp = tsadc_alarm_temp_v3,
|
|
.set_tshut_temp = tsadc_tshut_temp_v3,
|
|
.set_tshut_mode = tsadc_tshut_mode_v4,
|
|
|
|
.table = {
|
|
.id = rk3562_code_table,
|
|
.length = ARRAY_SIZE(rk3562_code_table),
|
|
.data_mask = TSADCV2_DATA_MASK,
|
|
.mode = ADC_INCREMENT,
|
|
},
|
|
};
|
|
|
|
static const struct rockchip_tsadc_chip rk3568_tsadc_data = {
|
|
.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
|
|
.chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
|
|
.chn_num = 2, /* two channels for tsadc */
|
|
|
|
.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
|
|
.tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
|
|
.tshut_temp = 95000,
|
|
|
|
.tsadc_init = tsadc_init_v7,
|
|
.tsadc_control = tsadc_control_v3,
|
|
.tsadc_get_temp = tsadc_get_temp_v2,
|
|
.irq_ack = tsadc_irq_ack_v3,
|
|
.set_alarm_temp = tsadc_alarm_temp_v2,
|
|
.set_tshut_temp = tsadc_tshut_temp_v2,
|
|
.set_tshut_mode = tsadc_tshut_mode_v2,
|
|
|
|
.table = {
|
|
.id = rk3568_code_table,
|
|
.length = ARRAY_SIZE(rk3568_code_table),
|
|
.data_mask = TSADCV2_DATA_MASK,
|
|
.mode = ADC_INCREMENT,
|
|
},
|
|
};
|
|
|
|
static const struct rockchip_tsadc_chip rk3588_tsadc_data = {
|
|
/* top, big_core0, big_core1, little_core, center, gpu, npu */
|
|
.chn_id = {0, 1, 2, 3, 4, 5, 6},
|
|
.chn_num = 7, /* seven channels for tsadc */
|
|
|
|
.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
|
|
.tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
|
|
.tshut_temp = 95000,
|
|
|
|
.tsadc_init = tsadc_init_v8,
|
|
.tsadc_control = tsadc_control_v4,
|
|
.tsadc_get_temp = tsadc_get_temp_v4,
|
|
.irq_ack = tsadc_irq_ack_v4,
|
|
.set_alarm_temp = tsadc_alarm_temp_v3,
|
|
.set_tshut_temp = tsadc_tshut_temp_v3,
|
|
.set_tshut_mode = tsadc_tshut_mode_v4,
|
|
|
|
.table = {
|
|
.id = rk3588_code_table,
|
|
.length = ARRAY_SIZE(rk3588_code_table),
|
|
.data_mask = TSADCV4_DATA_MASK,
|
|
.mode = ADC_INCREMENT,
|
|
},
|
|
};
|
|
|
|
static const struct udevice_id rockchip_thermal_match[] = {
|
|
{
|
|
.compatible = "rockchip,px30-tsadc",
|
|
.data = (ulong)&px30_tsadc_data,
|
|
},
|
|
{
|
|
.compatible = "rockchip,px30s-tsadc",
|
|
.data = (ulong)&px30s_tsadc_data,
|
|
},
|
|
{
|
|
.compatible = "rockchip,rk1808-tsadc",
|
|
.data = (ulong)&rk1808_tsadc_data,
|
|
},
|
|
{
|
|
.compatible = "rockchip,rk3228-tsadc",
|
|
.data = (ulong)&rk3228_tsadc_data,
|
|
},
|
|
{
|
|
.compatible = "rockchip,rk3288-tsadc",
|
|
.data = (ulong)&rk3288_tsadc_data,
|
|
},
|
|
{
|
|
.compatible = "rockchip,rk3308-tsadc",
|
|
.data = (ulong)&rk3308_tsadc_data,
|
|
},
|
|
{
|
|
.compatible = "rockchip,rk3308bs-tsadc",
|
|
.data = (ulong)&rk3308bs_tsadc_data,
|
|
},
|
|
{
|
|
.compatible = "rockchip,rk3328-tsadc",
|
|
.data = (ulong)&rk3328_tsadc_data,
|
|
},
|
|
{
|
|
.compatible = "rockchip,rk3366-tsadc",
|
|
.data = (ulong)&rk3366_tsadc_data,
|
|
},
|
|
{
|
|
.compatible = "rockchip,rk3368-tsadc",
|
|
.data = (ulong)&rk3368_tsadc_data,
|
|
},
|
|
{
|
|
.compatible = "rockchip,rk3399-tsadc",
|
|
.data = (ulong)&rk3399_tsadc_data,
|
|
},
|
|
{
|
|
.compatible = "rockchip,rk3528-tsadc",
|
|
.data = (ulong)&rk3528_tsadc_data,
|
|
},
|
|
{
|
|
.compatible = "rockchip,rk3562-tsadc",
|
|
.data = (ulong)&rk3562_tsadc_data,
|
|
},
|
|
{
|
|
.compatible = "rockchip,rk3568-tsadc",
|
|
.data = (ulong)&rk3568_tsadc_data,
|
|
},
|
|
{
|
|
.compatible = "rockchip,rk3588-tsadc",
|
|
.data = (ulong)&rk3588_tsadc_data,
|
|
},
|
|
{ /* end */ },
|
|
};
|
|
|
|
U_BOOT_DRIVER(rockchip_thermal) = {
|
|
.name = "rockchip_thermal",
|
|
.id = UCLASS_THERMAL,
|
|
.of_match = rockchip_thermal_match,
|
|
.priv_auto_alloc_size = sizeof(struct rockchip_thermal_priv),
|
|
.ofdata_to_platdata = rockchip_thermal_ofdata_to_platdata,
|
|
.ops = &rockchip_thermal_ops,
|
|
.probe = rockchip_thermal_probe,
|
|
};
|