448 lines
9.0 KiB
Plaintext
448 lines
9.0 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2021 Rockchip Electronics Co., Ltd
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*
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*/
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#include <dt-bindings/display/drm_mipi_dsi.h>
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#include <dt-bindings/clock/rk618-cru.h>
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/ {
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backlight: backlight {
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status = "okay";
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compatible = "pwm-backlight";
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pwms = <&pwm1 0 25000 0>;
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brightness-levels = <
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0 1 2 3 4 5 6 7
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8 9 10 11 12 13 14 15
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16 17 18 19 20 21 22 23
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24 25 26 27 28 29 30 31
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32 33 34 35 36 37 38 39
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40 41 42 43 44 45 46 47
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48 49 50 51 52 53 54 55
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56 57 58 59 60 61 62 63
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64 65 66 67 68 69 70 71
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72 73 74 75 76 77 78 79
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80 81 82 83 84 85 86 87
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88 89 90 91 92 93 94 95
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96 97 98 99 100 101 102 103
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104 105 106 107 108 109 110 111
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112 113 114 115 116 117 118 119
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120 121 122 123 124 125 126 127
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128 129 130 131 132 133 134 135
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136 137 138 139 140 141 142 143
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144 145 146 147 148 149 150 151
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152 153 154 155 156 157 158 159
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160 161 162 163 164 165 166 167
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168 169 170 171 172 173 174 175
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176 177 178 179 180 181 182 183
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184 185 186 187 188 189 190 191
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192 193 194 195 196 197 198 199
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200 201 202 203 204 205 206 207
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208 209 210 211 212 213 214 215
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216 217 218 219 220 221 222 223
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224 225 226 227 228 229 230 231
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232 233 234 235 236 237 238 239
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240 241 242 243 244 245 246 247
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248 249 250 251 252 253 254 255>;
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default-brightness-level = <200>;
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};
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vcc3v3_lcd_n: vcc3v3-lcd-n {
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compatible = "regulator-fixed";
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regulator-name = "vcc3v3_lcd_n";
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pinctrl-names = "default";
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pinctrl-0 = <&lcd_en>;
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gpio = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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regulator-boot-on;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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cma {
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compatible = "shared-dma-pool";
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reusable;
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size = <0x0 0x2000000>;
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linux,cma-default;
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};
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};
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};
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&i2c0 {
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clock-frequency = <100000>;
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status = "okay";
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gt1x: gt1x@14 {
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compatible = "goodix,gt1x";
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reg = <0x14>;
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pinctrl-names = "default";
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pinctrl-0 = <&tp_int>;
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power-supply = <&vcc3v3_lcd_n>;
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goodix,rst-gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
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goodix,irq-gpio = <&gpio0 RK_PC0 IRQ_TYPE_LEVEL_LOW>;
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};
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rk618@50 {
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compatible = "rockchip,rk618";
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reg = <0x50>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2s_8ch_0_mclk>;
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clocks = <&cru SCLK_I2S0_8CH_TX_OUT>;
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clock-names = "clkin";
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assigned-clocks = <&cru SCLK_I2S0_8CH_TX_OUT>;
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assigned-clock-rates = <12000000>;
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power-supply = <&vcc3v3_lcd_n>;
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reset-gpios = <&gpio2 RK_PB2 GPIO_ACTIVE_LOW>;
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status = "okay";
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clock: cru {
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compatible = "rockchip,rk618-cru";
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clocks = <&cru SCLK_I2S0_8CH_TX_OUT>, <&cru DCLK_VOP>;
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clock-names = "clkin", "lcdc0_dclkp";
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assigned-clocks = <&clock SCALER_PLLIN_CLK>,
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<&clock VIF_PLLIN_CLK>,
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<&clock SCALER_CLK>,
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<&clock VIF0_PRE_CLK>,
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<&clock CODEC_CLK>,
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<&clock DITHER_CLK>;
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assigned-clock-parents = <&cru SCLK_I2S0_8CH_TX_OUT>,
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<&clock LCDC0_CLK>,
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<&clock SCALER_PLL_CLK>,
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<&clock VIF_PLL_CLK>,
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<&cru SCLK_I2S0_8CH_TX_OUT>,
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<&clock VIF0_CLK>;
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#clock-cells = <1>;
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status = "okay";
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};
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dsi {
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compatible = "rockchip,rk618-dsi";
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clocks = <&clock MIPI_CLK>;
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clock-names = "dsi";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dsi_in_rgb: endpoint {
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remote-endpoint = <&rgb_out_dsi>;
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};
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};
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};
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panel@0 {
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compatible = "sitronix,st7703", "simple-panel-dsi";
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reg = <0>;
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power-supply = <&vcc3v3_lcd_n>;
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backlight = <&backlight>;
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prepare-delay-ms = <0>;
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reset-delay-ms = <0>;
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init-delay-ms = <80>;
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enable-delay-ms = <0>;
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disable-delay-ms = <10>;
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unprepare-delay-ms = <60>;
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width-mm = <68>;
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height-mm = <121>;
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dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
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MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
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dsi,format = <MIPI_DSI_FMT_RGB888>;
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dsi,lanes = <4>;
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panel-init-sequence = [
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39 00 04 ff 98 81 03
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15 00 02 01 00
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15 00 02 02 00
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15 00 02 03 53
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15 00 02 04 53
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15 00 02 05 13
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15 00 02 06 04
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15 00 02 07 02
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15 00 02 08 02
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15 00 02 09 00
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15 00 02 0a 00
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15 00 02 0b 00
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15 00 02 0c 00
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15 00 02 0d 00
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15 00 02 0e 00
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15 00 02 0f 00
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15 00 02 10 00
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15 00 02 11 00
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15 00 02 12 00
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15 00 02 13 00
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15 00 02 14 00
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15 00 02 15 08
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15 00 02 16 10
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15 00 02 17 00
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15 00 02 18 08
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15 00 02 19 00
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15 00 02 1a 00
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15 00 02 1b 00
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15 00 02 1c 00
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15 00 02 1d 00
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15 00 02 1e c0
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15 00 02 1f 80
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15 00 02 20 02
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15 00 02 21 09
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15 00 02 22 00
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15 00 02 23 00
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15 00 02 24 00
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15 00 02 25 00
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15 00 02 26 00
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15 00 02 27 00
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15 00 02 28 55
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15 00 02 29 03
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15 00 02 2a 00
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15 00 02 2b 00
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15 00 02 2c 00
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15 00 02 2d 00
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15 00 02 2e 00
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15 00 02 2f 00
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15 00 02 30 00
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15 00 02 31 00
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15 00 02 32 00
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15 00 02 33 00
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15 00 02 34 04
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15 00 02 35 05
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15 00 02 36 05
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15 00 02 37 00
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15 00 02 38 3c
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15 00 02 39 35
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15 00 02 3a 00
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15 00 02 3b 40
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15 00 02 3c 00
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15 00 02 3d 00
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15 00 02 3e 00
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15 00 02 3f 00
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15 00 02 40 00
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15 00 02 41 88
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15 00 02 42 00
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15 00 02 43 00
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15 00 02 44 1f
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15 00 02 50 01
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15 00 02 51 23
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15 00 02 52 45
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15 00 02 53 67
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15 00 02 54 89
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15 00 02 55 ab
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15 00 02 56 01
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15 00 02 57 23
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15 00 02 58 45
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15 00 02 59 67
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15 00 02 5a 89
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15 00 02 5b ab
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15 00 02 5c cd
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15 00 02 5d ef
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15 00 02 5e 03
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15 00 02 5f 14
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15 00 02 60 15
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15 00 02 61 0c
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15 00 02 62 0d
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15 00 02 63 0e
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15 00 02 64 0f
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15 00 02 65 10
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15 00 02 66 11
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15 00 02 67 08
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15 00 02 68 02
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15 00 02 69 0a
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15 00 02 6a 02
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15 00 02 6b 02
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15 00 02 6c 02
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15 00 02 6d 02
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15 00 02 6e 02
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15 00 02 6f 02
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15 00 02 70 02
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15 00 02 71 02
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15 00 02 72 06
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15 00 02 73 02
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15 00 02 74 02
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15 00 02 75 14
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15 00 02 76 15
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15 00 02 77 0f
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15 00 02 78 0e
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15 00 02 79 0d
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15 00 02 7a 0c
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15 00 02 7b 11
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15 00 02 7c 10
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15 00 02 7d 06
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15 00 02 7e 02
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15 00 02 7f 0a
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15 00 02 80 02
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15 00 02 81 02
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15 00 02 82 02
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15 00 02 83 02
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15 00 02 84 02
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15 00 02 85 02
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15 00 02 86 02
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15 00 02 87 02
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15 00 02 88 08
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15 00 02 89 02
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15 00 02 8a 02
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39 00 04 ff 98 81 04
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15 00 02 00 80
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15 00 02 70 00
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15 00 02 71 00
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15 00 02 66 fe
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15 00 02 82 15
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15 00 02 84 15
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15 00 02 85 15
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15 00 02 3a 24
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15 00 02 32 ac
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15 00 02 8c 80
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15 00 02 3c f5
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15 00 02 88 33
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39 00 04 ff 98 81 01
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15 00 02 22 0a
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15 00 02 31 00
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15 00 02 53 78
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15 00 02 50 5b
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15 00 02 51 5b
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15 00 02 60 20
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15 00 02 61 00
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15 00 02 62 0d
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15 00 02 63 00
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15 00 02 a0 00
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15 00 02 a1 10
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15 00 02 a2 1c
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15 00 02 a3 13
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15 00 02 a4 15
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15 00 02 a5 26
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15 00 02 a6 1a
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15 00 02 a7 1d
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15 00 02 a8 67
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15 00 02 a9 1c
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15 00 02 aa 29
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15 00 02 ab 5b
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15 00 02 ac 26
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15 00 02 ad 28
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15 00 02 ae 5c
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15 00 02 af 30
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15 00 02 b0 31
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15 00 02 b1 2e
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15 00 02 b2 32
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15 00 02 b3 00
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15 00 02 c0 00
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15 00 02 c1 10
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15 00 02 c2 1c
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15 00 02 c3 13
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15 00 02 c4 15
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15 00 02 c5 26
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15 00 02 c6 1a
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15 00 02 c7 1d
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15 00 02 c8 67
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15 00 02 c9 1c
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15 00 02 ca 29
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15 00 02 cb 5b
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15 00 02 cc 26
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15 00 02 cd 28
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15 00 02 ce 5c
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15 00 02 cf 30
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15 00 02 d0 31
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15 00 02 d1 2e
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15 00 02 d2 32
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15 00 02 d3 00
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39 00 04 ff 98 81 00
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05 00 01 11
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05 01 01 29
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];
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panel-exit-sequence = [
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05 00 01 28
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05 00 01 10
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];
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display-timings {
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native-mode = <&timing0>;
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timing0: timing0 {
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clock-frequency = <65000000>;
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hactive = <720>;
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vactive = <1280>;
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hfront-porch = <48>;
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hsync-len = <8>;
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hback-porch = <52>;
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vfront-porch = <16>;
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vsync-len = <6>;
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vback-porch = <15>;
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hsync-active = <0>;
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vsync-active = <0>;
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de-active = <0>;
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pixelclk-active = <0>;
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};
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};
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};
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};
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};
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};
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&display_subsystem {
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status = "okay";
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};
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&pinctrl {
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lcd {
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lcd_en: lcd-en {
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rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
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};
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tp_int: tp-int {
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rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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};
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&pwm1 {
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status = "okay";
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};
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&rgb {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&lcdc_ctl &lcdc_rgb888_m1>;
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ports {
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rgb_out: port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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rgb_out_dsi: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&dsi_in_rgb>;
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};
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};
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};
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};
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&route_rgb {
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logo,kernel = "logo_kernel.bmp";
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status = "okay";
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};
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&vop {
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status = "okay";
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};
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