2497 lines
68 KiB
Plaintext
2497 lines
68 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
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*/
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#include <dt-bindings/clock/rk3528-cru.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/power/rk3528-power.h>
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#include <dt-bindings/soc/rockchip,boot-mode.h>
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#include <dt-bindings/soc/rockchip-system-status.h>
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#include <dt-bindings/suspend/rockchip-rk3528.h>
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#include <dt-bindings/thermal/thermal.h>
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#include <dt-bindings/display/rockchip-tve.h>
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/ {
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compatible = "rockchip,rk3528";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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ethernet0 = &gmac0;
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ethernet1 = &gmac1;
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gpio0 = &gpio0;
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gpio1 = &gpio1;
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gpio2 = &gpio2;
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gpio3 = &gpio3;
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gpio4 = &gpio4;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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i2c4 = &i2c4;
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i2c5 = &i2c5;
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i2c6 = &i2c6;
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i2c7 = &i2c7;
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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serial4 = &uart4;
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serial5 = &uart5;
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serial6 = &uart6;
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serial7 = &uart7;
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spi0 = &spi0;
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spi1 = &spi1;
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spi2 = &sfc;
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};
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clocks {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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xin24m: xin24m {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "xin24m";
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};
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mclkin_sai0: mclkin-sai0 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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clock-output-names = "i2s0_mclkin";
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};
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mclkin_sai1: mclkin-sai1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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clock-output-names = "i2s1_mclkin";
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};
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mclkout_sai0: mclkout-sai0@ff340014 {
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compatible = "rockchip,clk-out";
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reg = <0 0xff340014 0 0x4>;
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clocks = <&cru MCLK_SAI_I2S0>;
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#clock-cells = <0>;
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clock-output-names = "mclk_sai0_to_io";
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rockchip,bit-shift = <1>;
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rockchip,bit-set-to-disable;
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};
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mclkout_sai1: mclkout-sai1@ff320004 {
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compatible = "rockchip,clk-out";
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reg = <0 0xff320004 0 0x4>;
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clocks = <&cru MCLK_SAI_I2S1>;
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#clock-cells = <0>;
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clock-output-names = "mclk_sai1_to_io";
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rockchip,bit-shift = <14>;
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rockchip,bit-set-to-disable;
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};
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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core2 {
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cpu = <&cpu2>;
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};
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core3 {
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cpu = <&cpu3>;
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};
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};
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};
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x0>;
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enable-method = "psci";
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clocks = <&scmi_clk SCMI_CLK_CPU>;
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#cooling-cells = <2>; /* min followed by max */
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dynamic-power-coefficient = <147>;
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operating-points-v2 = <&cpu0_opp_table>;
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cpu-idle-states = <&CPU_SLEEP0>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x1>;
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enable-method = "psci";
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clocks = <&scmi_clk SCMI_CLK_CPU>;
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operating-points-v2 = <&cpu0_opp_table>;
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cpu-idle-states = <&CPU_SLEEP0>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x2>;
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enable-method = "psci";
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clocks = <&scmi_clk SCMI_CLK_CPU>;
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operating-points-v2 = <&cpu0_opp_table>;
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cpu-idle-states = <&CPU_SLEEP1>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x3>;
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enable-method = "psci";
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clocks = <&scmi_clk SCMI_CLK_CPU>;
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operating-points-v2 = <&cpu0_opp_table>;
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cpu-idle-states = <&CPU_SLEEP1>;
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};
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idle-states {
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entry-method = "psci";
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CPU_SLEEP0: cpu-sleep0 {
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compatible = "arm,idle-state";
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local-timer-stop;
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arm,psci-suspend-param = <0x0010000>;
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entry-latency-us = <120>;
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exit-latency-us = <250>;
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min-residency-us = <900>;
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status = "disabled";
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};
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CPU_SLEEP1: cpu-sleep {
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compatible = "arm,idle-state";
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local-timer-stop;
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arm,psci-suspend-param = <0x0010000>;
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entry-latency-us = <120>;
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exit-latency-us = <250>;
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min-residency-us = <900>;
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status = "okay";
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};
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};
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};
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cpu0_opp_table: cpu0-opp-table {
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compatible = "operating-points-v2";
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opp-shared;
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mbist-vmin = <825000 925000 975000>;
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nvmem-cells = <&cpu_leakage>, <&cpu_opp_info>, <&cpu_mbist_vmin>;
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nvmem-cell-names = "leakage", "opp-info", "mbist-vmin";
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rockchip,video-4k-freq = <1200000>;
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rockchip,pvtm-voltage-sel = <
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0 1320 0
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1321 1350 1
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1351 1375 2
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1376 1405 3
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1406 1435 4
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1436 1470 5
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1471 1505 6
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1506 1540 7
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1541 1575 8
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1576 1610 9
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1611 1640 10
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1641 9999 11
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>;
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rockchip,pvtm-pvtpll;
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rockchip,pvtm-offset = <0x18>;
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rockchip,pvtm-sample-time = <1100>;
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rockchip,pvtm-freq = <1608000>;
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rockchip,pvtm-volt = <900000>;
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rockchip,pvtm-ref-temp = <40>;
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rockchip,pvtm-temp-prop = <0 0>;
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rockchip,pvtm-thermal-zone = "soc-thermal";
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rockchip,grf = <&grf>;
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opp-408000000 {
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opp-hz = /bits/ 64 <408000000>;
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opp-microvolt = <825000 825000 1100000>;
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opp-microvolt-L0 = <875000 875000 1100000>;
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opp-microvolt-L1 = <875000 875000 1100000>;
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opp-microvolt-L2 = <875000 875000 1100000>;
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opp-microvolt-L3 = <875000 875000 1100000>;
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opp-microvolt-L4 = <875000 875000 1100000>;
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opp-microvolt-L5 = <850000 850000 1100000>;
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clock-latency-ns = <40000>;
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opp-suspend;
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};
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opp-600000000 {
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opp-hz = /bits/ 64 <600000000>;
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opp-microvolt = <825000 825000 1100000>;
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opp-microvolt-L0 = <875000 875000 1100000>;
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opp-microvolt-L1 = <875000 875000 1100000>;
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opp-microvolt-L2 = <875000 875000 1100000>;
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opp-microvolt-L3 = <875000 875000 1100000>;
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opp-microvolt-L4 = <875000 875000 1100000>;
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opp-microvolt-L5 = <850000 850000 1100000>;
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clock-latency-ns = <40000>;
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};
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opp-816000000 {
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opp-hz = /bits/ 64 <816000000>;
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opp-microvolt = <825000 825000 1100000>;
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opp-microvolt-L0 = <875000 875000 1100000>;
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opp-microvolt-L1 = <875000 875000 1100000>;
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opp-microvolt-L2 = <875000 875000 1100000>;
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opp-microvolt-L3 = <875000 875000 1100000>;
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opp-microvolt-L4 = <875000 875000 1100000>;
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opp-microvolt-L5 = <850000 850000 1100000>;
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clock-latency-ns = <40000>;
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};
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opp-1008000000 {
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opp-hz = /bits/ 64 <1008000000>;
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opp-microvolt = <825000 825000 1100000>;
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opp-microvolt-L0 = <875000 875000 1100000>;
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opp-microvolt-L1 = <875000 875000 1100000>;
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opp-microvolt-L2 = <875000 875000 1100000>;
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opp-microvolt-L3 = <875000 875000 1100000>;
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opp-microvolt-L4 = <875000 875000 1100000>;
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opp-microvolt-L5 = <850000 850000 1100000>;
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clock-latency-ns = <40000>;
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};
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opp-1200000000 {
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opp-hz = /bits/ 64 <1200000000>;
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opp-microvolt = <825000 825000 1100000>;
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opp-microvolt-L0 = <900000 900000 1100000>;
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opp-microvolt-L1 = <887500 887500 1100000>;
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opp-microvolt-L2 = <875000 875000 1100000>;
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opp-microvolt-L3 = <875000 875000 1100000>;
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opp-microvolt-L4 = <875000 875000 1100000>;
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opp-microvolt-L5 = <862500 862500 1100000>;
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opp-microvolt-L6 = <850000 850000 1100000>;
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clock-latency-ns = <40000>;
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};
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opp-1416000000 {
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opp-hz = /bits/ 64 <1416000000>;
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opp-microvolt = <962500 962500 1100000>;
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opp-microvolt-L1 = <950000 950000 1100000>;
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opp-microvolt-L2 = <950000 950000 1100000>;
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opp-microvolt-L3 = <937500 937500 1100000>;
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opp-microvolt-L4 = <925000 925000 1100000>;
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opp-microvolt-L5 = <912500 912500 1100000>;
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opp-microvolt-L6 = <900000 900000 1100000>;
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opp-microvolt-L7 = <887500 887000 1100000>;
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opp-microvolt-L8 = <875000 875000 1100000>;
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opp-microvolt-L9 = <862500 862500 1100000>;
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opp-microvolt-L10 = <850000 850000 1100000>;
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opp-microvolt-L11 = <850000 850000 1100000>;
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clock-latency-ns = <40000>;
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};
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opp-1608000000 {
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opp-hz = /bits/ 64 <1608000000>;
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opp-microvolt = <1012500 1012500 1100000>;
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opp-microvolt-L2 = <1000000 1000000 1100000>;
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opp-microvolt-L3 = <987500 987500 1100000>;
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opp-microvolt-L4 = <975000 975000 1100000>;
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opp-microvolt-L5 = <962500 962500 1100000>;
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opp-microvolt-L6 = <950000 950000 1100000>;
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opp-microvolt-L7 = <937500 937500 1100000>;
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opp-microvolt-L8 = <925000 925000 1100000>;
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opp-microvolt-L9 = <912500 912500 1100000>;
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opp-microvolt-L10 = <900000 900000 1100000>;
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opp-microvolt-L11 = <887500 887500 1100000>;
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clock-latency-ns = <40000>;
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};
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opp-1800000000 {
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opp-hz = /bits/ 64 <1800000000>;
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opp-microvolt = <1062500 1062500 1100000>;
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opp-microvolt-L1 = <1050000 1050000 1100000>;
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opp-microvolt-L2 = <1037500 1037500 1100000>;
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opp-microvolt-L3 = <1025000 1025000 1100000>;
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opp-microvolt-L4 = <1012500 1012500 1100000>;
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opp-microvolt-L5 = <1000000 1000000 1100000>;
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opp-microvolt-L6 = <987500 987500 1100000>;
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opp-microvolt-L7 = <975000 975000 1100000>;
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opp-microvolt-L8 = <962500 962500 1100000>;
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opp-microvolt-L9 = <950000 950000 1100000>;
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opp-microvolt-L10 = <937500 937500 1100000>;
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opp-microvolt-L11 = <925000 925000 1100000>;
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clock-latency-ns = <40000>;
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};
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opp-2016000000 {
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opp-hz = /bits/ 64 <2016000000>;
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opp-microvolt = <1100000 1100000 1100000>;
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opp-microvolt-L1 = <1087500 1087500 1100000>;
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opp-microvolt-L2 = <1075000 1075000 1100000>;
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opp-microvolt-L3 = <1062500 1062500 1100000>;
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opp-microvolt-L4 = <1050000 1050000 1100000>;
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opp-microvolt-L5 = <1037500 1037500 1100000>;
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opp-microvolt-L6 = <1025000 1025000 1100000>;
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opp-microvolt-L7 = <1012500 1012500 1100000>;
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opp-microvolt-L8 = <1000000 1000000 1100000>;
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opp-microvolt-L9 = <987500 987500 1100000>;
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opp-microvolt-L10 = <975000 975000 1100000>;
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opp-microvolt-L11 = <962500 962500 1100000>;
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clock-latency-ns = <40000>;
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};
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};
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arm-pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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};
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cpuinfo {
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compatible = "rockchip,cpuinfo";
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nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>;
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nvmem-cell-names = "id", "cpu-version", "cpu-code";
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};
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display_subsystem: display-subsystem {
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compatible = "rockchip,display-subsystem";
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ports = <&vop_out>;
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status = "disabled";
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};
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dmc: dmc {
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compatible = "rockchip,rk3528-dmc";
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "complete";
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devfreq-events = <&dfi>;
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clocks = <&scmi_clk SCMI_CLK_DDR>;
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clock-names = "dmc_clk";
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operating-points-v2 = <&dmc_opp_table>;
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upthreshold = <40>;
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downdifferential = <20>;
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system-status-level = <
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/* system status freq level */
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SYS_STATUS_NORMAL DMC_FREQ_LEVEL_HIGH
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>;
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auto-min-freq = <324000>;
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auto-freq-en = <0>;
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status = "disabled";
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};
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dmc_opp_table: dmc-opp-table {
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compatible = "operating-points-v2";
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mbist-vmin = <850000 900000>;
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nvmem-cells = <&log_leakage>, <&dmc_opp_info>, <&logic_mbist_vmin>;
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nvmem-cell-names = "leakage", "opp-info", "mbist-vmin";
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rockchip,temp-hysteresis = <5000>;
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rockchip,low-temp = <10000>;
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rockchip,low-temp-min-volt = <900000>;
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rockchip,leakage-voltage-sel = <
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1 10 0
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11 14 1
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15 22 2
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23 28 3
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29 254 4
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>;
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opp-920000000 {
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opp-hz = /bits/ 64 <920000000>;
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opp-microvolt = <850000 850000 1000000>;
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};
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opp-1056000000 {
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opp-hz = /bits/ 64 <1056000000>;
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opp-microvolt = <850000 850000 1000000>;
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opp-microvolt-L0 = <875000 875000 1000000>;
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opp-microvolt-L1 = <850000 850000 1000000>;
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opp-microvolt-L2 = <850000 850000 1000000>;
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opp-microvolt-L3 = <850000 850000 1000000>;
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opp-microvolt-L4 = <850000 850000 1000000>;
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};
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opp-1184000000 {
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opp-hz = /bits/ 64 <1184000000>;
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opp-microvolt = <900000 900000 1000000>;
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opp-microvolt-L0 = <950000 950000 1000000>;
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opp-microvolt-L1 = <925000 925000 1000000>;
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opp-microvolt-L2 = <900000 900000 1000000>;
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opp-microvolt-L3 = <875000 875000 1000000>;
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opp-microvolt-L4 = <862500 862500 1000000>;
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status = "disabled";
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};
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};
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firmware {
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scmi: scmi {
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compatible = "arm,scmi-smc";
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shmem = <&scmi_shmem>;
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arm,smc-id = <0x82000010>;
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#address-cells = <1>;
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#size-cells = <0>;
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scmi_clk: protocol@14 {
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reg = <0x14>;
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#clock-cells = <1>;
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assigned-clocks = <&scmi_clk SCMI_CLK_CPU>;
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assigned-clock-rates = <1200000000>;
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};
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};
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};
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mpp_srv: mpp-srv {
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compatible = "rockchip,mpp-service";
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rockchip,taskqueue-count = <5>;
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rockchip,resetgroup-count = <5>;
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status = "disabled";
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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rkvtunnel: rkvtunnel {
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compatible = "rockchip,video-tunnel";
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status = "disabled";
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};
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rockchip_suspend: rockchip-suspend {
|
|
compatible = "rockchip,pm-rk3528";
|
|
status = "disabled";
|
|
rockchip,sleep-debug-en = <0>;
|
|
rockchip,sleep-mode-config = <
|
|
(0
|
|
| RKPM_SLP_ARMPD
|
|
)
|
|
>;
|
|
rockchip,wakeup-config = <
|
|
(0
|
|
| RKPM_CPU0_WKUP_EN
|
|
| RKPM_GPIO_WKUP_EN
|
|
)
|
|
>;
|
|
};
|
|
|
|
rockchip_system_monitor: rockchip-system-monitor {
|
|
compatible = "rockchip,system-monitor";
|
|
|
|
rockchip,thermal-zone = "soc-thermal";
|
|
rockchip,polling-delay = <200>; /* milliseconds */
|
|
rockchip,temp-hysteresis = <5000>; /* millicelsius */
|
|
rockchip,offline-cpu-temp = <105000>; /* millicelsius */
|
|
rockchip,temp-offline-cpus = "2-3";
|
|
};
|
|
|
|
secure_otp: secure-otp {
|
|
compatible = "rockchip,secure-otp";
|
|
rockchip,otp-size = <32>;
|
|
status = "disabled";
|
|
};
|
|
|
|
thermal_zones: thermal-zones {
|
|
soc_thermal: soc-thermal {
|
|
polling-delay-passive = <20>; /* milliseconds */
|
|
polling-delay = <1000>; /* milliseconds */
|
|
sustainable-power = <638>; /* milliwatts */
|
|
|
|
thermal-sensors = <&tsadc 0>;
|
|
|
|
trips {
|
|
threshold: trip-point-0 {
|
|
temperature = <95000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
target: trip-point-1 {
|
|
temperature = <110000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
soc_crit: soc-crit {
|
|
temperature = <120000>; /* millicelsius */
|
|
hysteresis = <2000>; /* millicelsius */
|
|
type = "critical";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
map0 {
|
|
trip = <&target>;
|
|
cooling-device =
|
|
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
contribution = <1024>;
|
|
};
|
|
map1 {
|
|
trip = <&target>;
|
|
cooling-device =
|
|
<&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
contribution = <1024>;
|
|
};
|
|
};
|
|
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
|
};
|
|
|
|
scmi_shmem: scmi-shmem@10f000 {
|
|
compatible = "arm,scmi-shmem";
|
|
reg = <0x0 0x0010f000 0x0 0x100>;
|
|
};
|
|
|
|
sram: sram@fe480000 {
|
|
compatible = "mmio-sram";
|
|
reg = <0x0 0xfe480000 0x0 0xc000>;
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x0 0xfe480000 0xc000>;
|
|
|
|
/* start address and size should be 4k algin */
|
|
rkvdec_sram: rkvdec-sram@0 {
|
|
reg = <0x0 0xc000>;
|
|
};
|
|
};
|
|
|
|
pcie2x1: pcie@fe4f0000 {
|
|
compatible = "rockchip,rk3528-pcie", "snps,dw-pcie";
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
bus-range = <0x0 0xff>;
|
|
clocks = <&cru ACLK_PCIE>, <&cru HCLK_PCIE_SLV>,
|
|
<&cru HCLK_PCIE_DBI>, <&cru PCLK_CRU_PCIE>,
|
|
<&cru CLK_PCIE_AUX>, <&cru PCLK_PCIE>,
|
|
<&cru PCLK_PCIE_PHY>;
|
|
clock-names = "aclk", "hclk_slv",
|
|
"hclk_dbi", "pclk_cru",
|
|
"aux", "pclk",
|
|
"pipe";
|
|
device_type = "pci";
|
|
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "msi", "pmc", "sys", "legacy", "msg", "err";
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 7>;
|
|
interrupt-map = <0 0 0 1 &pcie2x1_intc 0>,
|
|
<0 0 0 2 &pcie2x1_intc 1>,
|
|
<0 0 0 3 &pcie2x1_intc 2>,
|
|
<0 0 0 4 &pcie2x1_intc 3>;
|
|
linux,pci-domain = <0>;
|
|
num-ib-windows = <8>;
|
|
num-ob-windows = <8>;
|
|
num-viewport = <4>;
|
|
max-link-speed = <2>;
|
|
num-lanes = <1>;
|
|
phys = <&combphy_pu PHY_TYPE_PCIE>;
|
|
phy-names = "pcie-phy";
|
|
ranges = <0x00000800 0x0 0xfc000000 0x0 0xfc000000 0x0 0x100000
|
|
0x81000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x100000
|
|
0x82000000 0x0 0xfc200000 0x0 0xfc200000 0x0 0x1e00000
|
|
0xc3000000 0x1 0x00000000 0x1 0x00000000 0x0 0x40000000>;
|
|
reg = <0x0 0xfe4f0000 0x0 0x10000>,
|
|
<0x1 0x40000000 0x0 0x400000>;
|
|
reg-names = "pcie-apb", "pcie-dbi";
|
|
resets = <&cru SRST_RESETN_PCIE_POWER_UP>, <&cru SRST_PRESETN_PCIE>,
|
|
<&cru SRST_PRESETN_CRU_PCIE>;
|
|
reset-names = "pcie", "periph", "preset_cru";
|
|
status = "disabled";
|
|
|
|
pcie2x1_intc: legacy-interrupt-controller {
|
|
interrupt-controller;
|
|
#address-cells = <0>;
|
|
#interrupt-cells = <1>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 155 IRQ_TYPE_EDGE_RISING>;
|
|
};
|
|
};
|
|
|
|
usbdrd30: usbdrd {
|
|
compatible = "rockchip,rk3528-dwc3", "rockchip,rk3399-dwc3";
|
|
clocks = <&cru CLK_REF_USB3OTG>, <&cru CLK_SUSPEND_USB3OTG>,
|
|
<&cru ACLK_USB3OTG>;
|
|
clock-names = "ref_clk", "suspend_clk",
|
|
"bus_clk";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
status = "disabled";
|
|
|
|
usbdrd_dwc3: dwc3@fe500000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0x0 0xfe500000 0x0 0x400000>;
|
|
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
|
|
dr_mode = "otg";
|
|
phys = <&u2phy_otg>, <&combphy_pu PHY_TYPE_USB3>;
|
|
phy-names = "usb2-phy", "usb3-phy";
|
|
phy_type = "utmi_wide";
|
|
resets = <&cru SRST_ARESETN_USB3OTG>;
|
|
reset-names = "usb3-otg";
|
|
snps,dis_enblslpm_quirk;
|
|
snps,dis-u1-entry-quirk;
|
|
snps,dis-u2-entry-quirk;
|
|
snps,dis-u2-freeclk-exists-quirk;
|
|
snps,dis-del-phy-power-chg-quirk;
|
|
snps,dis-tx-ipgap-linecheck-quirk;
|
|
snps,xhci-trb-ent-quirk;
|
|
snps,dis_rxdet_inp3_quirk;
|
|
snps,parkmode-disable-hs-quirk;
|
|
snps,parkmode-disable-ss-quirk;
|
|
quirk-skip-phy-init;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
gic: interrupt-controller@fed01000 {
|
|
compatible = "arm,gic-400";
|
|
#interrupt-cells = <3>;
|
|
#address-cells = <0>;
|
|
interrupt-controller;
|
|
reg = <0x0 0xfed01000 0 0x1000>,
|
|
<0x0 0xfed02000 0 0x2000>,
|
|
<0x0 0xfed04000 0 0x2000>,
|
|
<0x0 0xfed06000 0 0x2000>;
|
|
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
|
};
|
|
|
|
usb_host0_ehci: usb@ff100000 {
|
|
compatible = "generic-ehci";
|
|
reg = <0x0 0xff100000 0x0 0x40000>;
|
|
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru HCLK_USBHOST>,
|
|
<&cru HCLK_USBHOST_ARB>,
|
|
<&usb2phy>;
|
|
clock-names = "usbhost", "arbiter", "utmi";
|
|
phys = <&u2phy_host>;
|
|
phy-names = "usb2-phy";
|
|
status = "disabled";
|
|
};
|
|
|
|
usb_host0_ohci: usb@ff140000 {
|
|
compatible = "generic-ohci";
|
|
reg = <0x0 0xff140000 0x0 0x40000>;
|
|
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru HCLK_USBHOST>,
|
|
<&cru HCLK_USBHOST_ARB>,
|
|
<&usb2phy>;
|
|
clock-names = "usbhost", "arbiter", "utmi";
|
|
phys = <&u2phy_host>;
|
|
phy-names = "usb2-phy";
|
|
status = "disabled";
|
|
};
|
|
|
|
debug: debug@ff190000 {
|
|
compatible = "rockchip,debug";
|
|
reg = <0x0 0xff190000 0x0 0x1000>,
|
|
<0x0 0xff192000 0x0 0x1000>,
|
|
<0x0 0xff194000 0x0 0x1000>,
|
|
<0x0 0xff196000 0x0 0x1000>;
|
|
};
|
|
|
|
qos_crypto_a: qos@ff200000 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xff200000 0x0 0x20>;
|
|
};
|
|
|
|
qos_crypto_p: qos@ff200080 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xff200080 0x0 0x20>;
|
|
};
|
|
|
|
qos_dcf: qos@ff200100 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xff200100 0x0 0x20>;
|
|
};
|
|
|
|
qos_dft2apb: qos@ff200200 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xff200200 0x0 0x20>;
|
|
};
|
|
|
|
qos_dma2ddr: qos@ff200280 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xff200280 0x0 0x20>;
|
|
};
|
|
|
|
qos_dmac: qos@ff200300 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xff200300 0x0 0x20>;
|
|
};
|
|
|
|
qos_keyreader: qos@ff200380 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xff200380 0x0 0x20>;
|
|
};
|
|
|
|
qos_cpu: qos@ff210000 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xff210000 0x0 0x20>;
|
|
};
|
|
|
|
qos_debug: qos@ff210080 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xff210080 0x0 0x20>;
|
|
};
|
|
|
|
qos_gpu_m0: qos@ff220000 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xff220000 0x0 0x20>;
|
|
};
|
|
|
|
qos_gpu_m1: qos@ff220080 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xff220080 0x0 0x20>;
|
|
};
|
|
|
|
qos_pmu_mcu: qos@ff240000 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xff240000 0x0 0x20>;
|
|
};
|
|
|
|
qos_rkvdec: qos@ff250000 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xff250000 0x0 0x20>;
|
|
};
|
|
|
|
qos_rkvenc: qos@ff260000 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xff260000 0x0 0x20>;
|
|
};
|
|
|
|
qos_gmac0: qos@ff270000 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xff270000 0x0 0x20>;
|
|
};
|
|
|
|
qos_hdcp: qos@ff270080 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xff270080 0x0 0x20>;
|
|
};
|
|
|
|
qos_jpegdec: qos@ff270100 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xff270100 0x0 0x20>;
|
|
};
|
|
|
|
qos_rga2_m0ro: qos@ff270200 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xff270200 0x0 0x20>;
|
|
};
|
|
|
|
qos_rga2_m0wo: qos@ff270280 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xff270280 0x0 0x20>;
|
|
};
|
|
|
|
qos_sdmmc0: qos@ff270300 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xff270300 0x0 0x20>;
|
|
};
|
|
|
|
qos_usb2host: qos@ff270380 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xff270380 0x0 0x20>;
|
|
};
|
|
|
|
qos_vdpp: qos@ff270480 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xff270480 0x0 0x20>;
|
|
};
|
|
|
|
qos_vop: qos@ff270500 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xff270500 0x0 0x20>;
|
|
};
|
|
|
|
qos_emmc: qos@ff280000 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xff280000 0x0 0x20>;
|
|
};
|
|
|
|
qos_fspi: qos@ff280080 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xff280080 0x0 0x20>;
|
|
};
|
|
|
|
qos_gmac1: qos@ff280100 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xff280100 0x0 0x20>;
|
|
};
|
|
|
|
qos_pcie: qos@ff280180 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xff280180 0x0 0x20>;
|
|
};
|
|
|
|
qos_sdio0: qos@ff280200 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xff280200 0x0 0x20>;
|
|
};
|
|
|
|
qos_sdio1: qos@ff280280 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xff280280 0x0 0x20>;
|
|
};
|
|
|
|
qos_tsp: qos@ff280300 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xff280300 0x0 0x20>;
|
|
};
|
|
|
|
qos_usb3otg: qos@ff280380 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xff280380 0x0 0x20>;
|
|
};
|
|
|
|
qos_vpu: qos@ff280400 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xff280400 0x0 0x20>;
|
|
};
|
|
|
|
/*
|
|
* Merge all GRF, each independent GRF offset is shown as bellow:
|
|
* CORE_GRF: 0xff300000
|
|
* GPU_GRF: 0xff310000
|
|
* RKVENC_GRF: 0xff320000
|
|
* DDR_GRF: 0xff330000
|
|
* VPU_GRF: 0xff340000
|
|
* COMBO_PIPE_PHY_GRF: 0xff348000
|
|
* RKVDEC_GRF: 0xff350000
|
|
* VO_GRF: 0xff360000
|
|
* PMU_GRF: 0xff370000
|
|
* SYS_GRF: 0xff380000
|
|
*/
|
|
grf: syscon@ff300000 {
|
|
compatible = "rockchip,rk3528-grf", "syscon", "simple-mfd";
|
|
reg = <0x0 0xff300000 0x0 0x90000>;
|
|
|
|
grf_cru: grf-clock-controller {
|
|
compatible = "rockchip,rk3528-grf-cru";
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
reboot_mode: reboot-mode {
|
|
compatible = "syscon-reboot-mode";
|
|
offset = <0x70200>;
|
|
mode-bootloader = <BOOT_BL_DOWNLOAD>;
|
|
mode-charge = <BOOT_CHARGING>;
|
|
mode-fastboot = <BOOT_FASTBOOT>;
|
|
mode-loader = <BOOT_BL_DOWNLOAD>;
|
|
mode-normal = <BOOT_NORMAL>;
|
|
mode-recovery = <BOOT_RECOVERY>;
|
|
mode-ums = <BOOT_UMS>;
|
|
mode-panic = <BOOT_PANIC>;
|
|
mode-watchdog = <BOOT_WATCHDOG>;
|
|
};
|
|
};
|
|
|
|
cru: clock-controller@ff4a0000 {
|
|
compatible = "rockchip,rk3528-cru";
|
|
reg = <0x0 0xff4a0000 0x0 0x30000>;
|
|
rockchip,grf = <&grf>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
|
|
assigned-clocks =
|
|
<&cru XIN_OSC0_DIV>,
|
|
<&cru PLL_GPLL>,
|
|
<&cru PLL_PPLL>,
|
|
<&cru PLL_CPLL>,
|
|
<&cru CLK_MATRIX_250M_SRC>,
|
|
<&cru CLK_MATRIX_500M_SRC>,
|
|
<&cru CLK_MATRIX_50M_SRC>,
|
|
<&cru CLK_MATRIX_100M_SRC>,
|
|
<&cru CLK_MATRIX_150M_SRC>,
|
|
<&cru CLK_MATRIX_200M_SRC>,
|
|
<&cru CLK_MATRIX_300M_SRC>,
|
|
<&cru CLK_MATRIX_339M_SRC>,
|
|
<&cru CLK_MATRIX_400M_SRC>,
|
|
<&cru CLK_MATRIX_600M_SRC>,
|
|
<&cru CLK_PPLL_50M_MATRIX>,
|
|
<&cru CLK_PPLL_100M_MATRIX>,
|
|
<&cru CLK_PPLL_125M_MATRIX>,
|
|
<&cru ACLK_BUS_VOPGL_ROOT>,
|
|
<&cru ACLK_VO_ROOT>,
|
|
<&cru ACLK_VPU_ROOT>,
|
|
<&cru ACLK_VPU_L_ROOT>;
|
|
|
|
assigned-clock-rates =
|
|
<32768>,
|
|
<1188000000>,
|
|
<1000000000>,
|
|
<996000000>,
|
|
<250000000>,
|
|
<500000000>,
|
|
<50000000>,
|
|
<100000000>,
|
|
<150000000>,
|
|
<200000000>,
|
|
<300000000>,
|
|
<340000000>,
|
|
<400000000>,
|
|
<600000000>,
|
|
<50000000>,
|
|
<100000000>,
|
|
<125000000>,
|
|
<500000000>,
|
|
<340000000>,
|
|
<300000000>,
|
|
<200000000>;
|
|
};
|
|
|
|
ioc_grf: syscon@ff540000 {
|
|
compatible = "rockchip,rk3528-ioc-grf", "syscon";
|
|
reg = <0x0 0xff540000 0x0 0x40000>;
|
|
};
|
|
|
|
pmu: power-management@ff600000 {
|
|
compatible = "rockchip,rk3528-pmu", "syscon", "simple-mfd";
|
|
reg = <0x0 0xff600000 0x0 0x2000>;
|
|
|
|
power: power-controller {
|
|
compatible = "rockchip,rk3528-power-controller";
|
|
#power-domain-cells = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "okay";
|
|
|
|
/* These power domains are grouped by VD_GPU */
|
|
pd_gpu@RK3528_PD_GPU {
|
|
reg = <RK3528_PD_GPU>;
|
|
clocks = <&cru ACLK_GPU_MALI>,
|
|
<&cru PCLK_GPU_ROOT>;
|
|
pm_qos = <&qos_gpu_m0>,
|
|
<&qos_gpu_m1>;
|
|
};
|
|
/* These power domains are grouped by VD_LOGIC */
|
|
pd_rkvdec@RK3528_PD_RKVDEC {
|
|
reg = <RK3528_PD_RKVDEC>;
|
|
};
|
|
pd_rkvenc@RK3528_PD_RKVENC {
|
|
reg = <RK3528_PD_RKVENC>;
|
|
};
|
|
pd_vo@RK3528_PD_VO {
|
|
reg = <RK3528_PD_VO>;
|
|
};
|
|
pd_vpu@RK3528_PD_VPU {
|
|
reg = <RK3528_PD_VPU>;
|
|
};
|
|
};
|
|
};
|
|
|
|
mailbox: mailbox@ff630000 {
|
|
compatible = "rockchip,rk3528-mailbox",
|
|
"rockchip,rk3368-mailbox";
|
|
reg = <0x0 0xff630000 0x0 0x200>;
|
|
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_PMU_MAILBOX>;
|
|
clock-names = "pclk_mailbox";
|
|
#mbox-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
gpu: gpu@ff700000 {
|
|
compatible = "arm,mali-450";
|
|
reg = <0x0 0xff700000 0x0 0x40000>;
|
|
|
|
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "Mali_GP_IRQ",
|
|
"Mali_GP_MMU_IRQ",
|
|
"IRQPP",
|
|
"Mali_PP0_IRQ",
|
|
"Mali_PP0_MMU_IRQ",
|
|
"Mali_PP1_IRQ",
|
|
"Mali_PP1_MMU_IRQ";
|
|
clocks = <&scmi_clk SCMI_CLK_GPU>, <&cru ACLK_GPU_MALI>,
|
|
<&cru PCLK_GPU_ROOT>;
|
|
clock-names = "clk_mali", "aclk_gpu_mali", "pclk_gpu";
|
|
assigned-clocks = <&scmi_clk SCMI_CLK_GPU>;
|
|
assigned-clock-rates = <300000000>;
|
|
power-domains = <&power RK3528_PD_GPU>;
|
|
operating-points-v2 = <&gpu_opp_table>;
|
|
#cooling-cells = <2>;
|
|
rockchip,grf = <&grf>;
|
|
status = "disabled";
|
|
|
|
gpu_power_model: power-model {
|
|
compatible = "simple-power-model";
|
|
leakage-range= <1 3>;
|
|
ls = <(-15658) 67354 0>;
|
|
static-coefficient = <10000>;
|
|
dynamic-coefficient = <724>;
|
|
ts = <3156546 120154 (-2506) 39>;
|
|
thermal-zone = "soc-thermal";
|
|
};
|
|
};
|
|
|
|
gpu_opp_table: gpu-opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
mbist-vmin = <825000 925000>;
|
|
nvmem-cells = <&gpu_leakage>, <&gpu_opp_info>, <&gpu_mbist_vmin>;
|
|
nvmem-cell-names = "leakage", "opp-info", "mbist-vmin";
|
|
|
|
rockchip,pvtm-voltage-sel = <
|
|
0 750 0
|
|
751 770 1
|
|
771 790 2
|
|
791 810 3
|
|
811 830 4
|
|
831 850 5
|
|
851 870 6
|
|
871 890 7
|
|
891 9999 8
|
|
>;
|
|
rockchip,pvtm-pvtpll;
|
|
rockchip,pvtm-offset = <0x10018>;
|
|
rockchip,pvtm-sample-time = <1100>;
|
|
rockchip,pvtm-freq = <800000>;
|
|
rockchip,pvtm-volt = <900000>;
|
|
rockchip,pvtm-ref-temp = <40>;
|
|
rockchip,pvtm-temp-prop = <0 0>;
|
|
rockchip,pvtm-thermal-zone = "soc-thermal";
|
|
rockchip,grf = <&grf>;
|
|
|
|
opp-300000000 {
|
|
opp-hz = /bits/ 64 <300000000>;
|
|
opp-microvolt = <875000 875000 1000000>;
|
|
opp-microvolt-L5 = <850000 850000 1000000>;
|
|
opp-microvolt-L6 = <837500 837500 1000000>;
|
|
opp-microvolt-L7 = <825000 825000 1000000>;
|
|
opp-microvolt-L8 = <825000 825000 1000000>;
|
|
};
|
|
opp-500000000 {
|
|
opp-hz = /bits/ 64 <500000000>;
|
|
opp-microvolt = <875000 875000 1000000>;
|
|
opp-microvolt-L5 = <850000 850000 1000000>;
|
|
opp-microvolt-L6 = <837500 837500 1000000>;
|
|
opp-microvolt-L7 = <825000 825000 1000000>;
|
|
opp-microvolt-L8 = <825000 825000 1000000>;
|
|
};
|
|
opp-600000000 {
|
|
opp-hz = /bits/ 64 <600000000>;
|
|
opp-microvolt = <875000 875000 1000000>;
|
|
opp-microvolt-L5 = <850000 850000 1000000>;
|
|
opp-microvolt-L6 = <837500 837500 1000000>;
|
|
opp-microvolt-L7 = <825000 825000 1000000>;
|
|
opp-microvolt-L8 = <825000 825000 1000000>;
|
|
};
|
|
opp-700000000 {
|
|
opp-hz = /bits/ 64 <700000000>;
|
|
opp-microvolt = <900000 900000 1000000>;
|
|
opp-microvolt-L1 = <887500 887500 1000000>;
|
|
opp-microvolt-L2 = <875000 875000 1000000>;
|
|
opp-microvolt-L3 = <875000 875000 1000000>;
|
|
opp-microvolt-L4 = <875000 875000 1000000>;
|
|
opp-microvolt-L5 = <850000 850000 1000000>;
|
|
opp-microvolt-L6 = <837500 837500 1000000>;
|
|
opp-microvolt-L7 = <825000 825000 1000000>;
|
|
opp-microvolt-L8 = <825000 825000 1000000>;
|
|
clock-latency-ns = <40000>;
|
|
};
|
|
opp-800000000 {
|
|
opp-hz = /bits/ 64 <800000000>;
|
|
opp-microvolt = <950000 950000 1000000>;
|
|
opp-microvolt-L1 = <937500 937500 1000000>;
|
|
opp-microvolt-L2 = <925000 925000 1000000>;
|
|
opp-microvolt-L3 = <912500 912500 1000000>;
|
|
opp-microvolt-L4 = <900000 900000 1000000>;
|
|
opp-microvolt-L5 = <887500 887500 1000000>;
|
|
opp-microvolt-L6 = <875000 875000 1000000>;
|
|
opp-microvolt-L7 = <862500 862500 1000000>;
|
|
opp-microvolt-L8 = <850000 850000 1000000>;
|
|
clock-latency-ns = <40000>;
|
|
};
|
|
};
|
|
|
|
gpu_bus: gpu-bus {
|
|
compatible = "rockchip,rk3528-bus";
|
|
rockchip,busfreq-policy = "clkfreq";
|
|
clocks = <&scmi_clk SCMI_CLK_GPU>;
|
|
clock-names = "bus";
|
|
operating-points-v2 = <&gpu_bus_opp_table>;
|
|
status = "disabled";
|
|
};
|
|
|
|
gpu_bus_opp_table: gpu-bus-opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
nvmem-cells = <&log_leakage>;
|
|
nvmem-cell-names = "leakage";
|
|
|
|
rockchip,leakage-voltage-sel = <
|
|
1 22 0
|
|
23 254 1
|
|
>;
|
|
|
|
opp-700000000 {
|
|
opp-hz = /bits/ 64 <700000000>;
|
|
opp-microvolt = <850000 850000 1000000>;
|
|
};
|
|
opp-800000000 {
|
|
opp-hz = /bits/ 64 <800000000>;
|
|
opp-microvolt = <875000 875000 1000000>;
|
|
opp-microvolt-L1 = <850000 850000 1000000>;
|
|
};
|
|
};
|
|
|
|
rkvdec: rkvdec@ff740100 {
|
|
compatible = "rockchip,rkv-decoder-rk3528", "rockchip,rkv-decoder-v2";
|
|
reg = <0x0 0xff740100 0x0 0x400>, <0x0 0xff740000 0x0 0x100>;
|
|
reg-names = "regs", "link";
|
|
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "irq_dec";
|
|
clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, <&cru CLK_HEVC_CA_RKVDEC>;
|
|
clock-names = "aclk_vcodec", "hclk_vcodec","clk_hevc_cabac";
|
|
rockchip,normal-rates = <340000000>, <0>, <600000000>;
|
|
assigned-clocks = <&cru ACLK_RKVDEC>, <&cru CLK_HEVC_CA_RKVDEC>;
|
|
assigned-clock-rates = <340000000>, <600000000>;
|
|
resets = <&cru SRST_ARESETN_RKVDEC>, <&cru SRST_HRESETN_RKVDEC>,
|
|
<&cru SRST_RESETN_HEVC_CA_RKVDEC>;
|
|
reset-names = "video_a", "video_h", "video_hevc_cabac";
|
|
iommus = <&rkvdec_mmu>;
|
|
rockchip,srv = <&mpp_srv>;
|
|
rockchip,taskqueue-node = <0>;
|
|
rockchip,resetgroup-node = <0>;
|
|
rockchip,task-capacity = <16>;
|
|
rockchip,sram = <&rkvdec_sram>;
|
|
/* rcb_iova: start and size */
|
|
rockchip,rcb-iova = <0x10000000 65536>;
|
|
rockchip,rcb-min-width = <512>;
|
|
status = "disabled";
|
|
};
|
|
|
|
rkvdec_mmu: iommu@ff740800 {
|
|
compatible = "rockchip,iommu-v2";
|
|
reg = <0x0 0xff740800 0x0 0x40>, <0x0 0xff740900 0x0 0x40>;
|
|
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "rkvdec_mmu";
|
|
clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, <&cru CLK_HEVC_CA_RKVDEC>;
|
|
clock-names = "aclk", "iface", "clk_hevc_cabac";
|
|
#iommu-cells = <0>;
|
|
rockchip,shootdown-entire;
|
|
status = "disabled";
|
|
};
|
|
|
|
rkvenc: rkvenc@ff780000 {
|
|
compatible = "rockchip,rkv-encoder-rk3528", "rockchip,rkv-encoder-v2";
|
|
reg = <0x0 0xff780000 0x0 0x6000>;
|
|
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "irq_rkvenc";
|
|
clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>, <&cru CLK_CORE_RKVENC>;
|
|
clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
|
|
rockchip,normal-rates = <300000000>, <0>, <300000000>;
|
|
resets = <&cru SRST_ARESETN_RKVENC>, <&cru SRST_HRESETN_RKVENC>,
|
|
<&cru SRST_RESETN_CORE_RKVENC>;
|
|
reset-names = "video_a", "video_h", "video_core";
|
|
assigned-clocks = <&cru ACLK_RKVENC>, <&cru CLK_CORE_RKVENC>;
|
|
assigned-clock-rates = <300000000>, <300000000>;
|
|
iommus = <&rkvenc_mmu>;
|
|
rockchip,srv = <&mpp_srv>;
|
|
rockchip,grf = <&grf>;
|
|
rockchip,grf-mem-offset = <0x20010>;
|
|
rockchip,grf-mem-values = <0x00000021>, <0xffff0021>;
|
|
rockchip,taskqueue-node = <1>;
|
|
rockchip,resetgroup-node = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
rkvenc_mmu: iommu@ff78f000 {
|
|
compatible = "rockchip,iommu-v2";
|
|
reg = <0x0 0xff78f000 0x0 0x40>;
|
|
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "rkvenc_mmu";
|
|
clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>;
|
|
clock-names = "aclk", "iface";
|
|
#iommu-cells = <0>;
|
|
rockchip,shootdown-entire;
|
|
status = "disabled";
|
|
};
|
|
|
|
vdpu: vdpu@ff7c0400 {
|
|
compatible = "rockchip,vpu-decoder-v2";
|
|
reg = <0x0 0xff7c0400 0x0 0x400>;
|
|
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "irq_dec";
|
|
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
|
|
clock-names = "aclk_vcodec", "hclk_vcodec";
|
|
rockchip,normal-rates = <300000000>, <0>;
|
|
assigned-clocks = <&cru ACLK_VPU>;
|
|
assigned-clock-rates = <300000000>;
|
|
resets = <&cru SRST_ARESETN_VPU>, <&cru SRST_HRESETN_VPU>;
|
|
reset-names = "shared_video_a", "shared_video_h";
|
|
iommus = <&vdpu_mmu>;
|
|
rockchip,srv = <&mpp_srv>;
|
|
rockchip,grf = <&grf>;
|
|
rockchip,grf-mem-offset = <0x40034>;
|
|
rockchip,grf-mem-values = <0x0f040000>, <0x0f040f04>;
|
|
rockchip,taskqueue-node = <2>;
|
|
rockchip,resetgroup-node = <2>;
|
|
rockchip,disable-auto-freq;
|
|
status = "disabled";
|
|
};
|
|
|
|
vdpu_mmu: iommu@ff7c0800 {
|
|
compatible = "rockchip,iommu-v2";
|
|
reg = <0x0 0xff7c0800 0x0 0x40>;
|
|
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "vdpu_mmu";
|
|
clock-names = "aclk", "iface";
|
|
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
|
|
#iommu-cells = <0>;
|
|
rockchip,shootdown-entire;
|
|
status = "disabled";
|
|
};
|
|
|
|
avsd: avsd_plus@ff7c1000 {
|
|
compatible = "rockchip,avs-plus-decoder";
|
|
reg = <0x0 0xff7c1000 0x0 0x200>;
|
|
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "irq_dec";
|
|
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
|
|
clock-names = "aclk_vcodec", "hclk_vcodec";
|
|
rockchip,normal-rates = <300000000>, <0>;
|
|
assigned-clocks = <&cru ACLK_VPU>;
|
|
assigned-clock-rates = <300000000>;
|
|
resets = <&cru SRST_ARESETN_VPU>, <&cru SRST_HRESETN_VPU>;
|
|
reset-names = "shared_video_a", "shared_video_h";
|
|
iommus = <&vdpu_mmu>;
|
|
rockchip,srv = <&mpp_srv>;
|
|
rockchip,taskqueue-node = <2>;
|
|
rockchip,resetgroup-node = <2>;
|
|
rockchip,disable-auto-freq;
|
|
status = "disabled";
|
|
};
|
|
|
|
vop: vop@ff840000 {
|
|
compatible = "rockchip,rk3528-vop";
|
|
reg = <0x0 0xff840000 0x0 0x3000>,
|
|
<0x0 0xff845000 0x0 0x1000>,
|
|
<0x0 0xff846400 0x0 0x800>;
|
|
reg-names = "regs",
|
|
"gamma_lut",
|
|
"acm_regs";
|
|
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru ACLK_VOP>,
|
|
<&cru HCLK_VOP>,
|
|
<&cru DCLK_VOP0>,
|
|
<&cru DCLK_VOP1>;
|
|
clock-names = "aclk_vop",
|
|
"hclk_vop",
|
|
"dclk_vp0",
|
|
"dclk_vp1";
|
|
assigned-clocks = <&cru DCLK_VOP0>;
|
|
assigned-clock-parents = <&inno_hdmiphy_clk>;
|
|
iommus = <&vop_mmu>;
|
|
rockchip,grf = <&grf>;
|
|
status = "disabled";
|
|
|
|
vop_out: ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0>;
|
|
|
|
vp0_out_hdmi: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&hdmi_in_vp0>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <1>;
|
|
|
|
vp1_out_tve: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&tve_in_vp1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
vop_mmu: iommu@ff847e00 {
|
|
compatible = "rockchip,iommu-v2";
|
|
reg = <0x0 0xff847e00 0x0 0x100>;
|
|
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "vop_mmu";
|
|
clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
|
|
clock-names = "aclk", "iface";
|
|
#iommu-cells = <0>;
|
|
rockchip,disable-device-link-resume;
|
|
rockchip,shootdown-entire;
|
|
status = "disabled";
|
|
};
|
|
|
|
rga2: rga@ff850000 {
|
|
compatible = "rockchip,rga2_core0";
|
|
reg = <0x0 0xff850000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "rga2_irq";
|
|
clocks = <&cru ACLK_RGA2E>, <&cru HCLK_RGA2E>, <&cru CLK_CORE_RGA2E>;
|
|
clock-names = "aclk_rga2", "hclk_rga2", "clk_rga2";
|
|
iommus = <&rga2_mmu>;
|
|
rockchip,grf = <&grf>;
|
|
rockchip,grf-offset = <0x600e0>;
|
|
rockchip,grf-values = <0x0ff10000>, <0x0ff10ff1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
rga2_mmu: iommu@ff850f00 {
|
|
compatible = "rockchip,iommu-v2";
|
|
reg = <0x0 0xff850f00 0x0 0x100>;
|
|
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "rga2_mmu";
|
|
clocks = <&cru ACLK_RGA2E>, <&cru HCLK_RGA2E>;
|
|
clock-names = "aclk", "iface";
|
|
#iommu-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
iep: iep@ff860000 {
|
|
compatible = "rockchip,iep-v2";
|
|
reg = <0x0 0xff860000 0x0 0x500>;
|
|
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru ACLK_VDPP>, <&cru HCLK_VDPP>, <&cru CLK_CORE_VDPP>;
|
|
clock-names = "aclk", "hclk", "sclk";
|
|
rockchip,normal-rates = <340000000>, <0>, <340000000>;
|
|
assigned-clocks = <&cru ACLK_VDPP>, <&cru CLK_CORE_VDPP>;
|
|
assigned-clock-rates = <340000000>, <340000000>;
|
|
resets = <&cru SRST_ARESETN_VDPP>, <&cru SRST_HRESETN_VDPP>,
|
|
<&cru SRST_RESETN_CORE_VDPP>;
|
|
reset-names = "shared_rst_a", "shared_rst_h", "shared_rst_s";
|
|
rockchip,srv = <&mpp_srv>;
|
|
rockchip,taskqueue-node = <3>;
|
|
rockchip,resetgroup-node = <3>;
|
|
iommus = <&iep_mmu>;
|
|
status = "disabled";
|
|
};
|
|
|
|
iep_mmu: iommu@ff860800 {
|
|
compatible = "rockchip,iommu-v2";
|
|
reg = <0x0 0xff860800 0x0 0x100>;
|
|
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "iep_mmu";
|
|
clocks = <&cru ACLK_VDPP>, <&cru HCLK_VDPP>;
|
|
clock-names = "aclk", "iface";
|
|
#iommu-cells = <0>;
|
|
rockchip,shootdown-entire;
|
|
status = "disabled";
|
|
};
|
|
|
|
vdpp: vdpp@ff861000 {
|
|
compatible = "rockchip,vdpp-v1";
|
|
reg = <0x0 0xff861000 0x0 0x100>, <0x0 0xff862000 0x0 0x900>;
|
|
reg-names = "vdpp_regs", "zme_regs";
|
|
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru ACLK_VDPP>, <&cru HCLK_VDPP>, <&cru CLK_CORE_VDPP>;
|
|
clock-names = "aclk", "hclk", "sclk";
|
|
rockchip,normal-rates = <340000000>, <0>, <340000000>;
|
|
assigned-clocks = <&cru ACLK_VDPP>, <&cru CLK_CORE_VDPP>;
|
|
assigned-clock-rates = <340000000>, <340000000>;
|
|
resets = <&cru SRST_ARESETN_VDPP>, <&cru SRST_HRESETN_VDPP>,
|
|
<&cru SRST_RESETN_CORE_VDPP>;
|
|
reset-names = "shared_rst_a", "shared_rst_h", "shared_rst_s";
|
|
rockchip,srv = <&mpp_srv>;
|
|
rockchip,grf = <&grf>;
|
|
rockchip,grf-mem-offset = <0x600e0>;
|
|
rockchip,grf-mem-values = <0xf0040000>, <0xf004f004>;
|
|
rockchip,taskqueue-node = <3>;
|
|
rockchip,resetgroup-node = <3>;
|
|
rockchip,disable-auto-freq;
|
|
iommus = <&iep_mmu>;
|
|
status = "disabled";
|
|
};
|
|
|
|
jpegd: jpegd@ff870000 {
|
|
compatible = "rockchip,rkv-jpeg-decoder-v1";
|
|
reg = <0x0 0xff870000 0x0 0x400>;
|
|
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru ACLK_JPEG_DECODER>, <&cru HCLK_JPEG_DECODER>;
|
|
clock-names = "aclk_vcodec", "hclk_vcodec";
|
|
rockchip,normal-rates = <340000000>, <0>;
|
|
assigned-clocks = <&cru ACLK_JPEG_DECODER>;
|
|
assigned-clock-rates = <340000000>;
|
|
rockchip,disable-auto-freq;
|
|
resets = <&cru SRST_ARESETN_JPEG_DECODER>, <&cru SRST_HRESETN_JPEG_DECODER>;
|
|
reset-names = "video_a", "video_h";
|
|
iommus = <&jpegd_mmu>;
|
|
rockchip,srv = <&mpp_srv>;
|
|
rockchip,taskqueue-node = <4>;
|
|
rockchip,resetgroup-node = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
jpegd_mmu: iommu@ff870480 {
|
|
compatible = "rockchip,iommu-v2";
|
|
reg = <0x0 0xff870480 0x0 0x40>;
|
|
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "jpegd_mmu";
|
|
clock-names = "aclk", "iface";
|
|
clocks = <&cru ACLK_JPEG_DECODER>, <&cru HCLK_JPEG_DECODER>;
|
|
#iommu-cells = <0>;
|
|
rockchip,shootdown-entire;
|
|
status = "disabled";
|
|
};
|
|
|
|
tve: tve@ff880000 {
|
|
compatible = "rockchip,rk3528-tve";
|
|
reg = <0x0 0xff880000 0x0 0x4000>,
|
|
<0x0 0xffde0000 0x0 0x300>;
|
|
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru HCLK_CVBS>,
|
|
<&cru PCLK_VCDCPHY>,
|
|
<&cru DCLK_CVBS>,
|
|
<&cru DCLK_4X_CVBS>;
|
|
clock-names = "hclk",
|
|
"pclk_vdac",
|
|
"dclk",
|
|
"dclk_4x";
|
|
rockchip,lumafilter0 = <0x0ff80006>;
|
|
rockchip,lumafilter1 = <0x00090010>;
|
|
rockchip,lumafilter2 = <0x0ffb0fd8>;
|
|
rockchip,lumafilter3 = <0x00080057>;
|
|
rockchip,lumafilter4 = <0x0fef0f64>;
|
|
rockchip,lumafilter5 = <0x0016010a>;
|
|
rockchip,lumafilter6 = <0x0f830df7>;
|
|
rockchip,lumafilter7 = <0x08de055f>;
|
|
rockchip,tve-upsample = <DCLK_UPSAMPLEx4>;
|
|
rockchip,grf = <&grf>;
|
|
nvmem-cells = <&vdac_out_current>, <&test_version>;
|
|
nvmem-cell-names = "out-current", "version";
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
tve_in_vp1: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&vp1_out_tve>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
hdcp2: hdcp2@ff8c0000 {
|
|
compatible = "rockchip,rk3528-hdmi-hdcp2";
|
|
reg = <0x0 0xff8c0000 0x0 0x2000>;
|
|
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru ACLK_HDCP>, <&cru PCLK_HDCP>,
|
|
<&cru HCLK_HDCP>;
|
|
clock-names ="aclk_hdcp2", "pclk_hdcp2", "hdcp2_clk_hdmi";
|
|
status = "disabled";
|
|
};
|
|
|
|
hdmi: hdmi@ff8d0000 {
|
|
compatible = "rockchip,rk3528-dw-hdmi";
|
|
reg = <0x0 0xff8d0000 0x0 0x20000>,
|
|
<0x0 0xff610000 0x0 0x200>;
|
|
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "hdmi", "hdmi_wakeup";
|
|
clocks = <&cru PCLK_HDMI>,
|
|
<&cru CLK_SFR_HDMI>,
|
|
<&cru CLK_CEC_HDMI>,
|
|
<&inno_hdmiphy_clk>;
|
|
clock-names = "iahb", "isfr", "cec", "dclk_vp0";
|
|
ddc-i2c-scl-high-time-ns = <9625>;
|
|
ddc-i2c-scl-low-time-ns = <10000>;
|
|
reg-io-width = <4>;
|
|
rockchip,grf = <&grf>;
|
|
pinctrl-names = "default", "idle";
|
|
pinctrl-0 = <&hdmi_pins>;
|
|
pinctrl-1 = <&hdmi_pins_idle>;
|
|
phys = <&hdmiphy>;
|
|
phy-names = "hdmi";
|
|
#sound-dai-cells = <0>;
|
|
hpd-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
hdmi_in_vp0: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&vp0_out_hdmi>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
dfi: dfi@ff930000 {
|
|
reg = <0x0 0xff930000 0x0 0x400>;
|
|
compatible = "rockchip,rk3528-dfi";
|
|
rockchip,grf = <&grf>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi0: spi@ff9c0000 {
|
|
compatible = "rockchip,rk3066-spi";
|
|
reg = <0x0 0xff9c0000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>, <&cru SCLK_IN_SPI0>;
|
|
clock-names = "spiclk", "apb_pclk", "sclk_in";
|
|
dmas = <&dmac 25>, <&dmac 24>;
|
|
dma-names = "tx", "rx";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi0_csn0 &spi0_csn1 &spi0_pins>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi1: spi@ff9d0000 {
|
|
compatible = "rockchip,rk3066-spi";
|
|
reg = <0x0 0xff9d0000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>, <&cru SCLK_IN_SPI1>;
|
|
clock-names = "spiclk", "apb_pclk", "sclk_in";
|
|
dmas = <&dmac 31>, <&dmac 30>;
|
|
dma-names = "tx", "rx";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi1_csn0 &spi1_csn1 &spi1_pins>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart0: serial@ff9f0000 {
|
|
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
|
|
reg = <0x0 0xff9f0000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
dmas = <&dmac 9>, <&dmac 8>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@ff9f8000 {
|
|
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
|
|
reg = <0x0 0xff9f8000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
dmas = <&dmac 11>, <&dmac 10>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@ffa00000 {
|
|
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
|
|
reg = <0x0 0xffa00000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
dmas = <&dmac 13>, <&dmac 12>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@ffa08000 {
|
|
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
|
|
reg = <0x0 0xffa08000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
dmas = <&dmac 15>, <&dmac 14>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart4: serial@ffa10000 {
|
|
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
|
|
reg = <0x0 0xffa10000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
dmas = <&dmac 17>, <&dmac 16>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart5: serial@ffa18000 {
|
|
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
|
|
reg = <0x0 0xffa18000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
dmas = <&dmac 19>, <&dmac 18>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart6: serial@ffa20000 {
|
|
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
|
|
reg = <0x0 0xffa20000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
dmas = <&dmac 21>, <&dmac 20>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart7: serial@ffa28000 {
|
|
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
|
|
reg = <0x0 0xffa28000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
dmas = <&dmac 23>, <&dmac 22>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c0: i2c@ffa50000 {
|
|
compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c";
|
|
reg = <0x0 0xffa50000 0x0 0x1000>;
|
|
clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
|
|
clock-names = "i2c", "pclk";
|
|
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c0m0_xfer>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@ffa58000 {
|
|
compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c";
|
|
reg = <0x0 0xffa58000 0x0 0x1000>;
|
|
clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
|
|
clock-names = "i2c", "pclk";
|
|
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c1m0_xfer>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@ffa60000 {
|
|
compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c";
|
|
reg = <0x0 0xffa60000 0x0 0x1000>;
|
|
clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
|
|
clock-names = "i2c", "pclk";
|
|
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c2m0_xfer>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c3: i2c@ffa68000 {
|
|
compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c";
|
|
reg = <0x0 0xffa68000 0x0 0x1000>;
|
|
clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
|
|
clock-names = "i2c", "pclk";
|
|
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c3m0_xfer>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c4: i2c@ffa70000 {
|
|
compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c";
|
|
reg = <0x0 0xffa70000 0x0 0x1000>;
|
|
clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
|
|
clock-names = "i2c", "pclk";
|
|
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c4_xfer>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c5: i2c@ffa78000 {
|
|
compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c";
|
|
reg = <0x0 0xffa78000 0x0 0x1000>;
|
|
clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
|
|
clock-names = "i2c", "pclk";
|
|
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c5m0_xfer>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c6: i2c@ffa80000 {
|
|
compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c";
|
|
reg = <0x0 0xffa80000 0x0 0x1000>;
|
|
clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>;
|
|
clock-names = "i2c", "pclk";
|
|
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c6m0_xfer>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c7: i2c@ffa88000 {
|
|
compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c";
|
|
reg = <0x0 0xffa88000 0x0 0x1000>;
|
|
clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>;
|
|
clock-names = "i2c", "pclk";
|
|
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c7_xfer>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm0: pwm@ffa90000 {
|
|
compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm";
|
|
reg = <0x0 0xffa90000 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
pinctrl-names = "active";
|
|
pinctrl-0 = <&pwm0m0_pins>;
|
|
clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
|
|
clock-names = "pwm", "pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm1: pwm@ffa90010 {
|
|
compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm";
|
|
reg = <0x0 0xffa90010 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
pinctrl-names = "active";
|
|
pinctrl-0 = <&pwm1m0_pins>;
|
|
clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
|
|
clock-names = "pwm", "pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm2: pwm@ffa90020 {
|
|
compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm";
|
|
reg = <0x0 0xffa90020 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
pinctrl-names = "active";
|
|
pinctrl-0 = <&pwm2m0_pins>;
|
|
clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
|
|
clock-names = "pwm", "pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm3: pwm@ffa90030 {
|
|
compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm";
|
|
reg = <0x0 0xffa90030 0x0 0x10>;
|
|
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
|
#pwm-cells = <3>;
|
|
pinctrl-names = "active";
|
|
pinctrl-0 = <&pwm3m0_pins>;
|
|
clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
|
|
clock-names = "pwm", "pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm4: pwm@ffa98000 {
|
|
compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm";
|
|
reg = <0x0 0xffa98000 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
pinctrl-names = "active";
|
|
pinctrl-0 = <&pwm4m0_pins>;
|
|
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
|
|
clock-names = "pwm", "pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm5: pwm@ffa98010 {
|
|
compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm";
|
|
reg = <0x0 0xffa98010 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
pinctrl-names = "active";
|
|
pinctrl-0 = <&pwm5m0_pins>;
|
|
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
|
|
clock-names = "pwm", "pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm6: pwm@ffa98020 {
|
|
compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm";
|
|
reg = <0x0 0xffa98020 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
pinctrl-names = "active";
|
|
pinctrl-0 = <&pwm6m0_pins>;
|
|
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
|
|
clock-names = "pwm", "pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm7: pwm@ffa98030 {
|
|
compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm";
|
|
reg = <0x0 0xffa98030 0x0 0x10>;
|
|
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
|
#pwm-cells = <3>;
|
|
pinctrl-names = "active";
|
|
pinctrl-0 = <&pwm7m0_pins>;
|
|
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
|
|
clock-names = "pwm", "pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
rktimer: timer@ffab0000 {
|
|
compatible = "rockchip,rk3528-timer", "rockchip,rk3288-timer";
|
|
reg = <0x0 0xffab0000 0x0 0x20>;
|
|
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>;
|
|
clock-names = "pclk", "timer";
|
|
};
|
|
|
|
wdt: watchdog@ffac0000 {
|
|
compatible = "snps,dw-wdt";
|
|
reg = <0x0 0xffac0000 0x0 0x100>;
|
|
clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>;
|
|
clock-names = "tclk", "pclk";
|
|
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tsadc: tsadc@ffad0000 {
|
|
compatible = "rockchip,rk3528-tsadc";
|
|
reg = <0x0 0xffad0000 0x0 0x400>;
|
|
rockchip,grf = <&grf>;
|
|
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>, <&cru PCLK_TSADC>;
|
|
clock-names = "tsadc", "tsadc_tsen", "apb_pclk";
|
|
assigned-clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>;
|
|
assigned-clock-rates = <1200000>, <12000000>;
|
|
resets = <&cru SRST_RESETN_TSADC>, <&cru SRST_PRESETN_TSADC>;
|
|
reset-names = "tsadc", "tsadc-apb";
|
|
#thermal-sensor-cells = <1>;
|
|
rockchip,hw-tshut-temp = <120000>;
|
|
rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
|
|
rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
|
|
nvmem-cells = <&cpu_tsadc_trim_l>, <&cpu_tsadc_trim_h>;
|
|
nvmem-cell-names = "trim_l", "trim_h";
|
|
status = "disabled";
|
|
};
|
|
|
|
saradc: saradc@ffae0000 {
|
|
compatible = "rockchip,rk3528-saradc";
|
|
reg = <0x0 0xffae0000 0x0 0x10000>;
|
|
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
|
#io-channel-cells = <1>;
|
|
clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
|
|
clock-names = "saradc", "apb_pclk";
|
|
resets = <&cru SRST_PRESETN_SARADC>;
|
|
reset-names = "saradc-apb";
|
|
status = "disabled";
|
|
};
|
|
|
|
sai3: sai@ffb70000 {
|
|
compatible = "rockchip,rk3528-sai", "rockchip,sai-v1";
|
|
reg = <0x0 0xffb70000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru MCLK_SAI_I2S3>, <&cru HCLK_SAI_I2S3>;
|
|
clock-names = "mclk", "hclk";
|
|
dmas = <&dmac 5>;
|
|
dma-names = "tx";
|
|
resets = <&cru SRST_MRESETN_SAI_I2S3>, <&cru SRST_HRESETN_SAI_I2S3>;
|
|
reset-names = "m", "h";
|
|
#sound-dai-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sai0: sai@ffb80000 {
|
|
compatible = "rockchip,rk3528-sai", "rockchip,sai-v1";
|
|
reg = <0x0 0xffb80000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru MCLK_SAI_I2S0>, <&cru HCLK_SAI_I2S0>;
|
|
clock-names = "mclk", "hclk";
|
|
dmas = <&dmac 1>, <&dmac 0>;
|
|
dma-names = "tx", "rx";
|
|
resets = <&cru SRST_MRESETN_SAI_I2S0>, <&cru SRST_HRESETN_SAI_I2S0>;
|
|
reset-names = "m", "h";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2s0m0_lrck
|
|
&i2s0m0_sclk
|
|
&i2s0m0_sdi
|
|
&i2s0m0_sdo>;
|
|
#sound-dai-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sai2: sai@ffb90000 {
|
|
compatible = "rockchip,rk3528-sai", "rockchip,sai-v1";
|
|
reg = <0x0 0xffb90000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru MCLK_SAI_I2S2>, <&cru HCLK_SAI_I2S2>;
|
|
clock-names = "mclk", "hclk";
|
|
dmas = <&dmac 4>;
|
|
dma-names = "tx";
|
|
resets = <&cru SRST_MRESETN_SAI_I2S2>, <&cru SRST_HRESETN_SAI_I2S2>;
|
|
reset-names = "m", "h";
|
|
#sound-dai-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sai1: sai@ffba0000 {
|
|
compatible = "rockchip,rk3528-sai", "rockchip,sai-v1";
|
|
reg = <0x0 0xffba0000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru MCLK_SAI_I2S1>, <&cru HCLK_SAI_I2S1>;
|
|
clock-names = "mclk", "hclk";
|
|
dmas = <&dmac 3>, <&dmac 2>;
|
|
dma-names = "tx", "rx";
|
|
resets = <&cru SRST_MRESETN_SAI_I2S1>, <&cru SRST_HRESETN_SAI_I2S1>;
|
|
reset-names = "m", "h";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2s1_sclk
|
|
&i2s1_lrck
|
|
&i2s1_sdi0
|
|
&i2s1_sdi1
|
|
&i2s1_sdi2
|
|
&i2s1_sdi3
|
|
&i2s1_sdo0
|
|
&i2s1_sdo1
|
|
&i2s1_sdo2
|
|
&i2s1_sdo3>;
|
|
#sound-dai-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pdm: pdm@ffbb0000 {
|
|
compatible = "rockchip,rk3528-pdm", "rockchip,rk3568-pdm";
|
|
reg = <0x0 0xffbb0000 0x0 0x1000>;
|
|
clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>;
|
|
clock-names = "pdm_clk", "pdm_hclk";
|
|
dmas = <&dmac 6>;
|
|
dma-names = "rx";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pdm_clk0
|
|
&pdm_clk1
|
|
&pdm_sdi0
|
|
&pdm_sdi1
|
|
&pdm_sdi2
|
|
&pdm_sdi3>;
|
|
#sound-dai-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spdif_8ch: spdif@ffbc0000 {
|
|
compatible = "rockchip,rk3528-spdif", "rockchip,rk3568-spdif";
|
|
reg = <0x0 0xffbc0000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&dmac 7>;
|
|
dma-names = "tx";
|
|
clock-names = "mclk", "hclk";
|
|
clocks = <&cru MCLK_SPDIF>, <&cru HCLK_SPDIF>;
|
|
#sound-dai-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spdifm0_pins>;
|
|
status = "disabled";
|
|
};
|
|
|
|
gmac0: ethernet@ffbd0000 {
|
|
compatible = "rockchip,rk3528-gmac", "snps,dwmac-4.20a";
|
|
reg = <0x0 0xffbd0000 0x0 0x10000>;
|
|
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "macirq", "eth_wake_irq";
|
|
rockchip,grf = <&grf>;
|
|
clocks = <&cru CLK_GMAC0_SRC>, <&cru CLK_GMAC0_RMII_50M>,
|
|
<&cru CLK_GMAC0_RX>, <&cru CLK_GMAC0_TX>,
|
|
<&cru PCLK_MAC_VO>, <&cru ACLK_MAC_VO>;
|
|
clock-names = "stmmaceth", "clk_mac_ref",
|
|
"mac_clk_rx", "mac_clk_tx",
|
|
"pclk_mac", "aclk_mac";
|
|
resets = <&cru SRST_ARESETN_MAC_VO>;
|
|
reset-names = "stmmaceth";
|
|
|
|
snps,mixed-burst;
|
|
snps,tso;
|
|
|
|
snps,axi-config = <&gmac0_stmmac_axi_setup>;
|
|
snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
|
|
snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
|
|
|
|
phy-mode = "rmii";
|
|
clock_in_out = "input";
|
|
phy-handle = <&rmii0_phy>;
|
|
|
|
nvmem-cells = <&macphy_bgs>;
|
|
nvmem-cell-names = "bgs";
|
|
status = "disabled";
|
|
|
|
mdio0: mdio {
|
|
compatible = "snps,dwmac-mdio";
|
|
#address-cells = <0x1>;
|
|
#size-cells = <0x0>;
|
|
rmii0_phy: ethernet-phy@2 {
|
|
compatible = "ethernet-phy-id0044.1400", "ethernet-phy-ieee802.3-c22";
|
|
reg = <2>;
|
|
clocks = <&cru CLK_MACPHY>;
|
|
resets = <&cru SRST_RESETN_MACPHY>;
|
|
phy-is-integrated;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&fephym0_led_link &fephym0_led_spd>;
|
|
nvmem-cells = <&macphy_txlevel>;
|
|
nvmem-cell-names = "txlevel";
|
|
};
|
|
};
|
|
|
|
gmac0_stmmac_axi_setup: stmmac-axi-config {
|
|
snps,wr_osr_lmt = <4>;
|
|
snps,rd_osr_lmt = <8>;
|
|
snps,blen = <0 0 0 0 16 8 4>;
|
|
};
|
|
|
|
gmac0_mtl_rx_setup: rx-queues-config {
|
|
snps,rx-queues-to-use = <1>;
|
|
queue0 {};
|
|
};
|
|
|
|
gmac0_mtl_tx_setup: tx-queues-config {
|
|
snps,tx-queues-to-use = <1>;
|
|
queue0 {};
|
|
};
|
|
};
|
|
|
|
gmac1: ethernet@ffbe0000 {
|
|
compatible = "rockchip,rk3528-gmac", "snps,dwmac-4.20a";
|
|
reg = <0x0 0xffbe0000 0x0 0x10000>;
|
|
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "macirq", "eth_wake_irq";
|
|
rockchip,grf = <&grf>;
|
|
clocks = <&cru CLK_GMAC1_SRC_VPU>, <&cru CLK_GMAC1_RMII_VPU>,
|
|
<&cru PCLK_MAC_VPU>, <&cru ACLK_MAC_VPU>;
|
|
clock-names = "stmmaceth", "clk_mac_ref",
|
|
"pclk_mac", "aclk_mac";
|
|
resets = <&cru SRST_ARESETN_MAC>;
|
|
reset-names = "stmmaceth";
|
|
|
|
snps,mixed-burst;
|
|
snps,tso;
|
|
|
|
snps,axi-config = <&gmac1_stmmac_axi_setup>;
|
|
snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
|
|
snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
|
|
|
|
status = "disabled";
|
|
|
|
mdio1: mdio {
|
|
compatible = "snps,dwmac-mdio";
|
|
#address-cells = <0x1>;
|
|
#size-cells = <0x0>;
|
|
};
|
|
|
|
gmac1_stmmac_axi_setup: stmmac-axi-config {
|
|
snps,wr_osr_lmt = <4>;
|
|
snps,rd_osr_lmt = <8>;
|
|
snps,blen = <0 0 0 0 16 8 4>;
|
|
};
|
|
|
|
gmac1_mtl_rx_setup: rx-queues-config {
|
|
snps,rx-queues-to-use = <1>;
|
|
queue0 {};
|
|
};
|
|
|
|
gmac1_mtl_tx_setup: tx-queues-config {
|
|
snps,tx-queues-to-use = <1>;
|
|
queue0 {};
|
|
};
|
|
};
|
|
|
|
sdhci: mmc@ffbf0000 {
|
|
compatible = "rockchip,rk3528-dwcmshc";
|
|
reg = <0x0 0xffbf0000 0x0 0x10000>;
|
|
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
|
|
assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_SRC_EMMC>;
|
|
assigned-clock-rates = <200000000>, <24000000>, <200000000>;
|
|
clocks = <&cru CCLK_SRC_EMMC>, <&cru HCLK_EMMC>,
|
|
<&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
|
|
<&cru TCLK_EMMC>;
|
|
clock-names = "core", "bus", "axi", "block", "timer";
|
|
resets = <&cru SRST_CRESETN_EMMC>, <&cru SRST_HRESETN_EMMC>,
|
|
<&cru SRST_ARESETN_EMMC>, <&cru SRST_BRESETN_EMMC>,
|
|
<&cru SRST_TRESETN_EMMC>;
|
|
reset-names = "core", "bus", "axi", "block", "timer";
|
|
max-frequency = <200000000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sfc: spi@ffc00000 {
|
|
compatible = "rockchip,sfc";
|
|
reg = <0x0 0xffc00000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
|
|
clock-names = "clk_sfc", "hclk_sfc";
|
|
assigned-clocks = <&cru SCLK_SFC>;
|
|
assigned-clock-rates = <100000000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdio0: mmc@ffc10000 {
|
|
compatible = "rockchip,rk3528-dw-mshc",
|
|
"rockchip,rk3288-dw-mshc";
|
|
reg = <0x0 0xffc10000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
|
|
max-frequency = <150000000>;
|
|
clocks = <&cru HCLK_SDIO0>, <&cru CCLK_SRC_SDIO0>,
|
|
<&grf_cru SCLK_SDIO0_DRV>, <&grf_cru SCLK_SDIO0_SAMPLE>;
|
|
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
|
fifo-depth = <0x100>;
|
|
resets = <&cru SRST_HRESETN_SDIO0>;
|
|
reset-names = "reset";
|
|
rockchip,use-v2-tuning;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdio1: mmc@ffc20000 {
|
|
compatible = "rockchip,rk3528-dw-mshc",
|
|
"rockchip,rk3288-dw-mshc";
|
|
reg = <0x0 0xffc20000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
|
|
max-frequency = <150000000>;
|
|
clocks = <&cru HCLK_SDIO1>, <&cru CCLK_SRC_SDIO1>,
|
|
<&grf_cru SCLK_SDIO1_DRV>, <&grf_cru SCLK_SDIO1_SAMPLE>;
|
|
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
|
fifo-depth = <0x100>;
|
|
resets = <&cru SRST_HRESETN_SDIO1>;
|
|
reset-names = "reset";
|
|
rockchip,use-v2-tuning;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdmmc: mmc@ffc30000 {
|
|
compatible = "rockchip,rk3528-dw-mshc",
|
|
"rockchip,rk3288-dw-mshc";
|
|
reg = <0x0 0xffc30000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
|
max-frequency = <150000000>;
|
|
clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SRC_SDMMC0>,
|
|
<&grf_cru SCLK_SDMMC_DRV>, <&grf_cru SCLK_SDMMC_SAMPLE>;
|
|
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
|
fifo-depth = <0x100>;
|
|
resets = <&cru SRST_HRESETN_SDMMC0>;
|
|
reset-names = "reset";
|
|
rockchip,use-v2-tuning;
|
|
status = "disabled";
|
|
};
|
|
|
|
crypto: crypto@ffc40000 {
|
|
compatible = "rockchip,crypto-v4";
|
|
reg = <0x0 0xffc40000 0x0 0x2000>;
|
|
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&scmi_clk SCMI_ACLK_CRYPTO>, <&scmi_clk SCMI_HCLK_CRYPTO>,
|
|
<&scmi_clk SCMI_CORE_CRYPTO>, <&scmi_clk SCMI_PKA_CRYPTO>;
|
|
clock-names = "aclk", "hclk", "sclk", "pka";
|
|
assigned-clocks = <&scmi_clk SCMI_CORE_CRYPTO>, <&scmi_clk SCMI_PKA_CRYPTO>;
|
|
assigned-clock-rates = <300000000>, <300000000>;
|
|
resets = <&cru SRST_RESETN_CORE_CRYPTO>;
|
|
reset-names = "crypto-rst";
|
|
status = "disabled";
|
|
};
|
|
|
|
rng: rng@ffc50000 {
|
|
compatible = "rockchip,rkrng";
|
|
reg = <0x0 0xffc50000 0x0 0x200>;
|
|
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&scmi_clk SCMI_HCLK_TRNG>;
|
|
clock-names = "hclk_trng";
|
|
resets = <&cru SRST_HRESETN_TRNG_NS>;
|
|
reset-names = "reset";
|
|
status = "disabled";
|
|
};
|
|
|
|
otp: otp@ffce0000 {
|
|
compatible = "rockchip,rk3528-otp";
|
|
reg = <0x0 0xffce0000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
clocks = <&cru CLK_USER_OTPC_NS>, <&cru CLK_SBPI_OTPC_NS>,
|
|
<&cru PCLK_OTPC_NS>;
|
|
clock-names = "usr", "sbpi", "apb";
|
|
resets = <&cru SRST_RESETN_USER_OTPC_NS>,
|
|
<&cru SRST_RESETN_SBPI_OTPC_NS>,
|
|
<&cru SRST_PRESETN_OTPC_NS>;
|
|
reset-names = "usr", "sbpi", "apb";
|
|
|
|
/* Data cells */
|
|
cpu_code: cpu-code@2 {
|
|
reg = <0x02 0x2>;
|
|
};
|
|
otp_cpu_version: cpu-version@8 {
|
|
reg = <0x08 0x1>;
|
|
bits = <3 3>;
|
|
};
|
|
cpu_mbist_vmin: cpu-mbist-vmin@9 {
|
|
reg = <0x09 0x1>;
|
|
bits = <0 3>;
|
|
};
|
|
gpu_mbist_vmin: gpu-mbist-vmin@9 {
|
|
reg = <0x09 0x1>;
|
|
bits = <3 2>;
|
|
};
|
|
logic_mbist_vmin: logic-mbist-vmin@9 {
|
|
reg = <0x09 0x1>;
|
|
bits = <5 2>;
|
|
};
|
|
otp_id: id@a {
|
|
reg = <0x0a 0x10>;
|
|
};
|
|
cpu_leakage: cpu-leakage@1a {
|
|
reg = <0x1a 0x1>;
|
|
};
|
|
log_leakage: log-leakage@1b {
|
|
reg = <0x1b 0x1>;
|
|
};
|
|
gpu_leakage: gpu-leakage@1c {
|
|
reg = <0x1c 0x1>;
|
|
};
|
|
test_version: test-version@29 {
|
|
reg = <0x29 0x1>;
|
|
};
|
|
macphy_bgs: macphy-bgs@2d {
|
|
reg = <0x2d 0x1>;
|
|
};
|
|
macphy_txlevel: macphy-txlevel@2e {
|
|
reg = <0x2e 0x2>;
|
|
};
|
|
vdac_out_current: vdac-out-current@30 {
|
|
reg = <0x30 0x1>;
|
|
};
|
|
cpu_opp_info: cpu-opp-info@32 {
|
|
reg = <0x32 0x6>;
|
|
};
|
|
gpu_opp_info: gpu-opp-info@38 {
|
|
reg = <0x38 0x6>;
|
|
};
|
|
dmc_opp_info: dmc-opp-info@3e {
|
|
reg = <0x3e 0x6>;
|
|
};
|
|
cpu_tsadc_trim_l: cpu-tsadc-trim-l@44 {
|
|
reg = <0x44 0x1>;
|
|
};
|
|
cpu_tsadc_trim_h: cpu-tsadc-trim-h@45 {
|
|
reg = <0x45 0x1>;
|
|
};
|
|
};
|
|
|
|
dmac: dma-controller@ffd60000 {
|
|
compatible = "arm,pl330", "arm,primecell";
|
|
reg = <0x0 0xffd60000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru ACLK_DMAC>;
|
|
clock-names = "apb_pclk";
|
|
#dma-cells = <1>;
|
|
arm,pl330-periph-burst;
|
|
};
|
|
|
|
hwlock: hwspinlock@ffd70000 {
|
|
compatible = "rockchip,hwspinlock";
|
|
reg = <0x0 0xffd70000 0x0 0x100>;
|
|
#hwlock-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
combphy_pu: phy@ffdc0000 {
|
|
compatible = "rockchip,rk3528-naneng-combphy";
|
|
reg = <0x0 0xffdc0000 0x0 0x10000>;
|
|
#phy-cells = <1>;
|
|
clocks = <&cru CLK_REF_PCIE_INNER_PHY>, <&cru PCLK_PCIE_PHY>, <&cru PCLK_PIPE_GRF>;
|
|
clock-names = "refclk", "apbclk", "pipe_clk";
|
|
assigned-clocks = <&cru CLK_REF_PCIE_INNER_PHY>;
|
|
assigned-clock-rates = <100000000>;
|
|
resets = <&cru SRST_PRESETN_PCIE_PHY>, <&cru SRST_RESETN_PCIE_PIPE_PHY>;
|
|
reset-names = "combphy-apb", "combphy";
|
|
rockchip,pipe-grf = <&grf>;
|
|
rockchip,pipe-phy-grf = <&grf>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb2phy: usb2-phy@ffdf0000 {
|
|
compatible = "rockchip,rk3528-usb2phy";
|
|
reg = <0x0 0xffdf0000 0x0 0x10000>;
|
|
clocks = <&cru CLK_REF_USBPHY>, <&cru PCLK_USBPHY>;
|
|
clock-names = "phyclk", "apb_pclk";
|
|
#clock-cells = <0>;
|
|
rockchip,usbgrf = <&grf>;
|
|
status = "disabled";
|
|
|
|
u2phy_otg: otg-port {
|
|
#phy-cells = <0>;
|
|
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "otg-bvalid",
|
|
"otg-id",
|
|
"linestate";
|
|
status = "disabled";
|
|
};
|
|
|
|
u2phy_host: host-port {
|
|
#phy-cells = <0>;
|
|
interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "linestate";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
hdmiphy: hdmiphy@ffe00000 {
|
|
compatible = "rockchip,rk3528-hdmi-phy";
|
|
reg = <0x0 0xffe00000 0x0 0x10000>;
|
|
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
|
#phy-cells = <0>;
|
|
clocks = <&cru PCLK_HDMIPHY>, <&xin24m>;
|
|
clock-names = "sysclk", "refclk";
|
|
status = "disabled";
|
|
|
|
inno_hdmiphy_clk: clk-port {
|
|
#clock-cells = <0>;
|
|
clock-output-names = "clk_hdmiphy_pixel_io";
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
acodec: acodec@ffe10000 {
|
|
compatible = "rockchip,rk3528-codec";
|
|
reg = <0x0 0xffe10000 0x0 0x1000>;
|
|
#sound-dai-cells = <0>;
|
|
clocks = <&cru PCLK_ACODEC>, <&cru MCLK_ACODEC_TX>;
|
|
clock-names = "pclk", "mclk";
|
|
resets = <&cru SRST_PRESETN_ACODEC>;
|
|
reset-names = "acodec";
|
|
status = "disabled";
|
|
};
|
|
|
|
pinctrl: pinctrl {
|
|
compatible = "rockchip,rk3528-pinctrl";
|
|
rockchip,grf = <&ioc_grf>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
gpio0: gpio@ff610000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x0 0xff610000 0x0 0x200>;
|
|
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&pinctrl 0 0 32>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio1: gpio@ffaf0000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x0 0xffaf0000 0x0 0x200>;
|
|
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&pinctrl 0 32 32>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio2: gpio@ffb00000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x0 0xffb00000 0x0 0x200>;
|
|
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&pinctrl 0 64 32>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio3: gpio@ffb10000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x0 0xffb10000 0x0 0x200>;
|
|
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&pinctrl 0 96 32>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio4: gpio@ffb20000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x0 0xffb20000 0x0 0x200>;
|
|
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&pinctrl 0 128 32>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
};
|
|
|
|
#include "rk3528-pinctrl.dtsi"
|