309 lines
5.1 KiB
Plaintext
309 lines
5.1 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
|
/*
|
|
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
|
|
*
|
|
*/
|
|
/ {
|
|
vcc_mipipwr: vcc-mipipwr-regulator {
|
|
compatible = "regulator-fixed";
|
|
gpio = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&mipicam_pwr>;
|
|
regulator-name = "vcc_mipipwr";
|
|
enable-active-high;
|
|
};
|
|
};
|
|
|
|
&csi2_dphy0 {
|
|
status = "okay";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
mipi_in_ucam0: endpoint@1 {
|
|
reg = <1>;
|
|
remote-endpoint = <&ov13855_out0>;
|
|
data-lanes = <1 2 3 4>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
csidphy0_out: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&mipi0_csi2_input>;
|
|
data-lanes = <1 2 3 4>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&csi2_dphy4 {
|
|
status = "okay";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
mipi_in_ucam1: endpoint@1 {
|
|
reg = <1>;
|
|
remote-endpoint = <&gc8034_out0>;
|
|
data-lanes = <1 2>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
csidphy4_out: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&mipi2_csi2_input>;
|
|
data-lanes = <1 2>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&i2c4 {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c4m0_xfer>;
|
|
|
|
dw9763: dw9763@c {
|
|
compatible = "dongwoon,dw9763";
|
|
status = "okay";
|
|
reg = <0x0c>;
|
|
avdd-supply = <&vcc2v8_dvp>;
|
|
rockchip,vcm-max-current = <120>;
|
|
rockchip,vcm-start-current = <25>;
|
|
rockchip,vcm-rated-current = <100>;
|
|
rockchip,vcm-step-mode = <4>;
|
|
rockchip,vcm-t-src = <0x20>;
|
|
rockchip,vcm-t-div = <1>;
|
|
rockchip,camera-module-index = <0>;
|
|
rockchip,camera-module-facing = "back";
|
|
};
|
|
|
|
ov13855: ov13855@36 {
|
|
status = "okay";
|
|
compatible = "ovti,ov13855";
|
|
reg = <0x36>;
|
|
clocks = <&cru CLK_CAM0_OUT2IO>;
|
|
clock-names = "xvclk";
|
|
pwdn-gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>;
|
|
avdd-supply = <&vcc2v8_dvp>;
|
|
dovdd-supply = <&vcc_mipipwr>;
|
|
dvdd-supply = <&vcc1v2_dvp>;
|
|
rockchip,camera-module-index = <0>;
|
|
rockchip,camera-module-facing = "back";
|
|
rockchip,camera-module-name = "KYT-10203-v1";
|
|
rockchip,camera-module-lens-name = "default";
|
|
lens-focus = <&dw9763>;
|
|
|
|
port {
|
|
ov13855_out0: endpoint {
|
|
remote-endpoint = <&mipi_in_ucam0>;
|
|
data-lanes = <1 2 3 4>;
|
|
};
|
|
};
|
|
};
|
|
|
|
gc8034: gc8034@37 {
|
|
compatible = "galaxycore,gc8034";
|
|
status = "okay";
|
|
reg = <0x37>;
|
|
clocks = <&cru CLK_CAM0_OUT2IO>;
|
|
clock-names = "xvclk";
|
|
pwdn-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
|
|
avdd-supply = <&vcc2v8_dvp>;
|
|
dovdd-supply = <&vcc_mipipwr>;
|
|
dvdd-supply = <&vcc1v2_dvp>;
|
|
rockchip,camera-module-index = <1>;
|
|
rockchip,camera-module-facing = "front";
|
|
rockchip,camera-module-name = "KYT-10203-v1";
|
|
rockchip,camera-module-lens-name = "default";
|
|
port {
|
|
gc8034_out0: endpoint {
|
|
remote-endpoint = <&mipi_in_ucam1>;
|
|
data-lanes = <1 2>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&csi2_dphy0_hw {
|
|
status = "okay";
|
|
};
|
|
|
|
&csi2_dphy1_hw {
|
|
status = "okay";
|
|
};
|
|
|
|
&mipi0_csi2 {
|
|
status = "okay";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
mipi0_csi2_input: endpoint@1 {
|
|
reg = <1>;
|
|
remote-endpoint = <&csidphy0_out>;
|
|
data-lanes = <1 2 3 4>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
mipi0_csi2_output: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&cif_mipi_in>;
|
|
data-lanes = <1 2 3 4>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&mipi2_csi2 {
|
|
status = "okay";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
mipi2_csi2_input: endpoint@1 {
|
|
reg = <1>;
|
|
remote-endpoint = <&csidphy4_out>;
|
|
data-lanes = <1 2>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
mipi2_csi2_output: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&cif_mipi_in2>;
|
|
data-lanes = <1 2>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&rkcif {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&camm0_clk0_out>;
|
|
};
|
|
|
|
&rkcif_mipi_lvds {
|
|
status = "okay";
|
|
|
|
port {
|
|
cif_mipi_in: endpoint {
|
|
remote-endpoint = <&mipi0_csi2_output>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&rkcif_mipi_lvds2 {
|
|
status = "okay";
|
|
|
|
port {
|
|
cif_mipi_in2: endpoint {
|
|
remote-endpoint = <&mipi2_csi2_output>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&rkcif_mipi_lvds_sditf {
|
|
status = "okay";
|
|
|
|
port {
|
|
mipi_lvds_sditf: endpoint {
|
|
remote-endpoint = <&isp_vir0_in0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&rkcif_mipi_lvds2_sditf {
|
|
status = "okay";
|
|
|
|
port {
|
|
mipi_lvds2_sditf: endpoint {
|
|
remote-endpoint = <&isp_vir0_in1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&rkcif_mmu {
|
|
status = "okay";
|
|
};
|
|
|
|
&rkisp {
|
|
status = "okay";
|
|
};
|
|
|
|
&rkisp_mmu {
|
|
status = "okay";
|
|
};
|
|
|
|
&rkisp_vir0 {
|
|
status = "okay";
|
|
|
|
port {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
isp_vir0_in0: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&mipi_lvds_sditf>;
|
|
};
|
|
isp_vir0_in1: endpoint@1 {
|
|
reg = <1>;
|
|
remote-endpoint = <&mipi_lvds2_sditf>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&pinctrl {
|
|
cam {
|
|
mipicam_pwr: mipicam-pwr {
|
|
rockchip,pins =
|
|
/* camera power en */
|
|
<3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
};
|
|
};
|
|
};
|