66 lines
1.2 KiB
Plaintext
66 lines
1.2 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2020 Rockchip Electronics Co., Ltd.
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*/
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#include "rk3568.dtsi"
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/ {
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aliases {
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/delete-property/ ethernet0;
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};
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};
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&cpu0_opp_table {
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/delete-node/ opp-1992000000;
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};
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&lpddr4_params {
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/* freq info, freq_0 is final frequency, unit: MHz */
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freq_0 = <1056>;
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};
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&lpddr4x_params {
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/* freq info, freq_0 is final frequency, unit: MHz */
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freq_0 = <1056>;
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};
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&power {
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pd_pipe@RK3568_PD_PIPE {
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reg = <RK3568_PD_PIPE>;
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clocks = <&cru PCLK_PIPE>;
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pm_qos = <&qos_pcie2x1>,
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<&qos_sata1>,
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<&qos_sata2>,
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<&qos_usb3_0>,
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<&qos_usb3_1>;
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};
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};
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&rkisp {
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rockchip,iq-feature = /bits/ 64 <0x1BFBF7FE67FF>;
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};
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&usbdrd_dwc3 {
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phys = <&u2phy0_otg>;
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phy-names = "usb2-phy";
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extcon = <&usb2phy0>;
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maximum-speed = "high-speed";
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snps,dis_u2_susphy_quirk;
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snps,usb2-lpm-disable;
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};
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/delete-node/ &combphy0_us;
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/delete-node/ &gmac0_clkin;
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/delete-node/ &gmac0_xpcsclk;
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/delete-node/ &gmac0;
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/delete-node/ &gmac_uio0;
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/delete-node/ &pcie30_phy_grf;
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/delete-node/ &pcie30phy;
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/delete-node/ &pcie3x1;
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/delete-node/ &pcie3x2;
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/delete-node/ &qos_pcie3x1;
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/delete-node/ &qos_pcie3x2;
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/delete-node/ &qos_sata0;
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/delete-node/ &sata0;
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