1268 lines
22 KiB
Plaintext
1268 lines
22 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
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*
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pwm/pwm.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/input/rk-input.h>
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#include <dt-bindings/display/drm_mipi_dsi.h>
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#include <dt-bindings/display/rockchip_vop.h>
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#include <dt-bindings/sensor-dev.h>
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/ {
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adc_keys: adc-keys {
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compatible = "adc-keys";
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io-channels = <&saradc 1>;
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io-channel-names = "buttons";
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keyup-threshold-microvolt = <1800000>;
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poll-interval = <100>;
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vol-up-key {
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label = "volume up";
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linux,code = <KEY_VOLUMEUP>;
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press-threshold-microvolt = <17000>;
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};
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vol-down-key {
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label = "volume down";
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linux,code = <KEY_VOLUMEDOWN>;
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press-threshold-microvolt = <417000>;
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};
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menu-key {
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label = "menu";
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linux,code = <KEY_MENU>;
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press-threshold-microvolt = <890000>;
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};
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back-key {
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label = "back";
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linux,code = <KEY_BACK>;
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press-threshold-microvolt = <1235000>;
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};
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};
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backlight: backlight {
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compatible = "pwm-backlight";
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brightness-levels = <
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0 20 20 21 21 22 22 23
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23 24 24 25 25 26 26 27
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27 28 28 29 29 30 30 31
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31 32 32 33 33 34 34 35
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35 36 36 37 37 38 38 39
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40 41 42 43 44 45 46 47
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48 49 50 51 52 53 54 55
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56 57 58 59 60 61 62 63
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64 65 66 67 68 69 70 71
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72 73 74 75 76 77 78 79
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80 81 82 83 84 85 86 87
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88 89 90 91 92 93 94 95
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96 97 98 99 100 101 102 103
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104 105 106 107 108 109 110 111
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112 113 114 115 116 117 118 119
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120 121 122 123 124 125 126 127
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128 129 130 131 132 133 134 135
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136 137 138 139 140 141 142 143
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144 145 146 147 148 149 150 151
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152 153 154 155 156 157 158 159
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160 161 162 163 164 165 166 167
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168 169 170 171 172 173 174 175
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176 177 178 179 180 181 182 183
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184 185 186 187 188 189 190 191
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192 193 194 195 196 197 198 199
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200 201 202 203 204 205 206 207
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208 209 210 211 212 213 214 215
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216 217 218 219 220 221 222 223
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224 225 226 227 228 229 230 231
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232 233 234 235 236 237 238 239
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240 241 242 243 244 245 246 247
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248 249 250 251 252 253 254 255
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>;
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default-brightness-level = <200>;
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};
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dp0_sound: dp0-sound {
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status = "disabled";
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compatible = "rockchip,hdmi";
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rockchip,card-name= "rockchip-dp0";
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rockchip,mclk-fs = <512>;
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rockchip,cpu = <&spdif_tx2>;
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rockchip,codec = <&dp0 1>;
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rockchip,jack-det;
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};
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dp1_sound: dp1-sound {
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status = "disabled";
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compatible = "rockchip,hdmi";
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rockchip,card-name= "rockchip-dp1";
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rockchip,mclk-fs = <512>;
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rockchip,cpu = <&spdif_tx5>;
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rockchip,codec = <&dp1 1>;
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rockchip,jack-det;
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};
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hdmi0_sound: hdmi0-sound {
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status = "disabled";
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compatible = "rockchip,hdmi";
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rockchip,mclk-fs = <128>;
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rockchip,card-name = "rockchip-hdmi0";
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rockchip,cpu = <&i2s5_8ch>;
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rockchip,codec = <&hdmi0>;
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rockchip,jack-det;
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};
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hdmi1_sound: hdmi1-sound {
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status = "disabled";
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compatible = "rockchip,hdmi";
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rockchip,mclk-fs = <128>;
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rockchip,card-name = "rockchip-hdmi1";
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rockchip,cpu = <&i2s6_8ch>;
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rockchip,codec = <&hdmi1>;
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rockchip,jack-det;
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};
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leds: leds {
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compatible = "gpio-leds";
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work_led: work {
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gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "heartbeat";
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};
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};
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spdif_tx1_dc: spdif-tx1-dc {
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status = "disabled";
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compatible = "linux,spdif-dit";
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#sound-dai-cells = <0>;
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};
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spdif_tx1_sound: spdif-tx1-sound {
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status = "disabled";
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compatible = "simple-audio-card";
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simple-audio-card,name = "rockchip,spdif-tx1";
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simple-audio-card,mclk-fs = <128>;
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simple-audio-card,cpu {
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sound-dai = <&spdif_tx1>;
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};
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simple-audio-card,codec {
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sound-dai = <&spdif_tx1_dc>;
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};
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};
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test-power {
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status = "okay";
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};
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vcc12v_dcin: vcc12v-dcin {
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compatible = "regulator-fixed";
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regulator-name = "vcc12v_dcin";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <12000000>;
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regulator-max-microvolt = <12000000>;
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};
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vcc5v0_sys: vcc5v0-sys {
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compatible = "regulator-fixed";
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regulator-name = "vcc5v0_sys";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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vin-supply = <&vcc12v_dcin>;
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};
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vcc5v0_usbdcin: vcc5v0-usbdcin {
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compatible = "regulator-fixed";
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regulator-name = "vcc5v0_usbdcin";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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vin-supply = <&vcc12v_dcin>;
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};
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vcc5v0_usb: vcc5v0-usb {
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compatible = "regulator-fixed";
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regulator-name = "vcc5v0_usb";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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vin-supply = <&vcc5v0_usbdcin>;
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};
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/*
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*in TB-RK3588 gpio0 RK_PB6 for MIPI dsi tp
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*/
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spi2: spi@feb20000 {
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compatible = "rockchip,rk3066-spi";
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reg = <0x0 0xfeb20000 0x0 0x1000>;
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interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
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clock-names = "spiclk", "apb_pclk";
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dmas = <&dmac1 15>, <&dmac1 16>;
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dma-names = "tx", "rx";
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pinctrl-names = "default";
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pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
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num-cs = <2>;
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status = "okay";
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};
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/*
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*just for rk3588s-evb4 in rk3588-rk806-single.dtsi
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*in TB-RK3588 gpio1 RK_PA6 for edp tp
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*/
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vcc_1v2_cam_s0: vcc-1v2-cam-s0 {
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status = "disabled";
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compatible = "regulator-fixed";
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regulator-name = "vcc_1v2_cam_s0";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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vin-supply = <&vcc_3v3_s3>;
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regulator-state-mem {
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regulator-off-in-suspend;
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};
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};
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vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 {
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compatible = "regulator-fixed";
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regulator-name = "vcc_1v1_nldo_s3";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <1100000>;
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regulator-max-microvolt = <1100000>;
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vin-supply = <&vcc5v0_sys>;
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};
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vcc_3v3_sd_s0: vcc-3v3-sd-s0 {
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compatible = "regulator-fixed";
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regulator-name = "vcc_3v3_sd_s0";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_LOW>;
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enable-active-low;
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vin-supply = <&vcc_3v3_s3>;
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regulator-state-mem {
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regulator-off-in-suspend;
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};
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};
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};
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&av1d_mmu {
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status = "okay";
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};
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&dsi0 {
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status = "disabled";
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//rockchip,lane-rate = <1000>;
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dsi0_panel: panel@0 {
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status = "okay";
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compatible = "simple-panel-dsi";
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reg = <0>;
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backlight = <&backlight>;
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reset-delay-ms = <60>;
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enable-delay-ms = <60>;
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prepare-delay-ms = <60>;
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unprepare-delay-ms = <60>;
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disable-delay-ms = <60>;
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dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
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MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
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dsi,format = <MIPI_DSI_FMT_RGB888>;
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dsi,lanes = <4>;
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panel-init-sequence = [
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23 00 02 FE 21
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23 00 02 04 00
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23 00 02 00 64
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23 00 02 2A 00
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23 00 02 26 64
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23 00 02 54 00
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23 00 02 50 64
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23 00 02 7B 00
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23 00 02 77 64
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23 00 02 A2 00
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23 00 02 9D 64
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23 00 02 C9 00
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23 00 02 C5 64
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23 00 02 01 71
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23 00 02 27 71
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23 00 02 51 71
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23 00 02 78 71
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23 00 02 9E 71
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23 00 02 C6 71
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23 00 02 02 89
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23 00 02 28 89
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23 00 02 52 89
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23 00 02 79 89
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23 00 02 9F 89
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23 00 02 C7 89
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23 00 02 03 9E
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23 00 02 29 9E
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23 00 02 53 9E
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23 00 02 7A 9E
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23 00 02 A0 9E
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23 00 02 C8 9E
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23 00 02 09 00
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23 00 02 05 B0
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23 00 02 31 00
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23 00 02 2B B0
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23 00 02 5A 00
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23 00 02 55 B0
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23 00 02 80 00
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23 00 02 7C B0
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23 00 02 A7 00
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23 00 02 A3 B0
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23 00 02 CE 00
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23 00 02 CA B0
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23 00 02 06 C0
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23 00 02 2D C0
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23 00 02 56 C0
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23 00 02 7D C0
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23 00 02 A4 C0
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23 00 02 CB C0
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23 00 02 07 CF
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23 00 02 2F CF
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23 00 02 58 CF
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23 00 02 7E CF
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23 00 02 A5 CF
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23 00 02 CC CF
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23 00 02 08 DD
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23 00 02 30 DD
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23 00 02 59 DD
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23 00 02 7F DD
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23 00 02 A6 DD
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23 00 02 CD DD
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23 00 02 0E 15
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23 00 02 0A E9
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23 00 02 36 15
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23 00 02 32 E9
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23 00 02 5F 15
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23 00 02 5B E9
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23 00 02 85 15
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23 00 02 81 E9
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23 00 02 AD 15
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23 00 02 A9 E9
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23 00 02 D3 15
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23 00 02 CF E9
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23 00 02 0B 14
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23 00 02 33 14
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23 00 02 5C 14
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23 00 02 82 14
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23 00 02 AA 14
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23 00 02 D0 14
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23 00 02 0C 36
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23 00 02 34 36
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23 00 02 5D 36
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23 00 02 83 36
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23 00 02 AB 36
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23 00 02 D1 36
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23 00 02 0D 6B
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23 00 02 35 6B
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23 00 02 5E 6B
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23 00 02 84 6B
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23 00 02 AC 6B
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23 00 02 D2 6B
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23 00 02 13 5A
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23 00 02 0F 94
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23 00 02 3B 5A
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23 00 02 37 94
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23 00 02 64 5A
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23 00 02 60 94
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23 00 02 8A 5A
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23 00 02 86 94
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23 00 02 B2 5A
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23 00 02 AE 94
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23 00 02 D8 5A
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23 00 02 D4 94
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23 00 02 10 D1
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23 00 02 38 D1
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23 00 02 61 D1
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23 00 02 87 D1
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23 00 02 AF D1
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23 00 02 D5 D1
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23 00 02 11 04
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23 00 02 39 04
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23 00 02 62 04
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23 00 02 88 04
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23 00 02 B0 04
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23 00 02 D6 04
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23 00 02 12 05
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23 00 02 3A 05
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23 00 02 63 05
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23 00 02 89 05
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23 00 02 B1 05
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23 00 02 D7 05
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23 00 02 18 AA
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23 00 02 14 36
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23 00 02 42 AA
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23 00 02 3D 36
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23 00 02 69 AA
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23 00 02 65 36
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23 00 02 8F AA
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23 00 02 8B 36
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23 00 02 B7 AA
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23 00 02 B3 36
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23 00 02 DD AA
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23 00 02 D9 36
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23 00 02 15 74
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23 00 02 3F 74
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23 00 02 66 74
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23 00 02 8C 74
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23 00 02 B4 74
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23 00 02 DA 74
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23 00 02 16 9F
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23 00 02 40 9F
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23 00 02 67 9F
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23 00 02 8D 9F
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23 00 02 B5 9F
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23 00 02 DB 9F
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23 00 02 17 DC
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23 00 02 41 DC
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23 00 02 68 DC
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23 00 02 8E DC
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23 00 02 B6 DC
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23 00 02 DC DC
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23 00 02 1D FF
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23 00 02 19 03
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23 00 02 47 FF
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23 00 02 43 03
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23 00 02 6E FF
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23 00 02 6A 03
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23 00 02 94 FF
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23 00 02 90 03
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23 00 02 BC FF
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23 00 02 B8 03
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23 00 02 E2 FF
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23 00 02 DE 03
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23 00 02 1A 35
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23 00 02 44 35
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23 00 02 6B 35
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23 00 02 91 35
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23 00 02 B9 35
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23 00 02 DF 35
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23 00 02 1B 45
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23 00 02 45 45
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23 00 02 6C 45
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23 00 02 92 45
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23 00 02 BA 45
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23 00 02 E0 45
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23 00 02 1C 55
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23 00 02 46 55
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23 00 02 6D 55
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23 00 02 93 55
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23 00 02 BB 55
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23 00 02 E1 55
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23 00 02 22 FF
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23 00 02 1E 68
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23 00 02 4C FF
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23 00 02 48 68
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23 00 02 73 FF
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23 00 02 6F 68
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23 00 02 99 FF
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23 00 02 95 68
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23 00 02 C1 FF
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23 00 02 BD 68
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23 00 02 E7 FF
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23 00 02 E3 68
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23 00 02 1F 7E
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23 00 02 49 7E
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23 00 02 70 7E
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23 00 02 96 7E
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23 00 02 BE 7E
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23 00 02 E4 7E
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23 00 02 20 97
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23 00 02 4A 97
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23 00 02 71 97
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23 00 02 97 97
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23 00 02 BF 97
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23 00 02 E5 97
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23 00 02 21 B5
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23 00 02 4B B5
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23 00 02 72 B5
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23 00 02 98 B5
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23 00 02 C0 B5
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23 00 02 E6 B5
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23 00 02 25 F0
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23 00 02 23 E8
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23 00 02 4F F0
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23 00 02 4D E8
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23 00 02 76 F0
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23 00 02 74 E8
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23 00 02 9C F0
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23 00 02 9A E8
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23 00 02 C4 F0
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23 00 02 C2 E8
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23 00 02 EA F0
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23 00 02 E8 E8
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23 00 02 24 FF
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23 00 02 4E FF
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23 00 02 75 FF
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23 00 02 9B FF
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23 00 02 C3 FF
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23 00 02 E9 FF
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23 00 02 FE 3D
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23 00 02 00 04
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23 00 02 FE 23
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23 00 02 08 82
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23 00 02 0A 00
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23 00 02 0B 00
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23 00 02 0C 01
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23 00 02 16 00
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23 00 02 18 02
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23 00 02 1B 04
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23 00 02 19 04
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23 00 02 1C 81
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23 00 02 1F 00
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23 00 02 20 03
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23 00 02 23 04
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23 00 02 21 01
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23 00 02 54 63
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23 00 02 55 54
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23 00 02 6E 45
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23 00 02 6D 36
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23 00 02 FE 3D
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23 00 02 55 78
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23 00 02 FE 20
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23 00 02 26 30
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23 00 02 FE 3D
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23 00 02 20 71
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23 00 02 50 8F
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23 00 02 51 8F
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|
23 00 02 FE 00
|
|
23 00 02 35 00
|
|
05 78 01 11
|
|
05 1E 01 29
|
|
];
|
|
|
|
panel-exit-sequence = [
|
|
05 00 01 28
|
|
05 00 01 10
|
|
];
|
|
|
|
disp_timings0: display-timings {
|
|
native-mode = <&dsi0_timing0>;
|
|
dsi0_timing0: timing0 {
|
|
clock-frequency = <132000000>;
|
|
hactive = <1080>;
|
|
vactive = <1920>;
|
|
hfront-porch = <15>;
|
|
hsync-len = <4>;
|
|
hback-porch = <30>;
|
|
vfront-porch = <15>;
|
|
vsync-len = <2>;
|
|
vback-porch = <15>;
|
|
hsync-active = <0>;
|
|
vsync-active = <0>;
|
|
de-active = <0>;
|
|
pixelclk-active = <0>;
|
|
};
|
|
};
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
panel_in_dsi: endpoint {
|
|
remote-endpoint = <&dsi_out_panel>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
dsi_out_panel: endpoint {
|
|
remote-endpoint = <&panel_in_dsi>;
|
|
};
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
&dsi1 {
|
|
status = "disabled";
|
|
//rockchip,lane-rate = <1000>;
|
|
dsi1_panel: panel@0 {
|
|
status = "okay";
|
|
compatible = "simple-panel-dsi";
|
|
reg = <0>;
|
|
backlight = <&backlight>;
|
|
reset-delay-ms = <60>;
|
|
enable-delay-ms = <60>;
|
|
prepare-delay-ms = <60>;
|
|
unprepare-delay-ms = <60>;
|
|
disable-delay-ms = <60>;
|
|
dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
|
|
MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
|
|
dsi,format = <MIPI_DSI_FMT_RGB888>;
|
|
dsi,lanes = <4>;
|
|
panel-init-sequence = [
|
|
23 00 02 FE 21
|
|
23 00 02 04 00
|
|
23 00 02 00 64
|
|
23 00 02 2A 00
|
|
23 00 02 26 64
|
|
23 00 02 54 00
|
|
23 00 02 50 64
|
|
23 00 02 7B 00
|
|
23 00 02 77 64
|
|
23 00 02 A2 00
|
|
23 00 02 9D 64
|
|
23 00 02 C9 00
|
|
23 00 02 C5 64
|
|
23 00 02 01 71
|
|
23 00 02 27 71
|
|
23 00 02 51 71
|
|
23 00 02 78 71
|
|
23 00 02 9E 71
|
|
23 00 02 C6 71
|
|
23 00 02 02 89
|
|
23 00 02 28 89
|
|
23 00 02 52 89
|
|
23 00 02 79 89
|
|
23 00 02 9F 89
|
|
23 00 02 C7 89
|
|
23 00 02 03 9E
|
|
23 00 02 29 9E
|
|
23 00 02 53 9E
|
|
23 00 02 7A 9E
|
|
23 00 02 A0 9E
|
|
23 00 02 C8 9E
|
|
23 00 02 09 00
|
|
23 00 02 05 B0
|
|
23 00 02 31 00
|
|
23 00 02 2B B0
|
|
23 00 02 5A 00
|
|
23 00 02 55 B0
|
|
23 00 02 80 00
|
|
23 00 02 7C B0
|
|
23 00 02 A7 00
|
|
23 00 02 A3 B0
|
|
23 00 02 CE 00
|
|
23 00 02 CA B0
|
|
23 00 02 06 C0
|
|
23 00 02 2D C0
|
|
23 00 02 56 C0
|
|
23 00 02 7D C0
|
|
23 00 02 A4 C0
|
|
23 00 02 CB C0
|
|
23 00 02 07 CF
|
|
23 00 02 2F CF
|
|
23 00 02 58 CF
|
|
23 00 02 7E CF
|
|
23 00 02 A5 CF
|
|
23 00 02 CC CF
|
|
23 00 02 08 DD
|
|
23 00 02 30 DD
|
|
23 00 02 59 DD
|
|
23 00 02 7F DD
|
|
23 00 02 A6 DD
|
|
23 00 02 CD DD
|
|
23 00 02 0E 15
|
|
23 00 02 0A E9
|
|
23 00 02 36 15
|
|
23 00 02 32 E9
|
|
23 00 02 5F 15
|
|
23 00 02 5B E9
|
|
23 00 02 85 15
|
|
23 00 02 81 E9
|
|
23 00 02 AD 15
|
|
23 00 02 A9 E9
|
|
23 00 02 D3 15
|
|
23 00 02 CF E9
|
|
23 00 02 0B 14
|
|
23 00 02 33 14
|
|
23 00 02 5C 14
|
|
23 00 02 82 14
|
|
23 00 02 AA 14
|
|
23 00 02 D0 14
|
|
23 00 02 0C 36
|
|
23 00 02 34 36
|
|
23 00 02 5D 36
|
|
23 00 02 83 36
|
|
23 00 02 AB 36
|
|
23 00 02 D1 36
|
|
23 00 02 0D 6B
|
|
23 00 02 35 6B
|
|
23 00 02 5E 6B
|
|
23 00 02 84 6B
|
|
23 00 02 AC 6B
|
|
23 00 02 D2 6B
|
|
23 00 02 13 5A
|
|
23 00 02 0F 94
|
|
23 00 02 3B 5A
|
|
23 00 02 37 94
|
|
23 00 02 64 5A
|
|
23 00 02 60 94
|
|
23 00 02 8A 5A
|
|
23 00 02 86 94
|
|
23 00 02 B2 5A
|
|
23 00 02 AE 94
|
|
23 00 02 D8 5A
|
|
23 00 02 D4 94
|
|
23 00 02 10 D1
|
|
23 00 02 38 D1
|
|
23 00 02 61 D1
|
|
23 00 02 87 D1
|
|
23 00 02 AF D1
|
|
23 00 02 D5 D1
|
|
23 00 02 11 04
|
|
23 00 02 39 04
|
|
23 00 02 62 04
|
|
23 00 02 88 04
|
|
23 00 02 B0 04
|
|
23 00 02 D6 04
|
|
23 00 02 12 05
|
|
23 00 02 3A 05
|
|
23 00 02 63 05
|
|
23 00 02 89 05
|
|
23 00 02 B1 05
|
|
23 00 02 D7 05
|
|
23 00 02 18 AA
|
|
23 00 02 14 36
|
|
23 00 02 42 AA
|
|
23 00 02 3D 36
|
|
23 00 02 69 AA
|
|
23 00 02 65 36
|
|
23 00 02 8F AA
|
|
23 00 02 8B 36
|
|
23 00 02 B7 AA
|
|
23 00 02 B3 36
|
|
23 00 02 DD AA
|
|
23 00 02 D9 36
|
|
23 00 02 15 74
|
|
23 00 02 3F 74
|
|
23 00 02 66 74
|
|
23 00 02 8C 74
|
|
23 00 02 B4 74
|
|
23 00 02 DA 74
|
|
23 00 02 16 9F
|
|
23 00 02 40 9F
|
|
23 00 02 67 9F
|
|
23 00 02 8D 9F
|
|
23 00 02 B5 9F
|
|
23 00 02 DB 9F
|
|
23 00 02 17 DC
|
|
23 00 02 41 DC
|
|
23 00 02 68 DC
|
|
23 00 02 8E DC
|
|
23 00 02 B6 DC
|
|
23 00 02 DC DC
|
|
23 00 02 1D FF
|
|
23 00 02 19 03
|
|
23 00 02 47 FF
|
|
23 00 02 43 03
|
|
23 00 02 6E FF
|
|
23 00 02 6A 03
|
|
23 00 02 94 FF
|
|
23 00 02 90 03
|
|
23 00 02 BC FF
|
|
23 00 02 B8 03
|
|
23 00 02 E2 FF
|
|
23 00 02 DE 03
|
|
23 00 02 1A 35
|
|
23 00 02 44 35
|
|
23 00 02 6B 35
|
|
23 00 02 91 35
|
|
23 00 02 B9 35
|
|
23 00 02 DF 35
|
|
23 00 02 1B 45
|
|
23 00 02 45 45
|
|
23 00 02 6C 45
|
|
23 00 02 92 45
|
|
23 00 02 BA 45
|
|
23 00 02 E0 45
|
|
23 00 02 1C 55
|
|
23 00 02 46 55
|
|
23 00 02 6D 55
|
|
23 00 02 93 55
|
|
23 00 02 BB 55
|
|
23 00 02 E1 55
|
|
23 00 02 22 FF
|
|
23 00 02 1E 68
|
|
23 00 02 4C FF
|
|
23 00 02 48 68
|
|
23 00 02 73 FF
|
|
23 00 02 6F 68
|
|
23 00 02 99 FF
|
|
23 00 02 95 68
|
|
23 00 02 C1 FF
|
|
23 00 02 BD 68
|
|
23 00 02 E7 FF
|
|
23 00 02 E3 68
|
|
23 00 02 1F 7E
|
|
23 00 02 49 7E
|
|
23 00 02 70 7E
|
|
23 00 02 96 7E
|
|
23 00 02 BE 7E
|
|
23 00 02 E4 7E
|
|
23 00 02 20 97
|
|
23 00 02 4A 97
|
|
23 00 02 71 97
|
|
23 00 02 97 97
|
|
23 00 02 BF 97
|
|
23 00 02 E5 97
|
|
23 00 02 21 B5
|
|
23 00 02 4B B5
|
|
23 00 02 72 B5
|
|
23 00 02 98 B5
|
|
23 00 02 C0 B5
|
|
23 00 02 E6 B5
|
|
23 00 02 25 F0
|
|
23 00 02 23 E8
|
|
23 00 02 4F F0
|
|
23 00 02 4D E8
|
|
23 00 02 76 F0
|
|
23 00 02 74 E8
|
|
23 00 02 9C F0
|
|
23 00 02 9A E8
|
|
23 00 02 C4 F0
|
|
23 00 02 C2 E8
|
|
23 00 02 EA F0
|
|
23 00 02 E8 E8
|
|
23 00 02 24 FF
|
|
23 00 02 4E FF
|
|
23 00 02 75 FF
|
|
23 00 02 9B FF
|
|
23 00 02 C3 FF
|
|
23 00 02 E9 FF
|
|
23 00 02 FE 3D
|
|
23 00 02 00 04
|
|
23 00 02 FE 23
|
|
23 00 02 08 82
|
|
23 00 02 0A 00
|
|
23 00 02 0B 00
|
|
23 00 02 0C 01
|
|
23 00 02 16 00
|
|
23 00 02 18 02
|
|
23 00 02 1B 04
|
|
23 00 02 19 04
|
|
23 00 02 1C 81
|
|
23 00 02 1F 00
|
|
23 00 02 20 03
|
|
23 00 02 23 04
|
|
23 00 02 21 01
|
|
23 00 02 54 63
|
|
23 00 02 55 54
|
|
23 00 02 6E 45
|
|
23 00 02 6D 36
|
|
23 00 02 FE 3D
|
|
23 00 02 55 78
|
|
23 00 02 FE 20
|
|
23 00 02 26 30
|
|
23 00 02 FE 3D
|
|
23 00 02 20 71
|
|
23 00 02 50 8F
|
|
23 00 02 51 8F
|
|
23 00 02 FE 00
|
|
23 00 02 35 00
|
|
05 78 01 11
|
|
05 1E 01 29
|
|
];
|
|
|
|
panel-exit-sequence = [
|
|
05 00 01 28
|
|
05 00 01 10
|
|
];
|
|
|
|
disp_timings1: display-timings {
|
|
native-mode = <&dsi1_timing0>;
|
|
dsi1_timing0: timing0 {
|
|
clock-frequency = <132000000>;
|
|
hactive = <1080>;
|
|
vactive = <1920>;
|
|
hfront-porch = <15>;
|
|
hsync-len = <4>;
|
|
hback-porch = <30>;
|
|
vfront-porch = <15>;
|
|
vsync-len = <2>;
|
|
vback-porch = <15>;
|
|
hsync-active = <0>;
|
|
vsync-active = <0>;
|
|
de-active = <0>;
|
|
pixelclk-active = <0>;
|
|
};
|
|
};
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
panel_in_dsi1: endpoint {
|
|
remote-endpoint = <&dsi1_out_panel>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
dsi1_out_panel: endpoint {
|
|
remote-endpoint = <&panel_in_dsi1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
&gpu {
|
|
mali-supply = <&vdd_gpu_s0>;
|
|
mem-supply = <&vdd_gpu_mem_s0>;
|
|
status = "okay";
|
|
};
|
|
|
|
&i2s0_8ch {
|
|
status = "okay";
|
|
pinctrl-0 = <&i2s0_lrck
|
|
&i2s0_sclk
|
|
&i2s0_sdi0
|
|
&i2s0_sdo0>;
|
|
};
|
|
|
|
&iep {
|
|
status = "okay";
|
|
};
|
|
|
|
&iep_mmu {
|
|
status = "okay";
|
|
};
|
|
|
|
&jpegd {
|
|
status = "okay";
|
|
};
|
|
|
|
&jpegd_mmu {
|
|
status = "okay";
|
|
};
|
|
|
|
&jpege_ccu {
|
|
status = "okay";
|
|
};
|
|
&jpege0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&jpege0_mmu {
|
|
status = "okay";
|
|
};
|
|
|
|
&jpege1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&jpege1_mmu {
|
|
status = "okay";
|
|
};
|
|
|
|
&jpege2 {
|
|
status = "okay";
|
|
};
|
|
|
|
&jpege2_mmu {
|
|
status = "okay";
|
|
};
|
|
|
|
&jpege3 {
|
|
status = "okay";
|
|
};
|
|
|
|
&jpege3_mmu {
|
|
status = "okay";
|
|
};
|
|
|
|
&mpp_srv {
|
|
status = "okay";
|
|
};
|
|
|
|
&rga3_core0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&rga3_0_mmu {
|
|
status = "okay";
|
|
};
|
|
|
|
&rga3_core1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&rga3_1_mmu {
|
|
status = "okay";
|
|
};
|
|
|
|
&rga2 {
|
|
status = "okay";
|
|
};
|
|
|
|
&rknpu {
|
|
rknpu-supply = <&vdd_npu_s0>;
|
|
mem-supply = <&vdd_npu_mem_s0>;
|
|
status = "okay";
|
|
};
|
|
|
|
&rknpu_mmu {
|
|
status = "okay";
|
|
};
|
|
|
|
&rkvdec_ccu {
|
|
status = "okay";
|
|
};
|
|
&rkvdec0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&rkvdec0_mmu {
|
|
status = "okay";
|
|
};
|
|
|
|
&rkvdec1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&rkvdec1_mmu {
|
|
status = "okay";
|
|
};
|
|
|
|
&rkvenc_ccu {
|
|
status = "okay";
|
|
};
|
|
|
|
&rkvenc0 {
|
|
venc-supply = <&vdd_vdenc_s0>;
|
|
mem-supply = <&vdd_vdenc_mem_s0>;
|
|
status = "okay";
|
|
};
|
|
|
|
&rkvenc0_mmu {
|
|
status = "okay";
|
|
};
|
|
|
|
&rkvenc1 {
|
|
venc-supply = <&vdd_vdenc_s0>;
|
|
mem-supply = <&vdd_vdenc_mem_s0>;
|
|
status = "okay";
|
|
};
|
|
|
|
&rkvenc1_mmu {
|
|
status = "okay";
|
|
};
|
|
|
|
&rockchip_suspend {
|
|
status = "okay";
|
|
rockchip,sleep-debug-en = <1>;
|
|
};
|
|
|
|
&saradc {
|
|
status = "okay";
|
|
vref-supply = <&vcc_1v8_s0>;
|
|
};
|
|
|
|
&sdhci {
|
|
bus-width = <8>;
|
|
no-sdio;
|
|
no-sd;
|
|
non-removable;
|
|
max-frequency = <200000000>;
|
|
mmc-hs400-1_8v;
|
|
mmc-hs400-enhanced-strobe;
|
|
status = "okay";
|
|
};
|
|
|
|
&sdmmc {
|
|
max-frequency = <150000000>;
|
|
no-sdio;
|
|
no-mmc;
|
|
bus-width = <4>;
|
|
cap-mmc-highspeed;
|
|
cap-sd-highspeed;
|
|
disable-wp;
|
|
sd-uhs-sdr104;
|
|
vmmc-supply = <&vcc_3v3_sd_s0>;
|
|
vqmmc-supply = <&vccio_sd_s0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
&tsadc {
|
|
status = "okay";
|
|
};
|
|
|
|
&u2phy0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&u2phy1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&u2phy2 {
|
|
status = "okay";
|
|
};
|
|
|
|
&u2phy3 {
|
|
status = "okay";
|
|
};
|
|
|
|
&u2phy0_otg {
|
|
rockchip,typec-vbus-det;
|
|
status = "okay";
|
|
};
|
|
|
|
&u2phy1_otg {
|
|
status = "okay";
|
|
};
|
|
|
|
&u2phy2_host {
|
|
status = "okay";
|
|
};
|
|
|
|
&u2phy3_host {
|
|
status = "okay";
|
|
};
|
|
|
|
&usb_host0_ehci {
|
|
status = "okay";
|
|
};
|
|
|
|
&usb_host0_ohci {
|
|
status = "okay";
|
|
};
|
|
|
|
&usb_host1_ehci {
|
|
status = "okay";
|
|
};
|
|
|
|
&usb_host1_ohci {
|
|
status = "okay";
|
|
};
|
|
|
|
&usbdp_phy0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&usbdp_phy0_dp {
|
|
status = "okay";
|
|
};
|
|
|
|
&usbdp_phy0_u3 {
|
|
status = "okay";
|
|
};
|
|
|
|
&usbdp_phy1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&usbdp_phy1_dp {
|
|
status = "okay";
|
|
};
|
|
|
|
&usbdp_phy1_u3 {
|
|
status = "okay";
|
|
};
|
|
|
|
&usbdrd3_0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&usbdrd_dwc3_0 {
|
|
dr_mode = "peripheral";
|
|
status = "okay";
|
|
};
|
|
|
|
&usbhost3_0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&usbhost_dwc3_0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&usbdrd3_1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&usbdrd_dwc3_1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&vdpu {
|
|
status = "okay";
|
|
};
|
|
|
|
&vdpu_mmu {
|
|
status = "okay";
|
|
};
|
|
|
|
&vepu {
|
|
status = "okay";
|
|
};
|
|
|
|
&vop {
|
|
status = "okay";
|
|
};
|
|
|
|
&vop_mmu {
|
|
status = "okay";
|
|
};
|
|
|
|
/* vp0 & vp1 splice for 8K output */
|
|
&vp0 {
|
|
rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>;
|
|
rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART0>;
|
|
};
|
|
|
|
&vp1 {
|
|
rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>;
|
|
rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART1>;
|
|
};
|
|
|
|
&vp2 {
|
|
rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>;
|
|
rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART2>;
|
|
};
|
|
|
|
&vp3 {
|
|
rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>;
|
|
rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART3>;
|
|
};
|
|
|
|
&i2c0 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c0m2_xfer>;
|
|
};
|
|
|
|
&cpu_l0 {
|
|
cpu-supply = <&vdd_cpu_lit_s0>;
|
|
mem-supply = <&vdd_cpu_lit_mem_s0>;
|
|
};
|
|
|
|
&cpu_b0 {
|
|
cpu-supply = <&vdd_cpu_big0_s0>;
|
|
mem-supply = <&vdd_cpu_big0_mem_s0>;
|
|
};
|
|
|
|
&cpu_b2 {
|
|
cpu-supply = <&vdd_cpu_big1_s0>;
|
|
mem-supply = <&vdd_cpu_big1_mem_s0>;
|
|
};
|