27 lines
981 B
C
27 lines
981 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
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* Author: Lin Huang <hl@rock-chips.com>
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*/
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#ifndef __SOC_ROCKCHIP_SIP_H
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#define __SOC_ROCKCHIP_SIP_H
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#define ROCKCHIP_SIP_DRAM_FREQ 0x82000008
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#define ROCKCHIP_SIP_CONFIG_DRAM_INIT 0x00
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#define ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE 0x01
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#define ROCKCHIP_SIP_CONFIG_DRAM_ROUND_RATE 0x02
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#define ROCKCHIP_SIP_CONFIG_DRAM_SET_AT_SR 0x03
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#define ROCKCHIP_SIP_CONFIG_DRAM_GET_BW 0x04
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#define ROCKCHIP_SIP_CONFIG_DRAM_GET_RATE 0x05
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#define ROCKCHIP_SIP_CONFIG_DRAM_CLR_IRQ 0x06
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#define ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM 0x07
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#define ROCKCHIP_SIP_CONFIG_DRAM_GET_VERSION 0x08
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#define ROCKCHIP_SIP_CONFIG_DRAM_POST_SET_RATE 0x09
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#define ROCKCHIP_SIP_CONFIG_DRAM_SET_MSCH_RL 0x0a
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#define ROCKCHIP_SIP_CONFIG_DRAM_DEBUG 0x0b
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#define ROCKCHIP_SIP_CONFIG_MCU_START 0x0c
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#define ROCKCHIP_SIP_CONFIG_DRAM_GET_FREQ_INFO 0x0e
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#define ROCKCHIP_SIP_CONFIG_DRAM_ADDRMAP_GET 0x10
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#endif
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