1099 lines
26 KiB
Plaintext
1099 lines
26 KiB
Plaintext
/*
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/clock/rk3128-cru.h>
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#include <dt-bindings/media/rockchip_mipi_dsi.h>
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#include "skeleton.dtsi"
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/ {
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compatible = "rockchip,rk3128";
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rockchip,sram = <&sram>;
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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gpio0 = &gpio0;
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gpio1 = &gpio1;
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gpio2 = &gpio2;
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gpio3 = &gpio3;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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spi0 = &spi0;
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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mmc0 = &emmc;
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mmc1 = &sdmmc;
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};
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memory {
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device_type = "memory";
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reg = <0x60000000 0x40000000>;
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};
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arm-pmu {
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compatible = "arm,cortex-a7-pmu";
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "rockchip,rk3128-smp";
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cpu0:cpu@0x000 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x000>;
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operating-points = <
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/* KHz uV */
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816000 1000000
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>;
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#cooling-cells = <2>; /* min followed by max */
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clock-latency = <40000>;
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clocks = <&cru ARMCLK>;
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};
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cpu1:cpu@0x001 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x001>;
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};
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cpu2:cpu@0x002 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x002>;
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};
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cpu3:cpu@0x003 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x003>;
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};
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};
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cpu_axi_bus: cpu_axi_bus {
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compatible = "rockchip,cpu_axi_bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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qos {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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crypto {
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reg = <0x10128080 0x20>;
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};
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core {
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reg = <0x1012a000 0x20>;
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};
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peri {
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reg = <0x1012c000 0x20>;
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};
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gpu {
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reg = <0x1012d000 0x20>;
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};
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vpu {
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reg = <0x1012e000 0x20>;
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};
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rga {
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reg = <0x1012f000 0x20>;
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};
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ebc {
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reg = <0x1012f080 0x20>;
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};
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iep {
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reg = <0x1012f100 0x20>;
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};
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lcdc {
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reg = <0x1012f180 0x20>;
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rockchip,priority = <3 3>;
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};
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vip {
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reg = <0x1012f200 0x20>;
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rockchip,priority = <3 3>;
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};
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};
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msch {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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msch@10128000 {
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reg = <0x10128000 0x20>;
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rockchip,read-latency = <0x3f>;
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};
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};
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};
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psci: psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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amba {
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compatible = "arm,amba-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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ranges;
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pdma: pdma@20078000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x20078000 0x4000>;
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arm,pl330-broken-no-flushp;//2
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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clocks = <&cru ACLK_DMAC>;
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clock-names = "apb_pclk";
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};
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};
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xin24m: xin24m {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "xin24m";
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#clock-cells = <0>;
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};
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xin12m: xin12m {
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compatible = "fixed-clock";
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clocks = <&xin24m>;
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clock-frequency = <12000000>;
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clock-output-names = "xin12m";
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#clock-cells = <0>;
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};
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timer {
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compatible = "arm,armv7-timer";
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arm,cpu-registers-not-fw-configured;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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clock-frequency = <24000000>;
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};
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timer@20044000 {
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compatible = "arm,armv7-timer";
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reg = <0x20044000 0xb8>;
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interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
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rockchip,broadcast = <1>;
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};
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watchdog: wdt@2004c000 {
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compatible = "rockchip,watch dog";
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reg = <0x2004c000 0x100>;
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clock-names = "pclk_wdt";
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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rockchip,irq = <1>;
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rockchip,timeout = <60>;
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rockchip,atboot = <1>;
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rockchip,debug = <0>;
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};
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reset: reset@20000110 {
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compatible = "rockchip,reset";
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reg = <0x20000110 0x24>;
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#reset-cells = <1>;
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};
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sfc: sfc@1020c000 {
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compatible ="rockchip,rksfc","rockchip,sfc";
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reg = <0x1020c000 0x8000>;
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interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
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clock-names = "clk_sfc", "hclk_sfc";
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assigned-clocks = <&cru SCLK_SFC>;
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assigned-clock-rates = <60000000>;
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status = "disabled";
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};
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nandc: nandc@10500000 {
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compatible = "rockchip,rk-nandc";
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reg = <0x10500000 0x4000>;
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
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nandc_id = <0>;
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clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>;
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clock-names = "clk_nandc", "hclk_nandc";
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status = "disabled";
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};
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dmc: dmc@20004000 {
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compatible = "rockchip,rk3128-dmc", "syscon";
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reg = <0x0 0x20004000 0x0 0x1000>;
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};
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cru: clock-controller@20000000 {
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compatible = "rockchip,rk3128-cru";
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reg = <0x20000000 0x1000>;
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rockchip,grf = <&grf>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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assigned-clocks = <&cru PLL_GPLL>;
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assigned-clock-rates = <594000000>;
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};
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uart0: serial0@20060000 {
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compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
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reg = <0x20060000 0x100>;
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clock-frequency = <24000000>;
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clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
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clock-names = "baudclk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
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dmas = <&pdma 2>, <&pdma 3>;
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#dma-cells = <2>;
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};
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uart1: serial1@20064000 {
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compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
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reg = <0x20064000 0x100>;
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interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clock-frequency = <24000000>;
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clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
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clock-names = "baudclk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_xfer>;
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dmas = <&pdma 4>, <&pdma 5>;
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#dma-cells = <2>;
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};
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uart2: serial2@20068000 {
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compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
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reg = <0x20068000 0x100>;
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interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clock-frequency = <24000000>;
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clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
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clock-names = "baudclk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&uart2_xfer>;
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dmas = <&pdma 6>, <&pdma 7>;
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#dma-cells = <2>;
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};
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saradc: saradc@2006c000 {
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compatible = "rockchip,saradc";
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reg = <0x2006c000 0x100>;
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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#io-channel-cells = <1>;
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clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
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clock-names = "saradc", "apb_pclk";
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resets = <&cru SRST_SARADC>;
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reset-names = "saradc-apb";
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status = "disabled";
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};
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pwm0: pwm0@20050000 {
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compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
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reg = <0x20050000 0x10>;
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#pwm-cells = <3>;
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pinctrl-names = "active";
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pinctrl-0 = <&pwm0_pin>;
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clocks = <&cru PCLK_PWM>;
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clock-names = "pwm";
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};
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pwm1: pwm1@20050010 {
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compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
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reg = <0x20050010 0x10>;
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#pwm-cells = <2>;
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pinctrl-names = "active";
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pinctrl-0 = <&pwm1_pin>;
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clocks = <&cru PCLK_PWM>;
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clock-names = "pwm";
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};
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pwm2: pwm2@20050020 {
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compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
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reg = <0x20050020 0x10>;
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#pwm-cells = <2>;
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pinctrl-names = "active";
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pinctrl-0 = <&pwm2_pin>;
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clocks = <&cru PCLK_PWM>;
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clock-names = "pwm";
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};
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pwm3: pwm3@20050030 {
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compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
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reg = <0x20050030 0x10>;
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#pwm-cells = <2>;
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pinctrl-names = "active";
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pinctrl-0 = <&pwm3_pin>;
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clocks = <&cru PCLK_PWM>;
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clock-names = "pwm";
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};
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sram: sram@10080400 {
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compatible = "rockchip,rk3128-smp-sram", "mmio-sram";
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reg = <0x10080400 0x1C00>;
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map-exec;
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map-cacheable;
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};
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pmu: syscon@100a0000 {
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compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
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reg = <0x100a0000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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vop: vop@1010e000 {
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compatible = "rockchip,rk3126-vop";
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reg = <0x1010e000 0x100>, <0x1010ec00 0x400>;
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reg-names = "regs", "gamma_lut";
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru ACLK_LCDC0>, <&cru DCLK_VOP>, <&cru HCLK_LCDC0>;
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clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
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status = "disabled";
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vop_out: port {
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#address-cells = <1>;
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#size-cells = <0>;
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vop_out_lvds: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&lvds_in_vop>;
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};
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vop_out_dsi: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&dsi_in_vop>;
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};
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vop_out_rgb: endpoint@2 {
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reg = <2>;
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remote-endpoint = <&rgb_in_vop>;
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};
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};
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};
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dsi: dsi@10110000 {
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compatible = "rockchip,rk3128-mipi-dsi";
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reg = <0x10110000 0x4000>;
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_MIPI>, <&cru HCLK_VIO_H2P>, <&video_phy>;
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clock-names = "pclk", "h2p", "hs_clk";
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resets = <&cru SRST_VIO_MIPI_DSI>;
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reset-names = "apb";
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phys = <&video_phy>;
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phy-names = "mipi_dphy";
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rockchip,grf = <&grf>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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ports {
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port {
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dsi_in_vop: endpoint {
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remote-endpoint = <&vop_out_dsi>;
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};
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};
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};
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};
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display_subsystem: display-subsystem {
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compatible = "rockchip,display-subsystem";
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ports = <&vop_out>;
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route {
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route_lvds: route-lvds {
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logo,uboot = "logo.bmp";
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logo,kernel = "logo_kernel.bmp";
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logo,mode = "fullscreen";
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charge_logo,mode = "center";
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connect = <&vop_out_lvds>;
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};
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route_dsi: route-dsi {
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logo,uboot = "logo.bmp";
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logo,kernel = "logo_kernel.bmp";
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logo,mode = "fullscreen";
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charge_logo,mode = "center";
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connect = <&vop_out_dsi>;
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};
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};
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};
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gic: interrupt-controller@10139000 {
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compatible = "arm,gic-400";
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interrupt-controller;
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#interrupt-cells = <3>;
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#address-cells = <0>;
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reg = <0x10139000 0x1000>,
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<0x1013a000 0x1000>,
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<0x1013c000 0x2000>,
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<0x1013e000 0x2000>;
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interrupts = <GIC_PPI 9 0xf04>;
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};
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usb_otg: usb@10180000 {
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compatible = "rockchip,rk3128-usb", "rockchip,rk3288-usb",
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"snps,dwc2";
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reg = <0x10180000 0x40000>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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dr_mode = "otg";
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g-use-dma;
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hnp-srp-disable;
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phys = <&u2phy_otg>;
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phy-names = "usb";
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status = "disabled";
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};
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usb_host_ehci: usb@101c0000 {
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compatible = "generic-ehci";
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reg = <0x101c0000 0x20000>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&u2phy_host>;
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phy-names = "usb";
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status = "disabled";
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};
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usb_host_ohci: usb@101e0000 {
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compatible = "generic-ohci";
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reg = <0x101e0000 0x20000>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&u2phy_host>;
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phy-names = "usb";
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status = "disabled";
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};
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sdmmc: dwmmc@10214000 {
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compatible = "rockchip,rk312x-dw-mshc", "rockchip,rk3288-dw-mshc";
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reg = <0x10214000 0x4000>;
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max-frequency = <150000000>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
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<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
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clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
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fifo-depth = <0x100>;
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pinctrl-names = "default";
|
|
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
|
|
bus-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
emmc: dwmmc@1021c000 {
|
|
compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
|
|
reg = <0x1021c000 0x4000>;
|
|
max-frequency = <150000000>;
|
|
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
|
|
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
|
|
clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
|
|
bus-width = <8>;
|
|
default-sample-phase = <158>;
|
|
num-slots = <1>;
|
|
fifo-depth = <0x100>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
|
|
resets = <&cru SRST_EMMC>;
|
|
reset-names = "reset";
|
|
status = "disabled";
|
|
};
|
|
|
|
video_phy: video-phy@20038000 {
|
|
compatible = "rockchip,rk3128-video-phy";
|
|
reg = <0x20038000 0x4000>, <0x10110000 0x4000>;
|
|
clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPIPHY>,
|
|
<&cru PCLK_MIPI>;
|
|
clock-names = "ref", "pclk_phy", "pclk_host";
|
|
#clock-cells = <0>;
|
|
resets = <&cru SRST_MIPIPHY_P>;
|
|
reset-names = "rst";
|
|
#phy-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c0: i2c0@20072000 {
|
|
compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
|
|
reg = <0x20072000 0x1000>;
|
|
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clock-names = "i2c";
|
|
clocks = <&cru PCLK_I2C0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c0_xfer>;
|
|
};
|
|
|
|
i2c1: i2c1@20056000 {
|
|
compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
|
|
reg = <0x20056000 0x1000>;
|
|
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clock-names = "i2c";
|
|
clocks = <&cru PCLK_I2C1>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c1_xfer>;
|
|
};
|
|
|
|
i2c2: i2c2@2005a000 {
|
|
compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
|
|
reg = <0x2005a000 0x1000>;
|
|
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clock-names = "i2c";
|
|
clocks = <&cru PCLK_I2C2>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c2_xfer>;
|
|
};
|
|
|
|
i2c3: i2c3@2005e000 {
|
|
compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
|
|
reg = <0x2005e000 0x1000>;
|
|
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clock-names = "i2c";
|
|
clocks = <&cru PCLK_I2C3>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c3_xfer>;
|
|
};
|
|
|
|
spi0: spi@20074000 {
|
|
compatible = "rockchip,rk3128-spi", "rockchip,rk3288-spi";
|
|
reg = <0x20074000 0x1000>;
|
|
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi0_tx &spi0_rx &spi0_clk &spi0_cs0 &spi0_cs1>;
|
|
clock-names = "spiclk", "apb_pclk";
|
|
dmas = <&pdma 8>, <&pdma 9>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
grf: syscon@20008000 {
|
|
compatible = "rockchip,rk3128-grf", "syscon";
|
|
reg = <0x20008000 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
lvds: lvds {
|
|
compatible = "rockchip,rk3126-lvds";
|
|
phys = <&video_phy>;
|
|
phy-names = "phy";
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
lvds_in_vop: endpoint {
|
|
remote-endpoint = <&vop_out_lvds>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
rgb: rgb {
|
|
compatible = "rockchip,rk3128-rgb";
|
|
phys = <&video_phy>;
|
|
phy-names = "phy";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&lcdc_rgb_pins>;
|
|
pinctrl-1 = <&lcdc_sleep_pins>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
rgb_in_vop: endpoint {
|
|
remote-endpoint = <&vop_out_rgb>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
u2phy: usb2-phy@17c {
|
|
compatible = "rockchip,rk3128-usb2phy";
|
|
reg = <0x017c 0x0c>;
|
|
clocks = <&cru SCLK_OTGPHY0>;
|
|
clock-names = "phyclk";
|
|
#clock-cells = <0>;
|
|
clock-output-names = "usb480m_phy";
|
|
assigned-clocks = <&cru SCLK_USB480M>;
|
|
assigned-clock-parents = <&u2phy>;
|
|
status = "disabled";
|
|
|
|
u2phy_otg: otg-port {
|
|
#phy-cells = <0>;
|
|
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "otg-bvalid", "otg-id",
|
|
"linestate";
|
|
status = "disabled";
|
|
};
|
|
|
|
u2phy_host: host-port {
|
|
#phy-cells = <0>;
|
|
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "linestate";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
|
|
pinctrl: pinctrl@20008000 {
|
|
compatible = "rockchip,rk3128-pinctrl";
|
|
reg = <0x20008000 0xA8>,
|
|
<0x200080A8 0x4C>,
|
|
<0x20008118 0x20>,
|
|
<0x20008100 0x04>;
|
|
reg-names = "base", "mux", "pull", "drv";
|
|
rockchip,grf = <&grf>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
gpio0: gpio0@2007c000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x2007c000 0x100>;
|
|
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO0>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio1: gpio1@20080000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x20080000 0x100>;
|
|
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO1>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio2: gpio2@20084000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x20084000 0x100>;
|
|
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO2>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio3: gpio2@20088000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x20088000 0x100>;
|
|
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO3>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
pcfg_pull_default: pcfg_pull_default {
|
|
bias-pull-pin-default;
|
|
};
|
|
|
|
pcfg_pull_none: pcfg-pull-none {
|
|
bias-disable;
|
|
};
|
|
|
|
emmc {
|
|
emmc_clk: emmc-clk {
|
|
rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
emmc_cmd: emmc-cmd {
|
|
rockchip,pins = <1 RK_PC6 2 &pcfg_pull_default>;
|
|
};
|
|
|
|
emmc_cmd1: emmc-cmd1 {
|
|
rockchip,pins = <2 RK_PA4 2 &pcfg_pull_default>;
|
|
};
|
|
|
|
emmc_pwr: emmc-pwr {
|
|
rockchip,pins = <2 RK_PA5 2 &pcfg_pull_default>;
|
|
};
|
|
|
|
emmc_bus1: emmc-bus1 {
|
|
rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>;
|
|
};
|
|
|
|
emmc_bus4: emmc-bus4 {
|
|
rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
|
|
<1 RK_PD1 2 &pcfg_pull_default>,
|
|
<1 RK_PD2 2 &pcfg_pull_default>,
|
|
<1 RK_PD3 2 &pcfg_pull_default>;
|
|
};
|
|
|
|
emmc_bus8: emmc-bus8 {
|
|
rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
|
|
<1 RK_PD1 2 &pcfg_pull_default>,
|
|
<1 RK_PD2 2 &pcfg_pull_default>,
|
|
<1 RK_PD3 2 &pcfg_pull_default>,
|
|
<1 RK_PD4 2 &pcfg_pull_default>,
|
|
<1 RK_PD5 2 &pcfg_pull_default>,
|
|
<1 RK_PD6 2 &pcfg_pull_default>,
|
|
<1 RK_PD7 2 &pcfg_pull_default>;
|
|
};
|
|
};
|
|
|
|
i2c0 {
|
|
i2c0_xfer: i2c0-xfer {
|
|
rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
|
|
<0 RK_PA1 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c1 {
|
|
i2c1_xfer: i2c1-xfer {
|
|
rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
|
|
<0 RK_PA3 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c2 {
|
|
i2c2_xfer: i2c2-xfer {
|
|
rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>,
|
|
<2 RK_PC5 3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c3 {
|
|
i2c3_xfer: i2c3-xfer {
|
|
rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
|
|
<0 RK_PA7 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
lcdc {
|
|
lcdc_rgb_pins: lcdc-rgb-pins {
|
|
rockchip,pins =
|
|
<2 RK_PB0 1 &pcfg_pull_none>, /* LCDC_DCLK */
|
|
<2 RK_PB1 1 &pcfg_pull_none>, /* LCDC_HSYNC */
|
|
<2 RK_PB2 1 &pcfg_pull_none>, /* LCDC_VSYNC */
|
|
<2 RK_PB3 1 &pcfg_pull_none>, /* LCDC_DEN */
|
|
<2 RK_PB4 1 &pcfg_pull_none>, /* LCDC_DATA10 */
|
|
<2 RK_PB5 1 &pcfg_pull_none>, /* LCDC_DATA11 */
|
|
<2 RK_PB6 1 &pcfg_pull_none>, /* LCDC_DATA12 */
|
|
<2 RK_PB7 1 &pcfg_pull_none>, /* LCDC_DATA13 */
|
|
<2 RK_PC0 1 &pcfg_pull_none>, /* LCDC_DATA14 */
|
|
<2 RK_PC1 1 &pcfg_pull_none>, /* LCDC_DATA15 */
|
|
<2 RK_PC2 1 &pcfg_pull_none>, /* LCDC_DATA16 */
|
|
<2 RK_PC3 1 &pcfg_pull_none>, /* LCDC_DATA17 */
|
|
<2 RK_PC4 1 &pcfg_pull_none>, /* LCDC_DATA18 */
|
|
<2 RK_PC5 1 &pcfg_pull_none>, /* LCDC_DATA19 */
|
|
<2 RK_PC6 1 &pcfg_pull_none>, /* LCDC_DATA20 */
|
|
<2 RK_PC7 1 &pcfg_pull_none>, /* LCDC_DATA21 */
|
|
<2 RK_PD0 1 &pcfg_pull_none>, /* LCDC_DATA22 */
|
|
<2 RK_PD1 1 &pcfg_pull_none>; /* LCDC_DATA23 */
|
|
};
|
|
|
|
lcdc_sleep_pins: lcdc-sleep-pins {
|
|
rockchip,pins =
|
|
<2 RK_PB0 0 &pcfg_pull_none>, /* LCDC_DCLK */
|
|
<2 RK_PB1 0 &pcfg_pull_none>, /* LCDC_HSYNC */
|
|
<2 RK_PB2 0 &pcfg_pull_none>, /* LCDC_VSYNC */
|
|
<2 RK_PB3 0 &pcfg_pull_none>, /* LCDC_DEN */
|
|
<2 RK_PB4 0 &pcfg_pull_none>, /* LCDC_DATA10 */
|
|
<2 RK_PB5 0 &pcfg_pull_none>, /* LCDC_DATA11 */
|
|
<2 RK_PB6 0 &pcfg_pull_none>, /* LCDC_DATA12 */
|
|
<2 RK_PB7 0 &pcfg_pull_none>, /* LCDC_DATA13 */
|
|
<2 RK_PC0 0 &pcfg_pull_none>, /* LCDC_DATA14 */
|
|
<2 RK_PC1 0 &pcfg_pull_none>, /* LCDC_DATA15 */
|
|
<2 RK_PC2 0 &pcfg_pull_none>, /* LCDC_DATA16 */
|
|
<2 RK_PC3 0 &pcfg_pull_none>, /* LCDC_DATA17 */
|
|
<2 RK_PC4 0 &pcfg_pull_none>, /* LCDC_DATA18 */
|
|
<2 RK_PC5 0 &pcfg_pull_none>, /* LCDC_DATA19 */
|
|
<2 RK_PC6 0 &pcfg_pull_none>, /* LCDC_DATA20 */
|
|
<2 RK_PC7 0 &pcfg_pull_none>, /* LCDC_DATA21 */
|
|
<2 RK_PD0 0 &pcfg_pull_none>, /* LCDC_DATA22 */
|
|
<2 RK_PD1 0 &pcfg_pull_none>; /* LCDC_DATA23 */
|
|
};
|
|
};
|
|
|
|
uart0 {
|
|
uart0_xfer: uart0-xfer {
|
|
rockchip,pins = <2 RK_PD2 2 &pcfg_pull_default>,
|
|
<2 RK_PD3 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart0_cts: uart0-cts {
|
|
rockchip,pins = <2 RK_PD5 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart0_rts: uart0-rts {
|
|
rockchip,pins = <0 RK_PC1 2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart1 {
|
|
uart1_xfer: uart1-xfer {
|
|
rockchip,pins = <1 RK_PB1 2 &pcfg_pull_default>,
|
|
<1 RK_PB2 2 &pcfg_pull_default>;
|
|
};
|
|
|
|
uart1_cts: uart1-cts {
|
|
rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart1_rts: uart1-rts {
|
|
rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart2 {
|
|
uart2_xfer: uart2-xfer {
|
|
rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>,
|
|
<1 RK_PC3 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart2_cts: uart2-cts {
|
|
rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart2_rts: uart2-rts {
|
|
rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
sdmmc {
|
|
sdmmc_clk: sdmmc-clk {
|
|
rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
sdmmc_cmd: sdmmc-cmd {
|
|
rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>;
|
|
};
|
|
|
|
sdmmc_wp: sdmmc-wp {
|
|
rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>;
|
|
};
|
|
|
|
sdmmc_pwren: sdmmc-pwren {
|
|
rockchip,pins = <1 RK_PB6 1 &pcfg_pull_default>;
|
|
};
|
|
|
|
sdmmc_bus4: sdmmc-bus4 {
|
|
rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>,
|
|
<1 RK_PC3 1 &pcfg_pull_default>,
|
|
<1 RK_PC4 1 &pcfg_pull_default>,
|
|
<1 RK_PC5 1 &pcfg_pull_default>;
|
|
};
|
|
};
|
|
|
|
sdio {
|
|
sdio_clk: sdio-clk {
|
|
rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
sdio_cmd: sdio-cmd {
|
|
rockchip,pins = <0 RK_PA3 2 &pcfg_pull_default>;
|
|
};
|
|
|
|
sdio_pwren: sdio-pwren {
|
|
rockchip,pins = <0 RK_PD6 1 &pcfg_pull_default>;
|
|
};
|
|
|
|
sdio_bus4: sdio-bus4 {
|
|
rockchip,pins = <1 RK_PA1 2 &pcfg_pull_default>,
|
|
<1 RK_PA2 2 &pcfg_pull_default>,
|
|
<1 RK_PA4 2 &pcfg_pull_default>,
|
|
<1 RK_PA5 2 &pcfg_pull_default>;
|
|
};
|
|
};
|
|
|
|
hdmi {
|
|
hdmii2c_xfer: hdmii2c-xfer {
|
|
rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>,
|
|
<0 RK_PA7 2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2s {
|
|
i2s_bus: i2s-bus {
|
|
rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>,
|
|
<0 RK_PB1 1 &pcfg_pull_none>,
|
|
<0 RK_PB3 1 &pcfg_pull_none>,
|
|
<0 RK_PB4 1 &pcfg_pull_none>,
|
|
<0 RK_PB5 1 &pcfg_pull_none>,
|
|
<0 RK_PB6 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s1_bus: i2s1-bus {
|
|
rockchip,pins = <1 RK_PA0 1 &pcfg_pull_none>,
|
|
<1 RK_PA1 1 &pcfg_pull_none>,
|
|
<1 RK_PA2 1 &pcfg_pull_none>,
|
|
<1 RK_PA3 1 &pcfg_pull_none>,
|
|
<1 RK_PA4 1 &pcfg_pull_none>,
|
|
<1 RK_PA5 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm0 {
|
|
pwm0_pin: pwm0-pin {
|
|
rockchip,pins = <0 RK_PD2 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm1 {
|
|
pwm1_pin: pwm1-pin {
|
|
rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm2 {
|
|
pwm2_pin: pwm2-pin {
|
|
rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm3 {
|
|
pwm3_pin: pwm3-pin {
|
|
rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
gmac {
|
|
rgmii_pins: rgmii-pins {
|
|
rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>,
|
|
<2 RK_PB1 3 &pcfg_pull_default>,
|
|
<2 RK_PB3 3 &pcfg_pull_default>,
|
|
<2 RK_PB4 3 &pcfg_pull_default>,
|
|
<2 RK_PB5 3 &pcfg_pull_default>,
|
|
<2 RK_PB6 3 &pcfg_pull_default>,
|
|
<2 RK_PC0 3 &pcfg_pull_default>,
|
|
<2 RK_PC1 3 &pcfg_pull_default>,
|
|
<2 RK_PC2 3 &pcfg_pull_default>,
|
|
<2 RK_PC3 3 &pcfg_pull_default>,
|
|
<2 RK_PD1 3 &pcfg_pull_default>,
|
|
<2 RK_PC4 4 &pcfg_pull_default>,
|
|
<2 RK_PC5 4 &pcfg_pull_default>,
|
|
<2 RK_PC6 4 &pcfg_pull_default>,
|
|
<2 RK_PC7 4 &pcfg_pull_default>;
|
|
};
|
|
|
|
rmii_pins: rmii-pins {
|
|
rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>,
|
|
<2 RK_PB4 3 &pcfg_pull_default>,
|
|
<2 RK_PB5 3 &pcfg_pull_default>,
|
|
<2 RK_PB6 3 &pcfg_pull_default>,
|
|
<2 RK_PB7 3 &pcfg_pull_default>,
|
|
<2 RK_PC0 3 &pcfg_pull_default>,
|
|
<2 RK_PC1 3 &pcfg_pull_default>,
|
|
<2 RK_PC3 3 &pcfg_pull_default>,
|
|
<2 RK_PC4 3 &pcfg_pull_default>,
|
|
<2 RK_PD1 3 &pcfg_pull_default>;
|
|
};
|
|
};
|
|
|
|
spdif {
|
|
spdif_tx: spdif-tx {
|
|
rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
spi {
|
|
spi0_clk: spi0-clk {
|
|
rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>;
|
|
};
|
|
|
|
spi0_cs0: spi0-cs0 {
|
|
rockchip,pins = <1 RK_PB3 1 &pcfg_pull_default>;
|
|
};
|
|
|
|
spi0_tx: spi0-tx {
|
|
rockchip,pins = <1 RK_PB1 1 &pcfg_pull_default>;
|
|
};
|
|
|
|
spi0_rx: spi0-rx {
|
|
rockchip,pins = <1 RK_PB2 1 &pcfg_pull_default>;
|
|
};
|
|
|
|
spi0_cs1: spi0-cs1 {
|
|
rockchip,pins = <1 RK_PB4 1 &pcfg_pull_default>;
|
|
};
|
|
|
|
spi1_clk: spi1-clk {
|
|
rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>;
|
|
};
|
|
|
|
spi1_cs0: spi1-cs0 {
|
|
rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>;
|
|
};
|
|
|
|
spi1_tx: spi1-tx {
|
|
rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>;
|
|
};
|
|
|
|
spi1_rx: spi1-rx {
|
|
rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>;
|
|
};
|
|
|
|
spi1_cs1: spi1-cs1 {
|
|
rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>;
|
|
};
|
|
|
|
spi2_clk: spi2-clk {
|
|
rockchip,pins = <0 RK_PB1 2 &pcfg_pull_default>;
|
|
};
|
|
|
|
spi2_cs0: spi2-cs0 {
|
|
rockchip,pins = <0 RK_PB6 2 &pcfg_pull_default>;
|
|
};
|
|
|
|
spi2_tx: spi2-tx {
|
|
rockchip,pins = <0 RK_PB3 2 &pcfg_pull_default>;
|
|
};
|
|
|
|
spi2_rx: spi2-rx {
|
|
rockchip,pins = <0 RK_PB5 2 &pcfg_pull_default>;
|
|
};
|
|
};
|
|
};
|
|
};
|