977 lines
25 KiB
C
977 lines
25 KiB
C
/*
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <errno.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/cru_rk3128.h>
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#include <asm/arch/hardware.h>
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#include <bitfield.h>
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#include <dm/lists.h>
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#include <dt-bindings/clock/rk3128-cru.h>
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#include <linux/log2.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
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#ifndef CONFIG_SPL_BUILD
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#define RK3128_CLK_DUMP(_id, _name, _iscru) \
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{ \
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.id = _id, \
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.name = _name, \
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.is_cru = _iscru, \
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}
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#endif
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static struct rockchip_pll_rate_table rk3128_pll_rates[] = {
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/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
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#ifndef CONFIG_SPL_BUILD
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RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
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RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0),
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RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
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#endif
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RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
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RK3036_PLL_RATE(800000000, 1, 200, 6, 1, 1, 0),
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RK3036_PLL_RATE(600000000, 1, 75, 3, 1, 1, 0),
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RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0),
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RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0),
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RK3036_PLL_RATE(400000000, 1, 100, 6, 1, 1, 0),
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{ /* sentinel */ },
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};
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#define RK3128_CPUCLK_RATE(_rate, _aclk_div, _pclk_div) \
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{ \
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.rate = _rate##U, \
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.aclk_div = _aclk_div, \
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.pclk_div = _pclk_div, \
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}
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static struct rockchip_cpu_rate_table rk3128_cpu_rates[] = {
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RK3128_CPUCLK_RATE(1200000000, 1, 5),
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RK3128_CPUCLK_RATE(1008000000, 1, 5),
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RK3128_CPUCLK_RATE(816000000, 1, 3),
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RK3128_CPUCLK_RATE(600000000, 1, 3),
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};
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#ifndef CONFIG_SPL_BUILD
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static const struct rk3128_clk_info clks_dump[] = {
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RK3128_CLK_DUMP(PLL_APLL, "apll", true),
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RK3128_CLK_DUMP(PLL_DPLL, "dpll", true),
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RK3128_CLK_DUMP(PLL_CPLL, "cpll", true),
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RK3128_CLK_DUMP(PLL_GPLL, "gpll", true),
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RK3128_CLK_DUMP(ARMCLK, "armclk", true),
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RK3128_CLK_DUMP(ACLK_CPU, "aclk_cpu", true),
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RK3128_CLK_DUMP(HCLK_CPU, "hclk_cpu", true),
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RK3128_CLK_DUMP(PCLK_CPU, "pclk_cpu", true),
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RK3128_CLK_DUMP(ACLK_PERI, "aclk_peri", true),
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RK3128_CLK_DUMP(HCLK_PERI, "hclk_peri", true),
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RK3128_CLK_DUMP(PCLK_PERI, "pclk_peri", true),
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};
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#endif
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static struct rockchip_pll_clock rk3128_pll_clks[] = {
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[APLL] = PLL(pll_rk3036, PLL_APLL, RK2928_PLL_CON(0),
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RK2928_MODE_CON, 0, 10, 0, rk3128_pll_rates),
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[DPLL] = PLL(pll_rk3036, PLL_DPLL, RK2928_PLL_CON(4),
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RK2928_MODE_CON, 4, 10, 0, NULL),
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[CPLL] = PLL(pll_rk3036, PLL_CPLL, RK2928_PLL_CON(8),
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RK2928_MODE_CON, 8, 10, 0, rk3128_pll_rates),
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[GPLL] = PLL(pll_rk3036, PLL_GPLL, RK2928_PLL_CON(12),
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RK2928_MODE_CON, 12, 10, 0, rk3128_pll_rates),
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};
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static ulong rk3128_armclk_set_clk(struct rk3128_clk_priv *priv, ulong hz)
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{
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struct rk3128_cru *cru = priv->cru;
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const struct rockchip_cpu_rate_table *rate;
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ulong old_rate;
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rate = rockchip_get_cpu_settings(rk3128_cpu_rates, hz);
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if (!rate) {
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printf("%s unsupported rate\n", __func__);
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return -EINVAL;
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}
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/*
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* select apll as cpu/core clock pll source and
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* set up dependent divisors for PERI and ACLK clocks.
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* core hz : apll = 1:1
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*/
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old_rate = rockchip_pll_get_rate(&rk3128_pll_clks[APLL],
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priv->cru, APLL);
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if (old_rate > hz) {
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if (rockchip_pll_set_rate(&rk3128_pll_clks[APLL],
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priv->cru, APLL, hz))
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return -EINVAL;
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rk_clrsetreg(&cru->cru_clksel_con[0],
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CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK,
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CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
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0 << CORE_DIV_CON_SHIFT);
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rk_clrsetreg(&cru->cru_clksel_con[1],
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CORE_ACLK_DIV_MASK | CORE_DBG_DIV_MASK,
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rate->aclk_div << CORE_ACLK_DIV_SHIFT |
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rate->pclk_div << CORE_DBG_DIV_SHIFT);
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} else if (old_rate < hz) {
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rk_clrsetreg(&cru->cru_clksel_con[1],
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CORE_ACLK_DIV_MASK | CORE_DBG_DIV_MASK,
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rate->aclk_div << CORE_ACLK_DIV_SHIFT |
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rate->pclk_div << CORE_DBG_DIV_SHIFT);
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rk_clrsetreg(&cru->cru_clksel_con[0],
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CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK,
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CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
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0 << CORE_DIV_CON_SHIFT);
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if (rockchip_pll_set_rate(&rk3128_pll_clks[APLL],
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priv->cru, APLL, hz))
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return -EINVAL;
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}
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return rockchip_pll_get_rate(&rk3128_pll_clks[APLL], priv->cru, APLL);
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}
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static ulong rockchip_mmc_get_clk(struct rk3128_clk_priv *priv,
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int periph)
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{
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struct rk3128_cru *cru = priv->cru;
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uint src_rate;
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uint div, mux;
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u32 con;
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switch (periph) {
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case HCLK_EMMC:
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case SCLK_EMMC:
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case SCLK_EMMC_SAMPLE:
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con = readl(&cru->cru_clksel_con[12]);
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mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
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div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
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break;
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case HCLK_SDMMC:
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case SCLK_SDMMC:
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case SCLK_SDMMC_SAMPLE:
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con = readl(&cru->cru_clksel_con[11]);
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mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
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div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
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break;
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case HCLK_SDIO:
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case SCLK_SDIO:
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case SCLK_SDIO_SAMPLE:
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con = readl(&cru->cru_clksel_con[12]);
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mux = (con & SDIO_PLL_MASK) >> SDIO_PLL_SHIFT;
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div = (con & SDIO_DIV_MASK) >> SDIO_DIV_SHIFT;
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break;
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default:
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return -EINVAL;
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}
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src_rate = mux == EMMC_SEL_24M ? OSC_HZ : priv->gpll_hz;
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return DIV_TO_RATE(src_rate, div);
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}
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static ulong rockchip_mmc_set_clk(struct rk3128_clk_priv *priv,
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int periph, uint freq)
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{
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struct rk3128_cru *cru = priv->cru;
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int src_clk_div;
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int mux;
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/* mmc clock defaulg div 2 internal, need provide double in cru */
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src_clk_div = DIV_ROUND_UP(priv->gpll_hz / 2, freq);
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if (src_clk_div > 128) {
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src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
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mux = EMMC_SEL_24M;
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} else {
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mux = EMMC_SEL_GPLL;
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}
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switch (periph) {
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case HCLK_EMMC:
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case SCLK_EMMC:
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rk_clrsetreg(&cru->cru_clksel_con[12],
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EMMC_PLL_MASK | EMMC_DIV_MASK,
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mux << EMMC_PLL_SHIFT |
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(src_clk_div - 1) << EMMC_DIV_SHIFT);
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break;
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case HCLK_SDMMC:
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case SCLK_SDMMC:
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rk_clrsetreg(&cru->cru_clksel_con[11],
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MMC0_PLL_MASK | MMC0_DIV_MASK,
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mux << MMC0_PLL_SHIFT |
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(src_clk_div - 1) << MMC0_DIV_SHIFT);
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break;
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case HCLK_SDIO:
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case SCLK_SDIO:
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rk_clrsetreg(&cru->cru_clksel_con[12],
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SDIO_PLL_MASK | SDIO_DIV_MASK,
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mux << SDIO_PLL_SHIFT |
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(src_clk_div - 1) << SDIO_DIV_SHIFT);
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break;
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default:
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return -EINVAL;
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}
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return rockchip_mmc_get_clk(priv, periph);
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}
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static ulong rk3128_peri_get_clk(struct rk3128_clk_priv *priv, ulong clk_id)
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{
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struct rk3128_cru *cru = priv->cru;
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u32 div, con, parent;
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switch (clk_id) {
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case ACLK_PERI:
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con = readl(&cru->cru_clksel_con[10]);
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div = (con & ACLK_PERI_DIV_MASK) >> ACLK_PERI_DIV_SHIFT;
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parent = priv->gpll_hz;
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break;
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case PCLK_PERI:
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case PCLK_I2C0:
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case PCLK_I2C1:
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case PCLK_I2C2:
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case PCLK_I2C3:
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case PCLK_PWM:
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case PCLK_WDT:
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con = readl(&cru->cru_clksel_con[10]);
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div = (con & PCLK_PERI_DIV_MASK) >> PCLK_PERI_DIV_SHIFT;
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parent = rk3128_peri_get_clk(priv, ACLK_PERI);
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break;
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case HCLK_PERI:
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con = readl(&cru->cru_clksel_con[10]);
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div = (con & HCLK_PERI_DIV_MASK) >> HCLK_PERI_DIV_SHIFT;
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parent = rk3128_peri_get_clk(priv, ACLK_PERI);
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break;
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default:
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printf("do not support this peripheral bus\n");
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return -EINVAL;
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}
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return DIV_TO_RATE(parent, div);
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}
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static ulong rk3128_peri_set_clk(struct rk3128_clk_priv *priv,
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ulong clk_id, uint hz)
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{
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struct rk3128_cru *cru = priv->cru;
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int src_clk_div;
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switch (clk_id) {
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case ACLK_PERI:
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src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz);
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assert(src_clk_div - 1 < 32);
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rk_clrsetreg(&cru->cru_clksel_con[10],
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PERI_PLL_SEL_MASK | ACLK_PERI_DIV_MASK,
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PERI_PLL_SEL_GPLL << PERI_PLL_SEL_SHIFT |
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(src_clk_div - 1) << ACLK_PERI_DIV_SHIFT);
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break;
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case PCLK_I2C0:
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case PCLK_I2C1:
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case PCLK_I2C2:
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case PCLK_I2C3:
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case PCLK_PWM:
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case PCLK_PERI:
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src_clk_div = DIV_ROUND_UP(rk3128_peri_get_clk(priv,
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ACLK_PERI),
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hz);
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assert(src_clk_div - 1 < 3);
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rk_clrsetreg(&cru->cru_clksel_con[10],
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PCLK_PERI_DIV_MASK,
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(src_clk_div - 1) << PCLK_PERI_DIV_SHIFT);
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break;
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case HCLK_PERI:
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src_clk_div = DIV_ROUND_UP(rk3128_peri_get_clk(priv,
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ACLK_PERI),
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hz);
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assert(src_clk_div - 1 < 7);
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rk_clrsetreg(&cru->cru_clksel_con[10],
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HCLK_PERI_DIV_MASK,
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(src_clk_div - 1) << HCLK_PERI_DIV_SHIFT);
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break;
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default:
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printf("do not support this peripheral bus\n");
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return -EINVAL;
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}
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return rk3128_peri_get_clk(priv, clk_id);
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}
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static ulong rk3128_bus_get_clk(struct rk3128_clk_priv *priv, ulong clk_id)
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{
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struct rk3128_cru *cru = priv->cru;
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u32 div, con, parent;
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switch (clk_id) {
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case ACLK_CPU:
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con = readl(&cru->cru_clksel_con[0]);
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div = (con & ACLK_BUS_DIV_MASK) >> ACLK_BUS_DIV_SHIFT;
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parent = priv->gpll_hz;
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break;
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case PCLK_CPU:
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con = readl(&cru->cru_clksel_con[1]);
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div = (con & PCLK_BUS_DIV_MASK) >> PCLK_BUS_DIV_SHIFT;
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parent = rk3128_bus_get_clk(priv, ACLK_CPU);
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break;
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case HCLK_CPU:
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con = readl(&cru->cru_clksel_con[1]);
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div = (con & HCLK_BUS_DIV_MASK) >> HCLK_BUS_DIV_SHIFT;
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parent = rk3128_bus_get_clk(priv, ACLK_CPU);
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break;
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default:
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printf("do not support this peripheral bus\n");
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return -EINVAL;
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}
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return DIV_TO_RATE(parent, div);
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}
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static ulong rk3128_bus_set_clk(struct rk3128_clk_priv *priv,
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ulong clk_id, uint hz)
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{
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struct rk3128_cru *cru = priv->cru;
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int src_clk_div;
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switch (clk_id) {
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case ACLK_CPU:
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src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz);
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assert(src_clk_div - 1 < 32);
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rk_clrsetreg(&cru->cru_clksel_con[0],
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BUS_PLL_SEL_MASK | ACLK_BUS_DIV_MASK,
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BUS_PLL_SEL_GPLL << BUS_PLL_SEL_SHIFT |
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(src_clk_div - 1) << ACLK_BUS_DIV_SHIFT);
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break;
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case PCLK_CPU:
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src_clk_div = DIV_ROUND_UP(rk3128_bus_get_clk(priv,
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ACLK_CPU),
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hz);
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assert(src_clk_div - 1 < 3);
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rk_clrsetreg(&cru->cru_clksel_con[1],
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PCLK_BUS_DIV_MASK,
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(src_clk_div - 1) << PCLK_BUS_DIV_SHIFT);
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break;
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case HCLK_CPU:
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src_clk_div = DIV_ROUND_UP(rk3128_bus_get_clk(priv,
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ACLK_CPU),
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hz);
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assert(src_clk_div - 1 < 7);
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rk_clrsetreg(&cru->cru_clksel_con[1],
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HCLK_BUS_DIV_MASK,
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(src_clk_div - 1) << HCLK_BUS_DIV_SHIFT);
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break;
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default:
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printf("do not support this peripheral bus\n");
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return -EINVAL;
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}
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return rk3128_bus_get_clk(priv, clk_id);
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}
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static ulong rk3128_spi_get_clk(struct rk3128_clk_priv *priv)
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{
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struct rk3128_cru *cru = priv->cru;
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u32 div, con, parent;
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con = readl(&cru->cru_clksel_con[25]);
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div = (con & SPI_DIV_MASK) >> SPI_DIV_SHIFT;
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parent = priv->gpll_hz;
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return DIV_TO_RATE(parent, div);
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}
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static ulong rk3128_spi_set_clk(struct rk3128_clk_priv *priv, ulong hz)
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{
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struct rk3128_cru *cru = priv->cru;
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int div;
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div = DIV_ROUND_UP(priv->gpll_hz, hz);
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assert(div - 1 < 128);
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rk_clrsetreg(&cru->cru_clksel_con[25],
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SPI_PLL_SEL_MASK | SPI_DIV_MASK,
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SPI_PLL_SEL_GPLL << SPI_PLL_SEL_SHIFT |
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(div - 1) << SPI_DIV_SHIFT);
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return rk3128_spi_get_clk(priv);
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}
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#ifndef CONFIG_SPL_BUILD
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static ulong rk3128_saradc_get_clk(struct rk3128_clk_priv *priv)
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{
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struct rk3128_cru *cru = priv->cru;
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u32 div, val;
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val = readl(&cru->cru_clksel_con[24]);
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div = bitfield_extract(val, SARADC_DIV_CON_SHIFT,
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SARADC_DIV_CON_WIDTH);
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return DIV_TO_RATE(OSC_HZ, div);
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}
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static ulong rk3128_saradc_set_clk(struct rk3128_clk_priv *priv, uint hz)
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{
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struct rk3128_cru *cru = priv->cru;
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int src_clk_div;
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src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
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assert(src_clk_div < 128);
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|
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rk_clrsetreg(&cru->cru_clksel_con[24],
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SARADC_DIV_CON_MASK,
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src_clk_div << SARADC_DIV_CON_SHIFT);
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return rk3128_saradc_get_clk(priv);
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}
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#define RK3128_LCDC_PLL_LIMIT 600000000
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static ulong rk3128_vop_set_clk(struct rk3128_clk_priv *priv,
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ulong clk_id, uint hz)
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{
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struct rk3128_cru *cru = priv->cru;
|
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int src_clk_div;
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|
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src_clk_div = GPLL_HZ / hz;
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assert(src_clk_div - 1 < 31);
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|
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switch (clk_id) {
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case ACLK_LCDC0:
|
|
case ACLK_VIO0:
|
|
rk_clrsetreg(&cru->cru_clksel_con[31],
|
|
VIO0_PLL_MASK | VIO0_DIV_MASK,
|
|
VIO0_SEL_GPLL << VIO0_PLL_SHIFT |
|
|
(src_clk_div - 1) << VIO0_DIV_SHIFT);
|
|
break;
|
|
case ACLK_VIO1:
|
|
rk_clrsetreg(&cru->cru_clksel_con[31],
|
|
VIO1_PLL_MASK | VIO1_DIV_MASK,
|
|
VIO1_SEL_GPLL << VIO1_PLL_SHIFT |
|
|
(src_clk_div - 1) << VIO1_DIV_SHIFT);
|
|
break;
|
|
case DCLK_VOP:
|
|
src_clk_div = DIV_ROUND_UP(RK3128_LCDC_PLL_LIMIT, hz);
|
|
rockchip_pll_set_rate(&rk3128_pll_clks[CPLL],
|
|
priv->cru, CPLL, src_clk_div * hz);
|
|
rk_clrsetreg(&cru->cru_clksel_con[27],
|
|
DCLK_VOP_SEL_MASK | DCLK_VOP_DIV_CON_MASK,
|
|
DCLK_VOP_PLL_SEL_CPLL << DCLK_VOP_SEL_SHIFT |
|
|
(src_clk_div - 1) << DCLK_VOP_DIV_CON_SHIFT);
|
|
break;
|
|
default:
|
|
printf("do not support this vop freq\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
return hz;
|
|
}
|
|
|
|
static ulong rk3128_vop_get_rate(struct rk3128_clk_priv *priv, ulong clk_id)
|
|
{
|
|
struct rk3128_cru *cru = priv->cru;
|
|
u32 div, con, parent;
|
|
|
|
switch (clk_id) {
|
|
case ACLK_LCDC0:
|
|
case ACLK_VIO0:
|
|
con = readl(&cru->cru_clksel_con[31]);
|
|
div = con & 0x1f;
|
|
parent = GPLL_HZ;
|
|
break;
|
|
case ACLK_VIO1:
|
|
con = readl(&cru->cru_clksel_con[31]);
|
|
div = (con >> 8) & 0x1f;
|
|
parent = GPLL_HZ;
|
|
break;
|
|
case DCLK_VOP:
|
|
con = readl(&cru->cru_clksel_con[27]);
|
|
div = (con & DCLK_VOP_DIV_CON_MASK) >> DCLK_VOP_DIV_CON_SHIFT;
|
|
parent = rockchip_pll_get_rate(&rk3128_pll_clks[CPLL],
|
|
priv->cru, CPLL);
|
|
break;
|
|
default:
|
|
return -ENOENT;
|
|
}
|
|
return DIV_TO_RATE(parent, div);
|
|
}
|
|
|
|
static ulong rk3128_crypto_get_rate(struct rk3128_clk_priv *priv)
|
|
{
|
|
struct rk3128_cru *cru = priv->cru;
|
|
u32 div, val;
|
|
|
|
val = readl(&cru->cru_clksel_con[24]);
|
|
div = (val & CLK_CRYPTO_DIV_CON_MASK) >> CLK_CRYPTO_DIV_CON_SHIFT;
|
|
|
|
return DIV_TO_RATE(rk3128_bus_get_clk(priv, ACLK_CPU), div);
|
|
}
|
|
|
|
static ulong rk3128_crypto_set_rate(struct rk3128_clk_priv *priv,
|
|
uint hz)
|
|
{
|
|
struct rk3128_cru *cru = priv->cru;
|
|
int src_clk_div;
|
|
uint p_rate;
|
|
|
|
p_rate = rk3128_bus_get_clk(priv, ACLK_CPU);
|
|
src_clk_div = DIV_ROUND_UP(p_rate, hz) - 1;
|
|
assert(src_clk_div < 3);
|
|
|
|
rk_clrsetreg(&cru->cru_clksel_con[24],
|
|
CLK_CRYPTO_DIV_CON_MASK,
|
|
src_clk_div << CLK_CRYPTO_DIV_CON_SHIFT);
|
|
|
|
return rk3128_crypto_get_rate(priv);
|
|
}
|
|
#endif
|
|
|
|
static ulong rk3128_clk_get_rate(struct clk *clk)
|
|
{
|
|
struct rk3128_clk_priv *priv = dev_get_priv(clk->dev);
|
|
ulong rate = 0;
|
|
|
|
switch (clk->id) {
|
|
case PLL_APLL:
|
|
case PLL_DPLL:
|
|
case PLL_CPLL:
|
|
case PLL_GPLL:
|
|
rate = rockchip_pll_get_rate(&rk3128_pll_clks[clk->id - 1],
|
|
priv->cru, clk->id - 1);
|
|
break;
|
|
case ARMCLK:
|
|
rate = rockchip_pll_get_rate(&rk3128_pll_clks[APLL],
|
|
priv->cru, APLL);
|
|
break;
|
|
case HCLK_EMMC:
|
|
case SCLK_EMMC:
|
|
case HCLK_SDMMC:
|
|
case SCLK_SDMMC:
|
|
case HCLK_SDIO:
|
|
case SCLK_SDIO:
|
|
rate = rockchip_mmc_get_clk(priv, clk->id);
|
|
break;
|
|
case ACLK_PERI:
|
|
case HCLK_PERI:
|
|
case PCLK_PERI:
|
|
case PCLK_I2C0:
|
|
case PCLK_I2C1:
|
|
case PCLK_I2C2:
|
|
case PCLK_I2C3:
|
|
case PCLK_PWM:
|
|
case PCLK_WDT:
|
|
rate = rk3128_peri_get_clk(priv, clk->id);
|
|
break;
|
|
case ACLK_CPU:
|
|
case HCLK_CPU:
|
|
case PCLK_CPU:
|
|
rate = rk3128_bus_get_clk(priv, clk->id);
|
|
break;
|
|
case SCLK_SPI0:
|
|
rate = rk3128_spi_get_clk(priv);
|
|
break;
|
|
#ifndef CONFIG_SPL_BUILD
|
|
case SCLK_SARADC:
|
|
rate = rk3128_saradc_get_clk(priv);
|
|
break;
|
|
case DCLK_VOP:
|
|
case ACLK_VIO0:
|
|
case ACLK_VIO1:
|
|
case ACLK_LCDC0:
|
|
rate = rk3128_vop_get_rate(priv, clk->id);
|
|
break;
|
|
case SCLK_CRYPTO:
|
|
rate = rk3128_crypto_get_rate(priv);
|
|
break;
|
|
#endif
|
|
default:
|
|
return -ENOENT;
|
|
}
|
|
return rate;
|
|
}
|
|
|
|
static ulong rk3128_clk_set_rate(struct clk *clk, ulong rate)
|
|
{
|
|
struct rk3128_clk_priv *priv = dev_get_priv(clk->dev);
|
|
ulong ret = 0;
|
|
|
|
switch (clk->id) {
|
|
case PLL_APLL:
|
|
case PLL_DPLL:
|
|
case PLL_CPLL:
|
|
ret = rockchip_pll_set_rate(&rk3128_pll_clks[clk->id - 1],
|
|
priv->cru, clk->id - 1, rate);
|
|
case PLL_GPLL:
|
|
ret = rockchip_pll_set_rate(&rk3128_pll_clks[GPLL],
|
|
priv->cru, GPLL, rate);
|
|
priv->gpll_hz = rate;
|
|
break;
|
|
case ARMCLK:
|
|
if (priv->armclk_hz)
|
|
ret = rk3128_armclk_set_clk(priv, rate);
|
|
priv->armclk_hz = rate;
|
|
break;
|
|
case HCLK_EMMC:
|
|
case SCLK_EMMC:
|
|
case SCLK_EMMC_SAMPLE:
|
|
case HCLK_SDMMC:
|
|
case SCLK_SDMMC:
|
|
case SCLK_SDMMC_SAMPLE:
|
|
case HCLK_SDIO:
|
|
case SCLK_SDIO:
|
|
case SCLK_SDIO_SAMPLE:
|
|
ret = rockchip_mmc_set_clk(priv, clk->id, rate);
|
|
break;
|
|
case ACLK_PERI:
|
|
case PCLK_PERI:
|
|
case HCLK_PERI:
|
|
case PCLK_I2C0:
|
|
case PCLK_I2C1:
|
|
case PCLK_I2C2:
|
|
case PCLK_I2C3:
|
|
case PCLK_PWM:
|
|
ret = rk3128_peri_set_clk(priv, clk->id, rate);
|
|
break;
|
|
case ACLK_CPU:
|
|
case HCLK_CPU:
|
|
case PCLK_CPU:
|
|
ret = rk3128_bus_set_clk(priv, clk->id, rate);
|
|
break;
|
|
case SCLK_SPI0:
|
|
rate = rk3128_spi_set_clk(priv, rate);
|
|
break;
|
|
#ifndef CONFIG_SPL_BUILD
|
|
case SCLK_SARADC:
|
|
ret = rk3128_saradc_set_clk(priv, rate);
|
|
break;
|
|
case DCLK_VOP:
|
|
case ACLK_VIO0:
|
|
case ACLK_VIO1:
|
|
case ACLK_LCDC0:
|
|
ret = rk3128_vop_set_clk(priv, clk->id, rate);
|
|
break;
|
|
case SCLK_CRYPTO:
|
|
ret = rk3128_crypto_set_rate(priv, rate);
|
|
break;
|
|
#endif
|
|
default:
|
|
return -ENOENT;
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
#define ROCKCHIP_MMC_DELAY_SEL BIT(10)
|
|
#define ROCKCHIP_MMC_DEGREE_MASK 0x3
|
|
#define ROCKCHIP_MMC_DELAYNUM_OFFSET 2
|
|
#define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET)
|
|
|
|
#define PSECS_PER_SEC 1000000000000LL
|
|
/*
|
|
* Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
|
|
* simplify calculations. So 45degs could be anywhere between 33deg and 57.8deg.
|
|
*/
|
|
#define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60
|
|
|
|
int rk3128_mmc_get_phase(struct clk *clk)
|
|
{
|
|
struct rk3128_clk_priv *priv = dev_get_priv(clk->dev);
|
|
struct rk3128_cru *cru = priv->cru;
|
|
u32 raw_value, delay_num;
|
|
u16 degrees = 0;
|
|
ulong rate;
|
|
|
|
rate = rk3128_clk_get_rate(clk);
|
|
|
|
if (rate < 0)
|
|
return rate;
|
|
|
|
if (clk->id == SCLK_EMMC_SAMPLE)
|
|
raw_value = readl(&cru->cru_emmc_con[1]);
|
|
else if (clk->id == SCLK_SDMMC_SAMPLE)
|
|
raw_value = readl(&cru->cru_sdmmc_con[1]);
|
|
else
|
|
raw_value = readl(&cru->cru_sdio_con[1]);
|
|
|
|
raw_value >>= 1;
|
|
degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90;
|
|
|
|
if (raw_value & ROCKCHIP_MMC_DELAY_SEL) {
|
|
/* degrees/delaynum * 10000 */
|
|
unsigned long factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) *
|
|
36 * (rate / 1000000);
|
|
|
|
delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK);
|
|
delay_num >>= ROCKCHIP_MMC_DELAYNUM_OFFSET;
|
|
degrees += DIV_ROUND_CLOSEST(delay_num * factor, 10000);
|
|
}
|
|
|
|
return degrees % 360;
|
|
}
|
|
|
|
int rk3128_mmc_set_phase(struct clk *clk, u32 degrees)
|
|
{
|
|
struct rk3128_clk_priv *priv = dev_get_priv(clk->dev);
|
|
struct rk3128_cru *cru = priv->cru;
|
|
u8 nineties, remainder, delay_num;
|
|
u32 raw_value, delay;
|
|
ulong rate;
|
|
|
|
rate = rk3128_clk_get_rate(clk);
|
|
|
|
if (rate < 0)
|
|
return rate;
|
|
|
|
nineties = degrees / 90;
|
|
remainder = (degrees % 90);
|
|
|
|
/*
|
|
* Convert to delay; do a little extra work to make sure we
|
|
* don't overflow 32-bit / 64-bit numbers.
|
|
*/
|
|
delay = 10000000; /* PSECS_PER_SEC / 10000 / 10 */
|
|
delay *= remainder;
|
|
delay = DIV_ROUND_CLOSEST(delay, (rate / 1000) * 36 *
|
|
(ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10));
|
|
|
|
delay_num = (u8)min_t(u32, delay, 255);
|
|
|
|
raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0;
|
|
raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET;
|
|
raw_value |= nineties;
|
|
|
|
raw_value <<= 1;
|
|
if (clk->id == SCLK_EMMC_SAMPLE)
|
|
writel(raw_value | 0xffff0000, &cru->cru_emmc_con[1]);
|
|
else if (clk->id == SCLK_SDMMC_SAMPLE)
|
|
writel(raw_value | 0xffff0000, &cru->cru_sdmmc_con[1]);
|
|
else
|
|
writel(raw_value | 0xffff0000, &cru->cru_sdio_con[1]);
|
|
|
|
debug("mmc set_phase(%d) delay_nums=%u reg=%#x actual_degrees=%d\n",
|
|
degrees, delay_num, raw_value, rk3128_mmc_get_phase(clk));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rk3128_clk_get_phase(struct clk *clk)
|
|
{
|
|
int ret;
|
|
|
|
debug("%s %ld\n", __func__, clk->id);
|
|
switch (clk->id) {
|
|
case SCLK_EMMC_SAMPLE:
|
|
case SCLK_SDMMC_SAMPLE:
|
|
case SCLK_SDIO_SAMPLE:
|
|
ret = rk3128_mmc_get_phase(clk);
|
|
break;
|
|
default:
|
|
return -ENOENT;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int rk3128_clk_set_phase(struct clk *clk, int degrees)
|
|
{
|
|
int ret;
|
|
|
|
debug("%s %ld\n", __func__, clk->id);
|
|
switch (clk->id) {
|
|
case SCLK_EMMC_SAMPLE:
|
|
case SCLK_SDMMC_SAMPLE:
|
|
case SCLK_SDIO_SAMPLE:
|
|
ret = rk3128_mmc_set_phase(clk, degrees);
|
|
break;
|
|
default:
|
|
return -ENOENT;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static struct clk_ops rk3128_clk_ops = {
|
|
.get_rate = rk3128_clk_get_rate,
|
|
.set_rate = rk3128_clk_set_rate,
|
|
.get_phase = rk3128_clk_get_phase,
|
|
.set_phase = rk3128_clk_set_phase,
|
|
};
|
|
|
|
static int rk3128_clk_ofdata_to_platdata(struct udevice *dev)
|
|
{
|
|
struct rk3128_clk_priv *priv = dev_get_priv(dev);
|
|
|
|
priv->cru = dev_read_addr_ptr(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void rkclk_init(struct rk3128_clk_priv *priv)
|
|
{
|
|
if (rockchip_pll_get_rate(&rk3128_pll_clks[APLL],
|
|
priv->cru, APLL) != APLL_HZ)
|
|
rk3128_armclk_set_clk(priv, APLL_HZ);
|
|
|
|
priv->gpll_hz = rockchip_pll_get_rate(&rk3128_pll_clks[GPLL],
|
|
priv->cru, GPLL);
|
|
rk3128_bus_set_clk(priv, ACLK_CPU, ACLK_BUS_HZ / 2);
|
|
rk3128_peri_set_clk(priv, ACLK_PERI, ACLK_PERI_HZ / 2);
|
|
rockchip_pll_set_rate(&rk3128_pll_clks[GPLL],
|
|
priv->cru, GPLL, GPLL_HZ);
|
|
priv->gpll_hz = GPLL_HZ;
|
|
rk_clrsetreg(&priv->cru->cru_clksel_con[2],
|
|
NANDC_PLL_SEL_MASK | NANDC_CLK_DIV_MASK,
|
|
NANDC_PLL_SEL_GPLL << NANDC_PLL_SEL_SHIFT |
|
|
3 << NANDC_CLK_DIV_SHIFT);
|
|
rk_clrsetreg(&priv->cru->cru_clksel_con[11],
|
|
SFC_PLL_SEL_MASK | SFC_CLK_DIV_MASK,
|
|
SFC_PLL_SEL_GPLL << SFC_PLL_SEL_SHIFT |
|
|
9 << SFC_CLK_DIV_SHIFT);
|
|
|
|
rk3128_bus_set_clk(priv, ACLK_CPU, ACLK_BUS_HZ);
|
|
rk3128_bus_set_clk(priv, HCLK_CPU, ACLK_BUS_HZ / 2);
|
|
rk3128_bus_set_clk(priv, PCLK_CPU, ACLK_BUS_HZ / 2);
|
|
rk3128_peri_set_clk(priv, ACLK_PERI, ACLK_PERI_HZ);
|
|
rk3128_peri_set_clk(priv, HCLK_PERI, ACLK_PERI_HZ / 2);
|
|
rk3128_peri_set_clk(priv, PCLK_PERI, ACLK_PERI_HZ / 2);
|
|
|
|
rockchip_pll_set_rate(&rk3128_pll_clks[CPLL],
|
|
priv->cru, CPLL, CPLL_HZ);
|
|
}
|
|
|
|
static int rk3128_clk_probe(struct udevice *dev)
|
|
{
|
|
struct rk3128_clk_priv *priv = dev_get_priv(dev);
|
|
|
|
priv->sync_kernel = false;
|
|
if (!priv->armclk_enter_hz)
|
|
priv->armclk_enter_hz =
|
|
rockchip_pll_get_rate(&rk3128_pll_clks[APLL],
|
|
priv->cru, APLL);
|
|
rkclk_init(priv);
|
|
if (!priv->armclk_init_hz)
|
|
priv->armclk_init_hz =
|
|
rockchip_pll_get_rate(&rk3128_pll_clks[APLL],
|
|
priv->cru, APLL);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rk3128_clk_bind(struct udevice *dev)
|
|
{
|
|
int ret;
|
|
struct udevice *sys_child, *sf_child;
|
|
struct sysreset_reg *priv;
|
|
struct softreset_reg *sf_priv;
|
|
|
|
/* The reset driver does not have a device node, so bind it here */
|
|
ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
|
|
&sys_child);
|
|
if (ret) {
|
|
debug("Warning: No sysreset driver: ret=%d\n", ret);
|
|
} else {
|
|
priv = malloc(sizeof(struct sysreset_reg));
|
|
priv->glb_srst_fst_value = offsetof(struct rk3128_cru,
|
|
cru_glb_srst_fst_value);
|
|
priv->glb_srst_snd_value = offsetof(struct rk3128_cru,
|
|
cru_glb_srst_snd_value);
|
|
sys_child->priv = priv;
|
|
}
|
|
|
|
ret = device_bind_driver_to_node(dev, "rockchip_reset", "reset",
|
|
dev_ofnode(dev), &sf_child);
|
|
if (ret) {
|
|
debug("Warning: No rockchip reset driver: ret=%d\n", ret);
|
|
} else {
|
|
sf_priv = malloc(sizeof(struct softreset_reg));
|
|
sf_priv->sf_reset_offset = offsetof(struct rk3128_cru,
|
|
cru_softrst_con[0]);
|
|
sf_priv->sf_reset_num = 9;
|
|
sf_child->priv = sf_priv;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct udevice_id rk3128_clk_ids[] = {
|
|
{ .compatible = "rockchip,rk3128-cru" },
|
|
{ .compatible = "rockchip,rk3126-cru" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(rockchip_rk3128_cru) = {
|
|
.name = "clk_rk3128",
|
|
.id = UCLASS_CLK,
|
|
.of_match = rk3128_clk_ids,
|
|
.priv_auto_alloc_size = sizeof(struct rk3128_clk_priv),
|
|
.ofdata_to_platdata = rk3128_clk_ofdata_to_platdata,
|
|
.ops = &rk3128_clk_ops,
|
|
.bind = rk3128_clk_bind,
|
|
.probe = rk3128_clk_probe,
|
|
};
|
|
|
|
#ifndef CONFIG_SPL_BUILD
|
|
/**
|
|
* soc_clk_dump() - Print clock frequencies
|
|
* Returns zero on success
|
|
*
|
|
* Implementation for the clk dump command.
|
|
*/
|
|
int soc_clk_dump(void)
|
|
{
|
|
struct udevice *cru_dev;
|
|
struct rk3128_clk_priv *priv;
|
|
const struct rk3128_clk_info *clk_dump;
|
|
struct clk clk;
|
|
unsigned long clk_count = ARRAY_SIZE(clks_dump);
|
|
unsigned long rate;
|
|
int i, ret;
|
|
|
|
ret = uclass_get_device_by_driver(UCLASS_CLK,
|
|
DM_GET_DRIVER(rockchip_rk3128_cru),
|
|
&cru_dev);
|
|
if (ret) {
|
|
printf("%s failed to get cru device\n", __func__);
|
|
return ret;
|
|
}
|
|
|
|
priv = dev_get_priv(cru_dev);
|
|
printf("CLK: (%s. arm: enter %lu KHz, init %lu KHz, kernel %lu%s)\n",
|
|
priv->sync_kernel ? "sync kernel" : "uboot",
|
|
priv->armclk_enter_hz / 1000,
|
|
priv->armclk_init_hz / 1000,
|
|
priv->set_armclk_rate ? priv->armclk_hz / 1000 : 0,
|
|
priv->set_armclk_rate ? " KHz" : "N/A");
|
|
for (i = 0; i < clk_count; i++) {
|
|
clk_dump = &clks_dump[i];
|
|
if (clk_dump->name) {
|
|
clk.id = clk_dump->id;
|
|
if (clk_dump->is_cru)
|
|
ret = clk_request(cru_dev, &clk);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
rate = clk_get_rate(&clk);
|
|
clk_free(&clk);
|
|
if (i == 0) {
|
|
if (rate < 0)
|
|
printf(" %s %s\n", clk_dump->name,
|
|
"unknown");
|
|
else
|
|
printf(" %s %lu KHz\n", clk_dump->name,
|
|
rate / 1000);
|
|
} else {
|
|
if (rate < 0)
|
|
printf(" %s %s\n", clk_dump->name,
|
|
"unknown");
|
|
else
|
|
printf(" %s %lu KHz\n", clk_dump->name,
|
|
rate / 1000);
|
|
}
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|