78 lines
		
	
	
		
			3.9 KiB
		
	
	
	
		
			C++
		
	
	
	
			
		
		
	
	
			78 lines
		
	
	
		
			3.9 KiB
		
	
	
	
		
			C++
		
	
	
	
| /*
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|  * Copyright (c) 2019-2020 Arm Limited.
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|  *
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|  * SPDX-License-Identifier: MIT
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|  *
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|  * Permission is hereby granted, free of charge, to any person obtaining a copy
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|  * of this software and associated documentation files (the "Software"), to
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|  * deal in the Software without restriction, including without limitation the
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|  * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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|  * sell copies of the Software, and to permit persons to whom the Software is
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|  * furnished to do so, subject to the following conditions:
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|  *
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|  * The above copyright notice and this permission notice shall be included in all
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|  * copies or substantial portions of the Software.
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|  *
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|  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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|  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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|  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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|  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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|  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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|  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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|  * SOFTWARE.
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|  */
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| #ifndef ARM_COMPUTE_NEROIALIGNLAYER_H
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| #define ARM_COMPUTE_NEROIALIGNLAYER_H
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| 
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| #include "arm_compute/core/Types.h"
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| #include "arm_compute/runtime/NEON/INESimpleFunctionNoBorder.h"
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| 
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| namespace arm_compute
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| {
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| class ITensor;
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| class ITensorInfo;
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| 
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| /** Basic function to run @ref NEROIAlignLayerKernel.
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|  *
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|  * This function calls the following NEON kernels:
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|  * -# @ref NEROIAlignLayerKernel
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|  *
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|  */
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| class NEROIAlignLayer : public INESimpleFunctionNoBorder
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| {
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| public:
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|     /** Set the input and output tensors.
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|      *
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|      * @param[in]  input     Source tensor. Data types supported: QASYMM8/QASYMM8_SIGNED/F16/F32.
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|      * @param[in]  rois      ROIs tensor, it is a 2D tensor of size [5, N] (where N is the number of ROIs) containing top left and bottom right corner
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|      *                       as coordinate of an image and batch_id of ROI [ batch_id, x1, y1, x2, y2 ].
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|      *                       Data types supported: QASYMM16 with scale of 0.125 and 0 offset if @p input is QASYMM8, otherwise same as @p input
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|      * @param[out] output    Destination tensor. Data types supported: Same as @p input.
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|      * @param[in]  pool_info Contains pooling operation information described in @ref ROIPoolingLayerInfo.
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|      *
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|      * @note The x and y dimensions of @p output tensor must be the same as @p pool_info 's pooled
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|      * width and pooled height.
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|      * @note The z dimensions of @p output tensor and @p input tensor must be the same.
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|      * @note The fourth dimension of @p output tensor must be the same as the number of elements in @p rois array.
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|      */
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|     void configure(const ITensor *input, const ITensor *rois, ITensor *output, const ROIPoolingLayerInfo &pool_info);
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|     /** Static function to check if given info will lead to a valid configuration of @ref NEROIAlignLayerKernel
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|      *
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|      * @param[in] input     Source tensor info. Data types supported: QASYMM8/QASYMM8_SIGNED/F16/F32.
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|      * @param[in] rois      ROIs tensor info. Data types supported: QASYMM16 with scale of 0.125 and 0 offset if @p input is QASYMM8,
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|      *                      otherwise same as @p input
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|      * @param[in] output    Destination tensor info. Data types supported: Same as @p input.
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|      * @param[in] pool_info Contains pooling operation information described in @ref ROIPoolingLayerInfo.
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|      *
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|      * @note The x and y dimensions of @p output tensor must be the same as @p pool_info 's pooled
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|      * width and pooled height.
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|      * @note The z dimensions of @p output tensor and @p input tensor must be the same.
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|      * @note The fourth dimension of @p output tensor must be the same as the number of elements in @p rois array.
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|      *
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|      * @return a Status
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|      */
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|     static Status validate(const ITensorInfo *input, const ITensorInfo *rois, ITensorInfo *output, const ROIPoolingLayerInfo &pool_info);
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| };
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| } // namespace arm_compute
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| #endif /* ARM_COMPUTE_NEROIALIGNLAYER_H */
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