192 lines
5.9 KiB
C
192 lines
5.9 KiB
C
/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <arch.h>
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#include <plat/common/common_def.h>
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#include <board_def.h>
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/*******************************************************************************
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* Generic platform constants
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******************************************************************************/
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/* Size of cacheable stack */
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#if IMAGE_BL31
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#define PLATFORM_STACK_SIZE 0x800
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#else
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#define PLATFORM_STACK_SIZE 0x1000
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#endif
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#define PLATFORM_SYSTEM_COUNT 1
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#define PLATFORM_CORE_COUNT (K3_CLUSTER0_CORE_COUNT + \
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K3_CLUSTER1_CORE_COUNT + \
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K3_CLUSTER2_CORE_COUNT + \
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K3_CLUSTER3_CORE_COUNT)
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#define PLATFORM_CLUSTER_COUNT ((K3_CLUSTER0_CORE_COUNT != 0) + \
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(K3_CLUSTER1_CORE_COUNT != 0) + \
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(K3_CLUSTER2_CORE_COUNT != 0) + \
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(K3_CLUSTER3_CORE_COUNT != 0))
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#define PLAT_NUM_PWR_DOMAINS (PLATFORM_SYSTEM_COUNT + \
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PLATFORM_CLUSTER_COUNT + \
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PLATFORM_CORE_COUNT)
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#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
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/*******************************************************************************
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* Memory layout constants
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******************************************************************************/
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/*
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* ARM-TF lives in SRAM, partition it here
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*
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* BL3-1 specific defines.
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*
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* Put BL3-1 at the base of the Trusted SRAM.
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*/
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#define BL31_BASE SEC_SRAM_BASE
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#define BL31_SIZE SEC_SRAM_SIZE
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#define BL31_LIMIT (BL31_BASE + BL31_SIZE)
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/*
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* Defines the maximum number of translation tables that are allocated by the
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* translation table library code. To minimize the amount of runtime memory
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* used, choose the smallest value needed to map the required virtual addresses
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* for each BL stage.
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*/
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#if USE_COHERENT_MEM
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#define MAX_XLAT_TABLES 10
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#else
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#define MAX_XLAT_TABLES 9
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#endif
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/*
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* Defines the maximum number of regions that are allocated by the translation
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* table library code. A region consists of physical base address, virtual base
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* address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as
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* defined in the `mmap_region_t` structure. The platform defines the regions
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* that should be mapped. Then, the translation table library will create the
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* corresponding tables and descriptors at runtime. To minimize the amount of
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* runtime memory used, choose the smallest value needed to register the
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* required regions for each BL stage.
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*/
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#define MAX_MMAP_REGIONS 11
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/*
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* Defines the total size of the address space in bytes. For example, for a 32
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* bit address space, this value should be `(1ull << 32)`.
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*/
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32)
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/*
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* Some data must be aligned on the biggest cache line size in the platform.
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* This is known only to the platform as it might have a combination of
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* integrated and external caches.
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*/
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#define CACHE_WRITEBACK_SHIFT 6
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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/* Platform default console definitions */
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#ifndef K3_USART_BASE
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#define K3_USART_BASE (0x02800000 + 0x10000 * K3_USART)
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#endif
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/* USART has a default size for address space */
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#define K3_USART_SIZE 0x1000
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#ifndef K3_USART_CLK_SPEED
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#define K3_USART_CLK_SPEED 48000000
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#endif
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/* Crash console defaults */
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#define CRASH_CONSOLE_BASE K3_USART_BASE
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#define CRASH_CONSOLE_CLK K3_USART_CLK_SPEED
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#define CRASH_CONSOLE_BAUD_RATE K3_USART_BAUD
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/* Timer frequency */
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#ifndef SYS_COUNTER_FREQ_IN_TICKS
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#define SYS_COUNTER_FREQ_IN_TICKS 200000000
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#endif
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/* Interrupt numbers */
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#define ARM_IRQ_SEC_PHY_TIMER 29
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#define ARM_IRQ_SEC_SGI_0 8
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#define ARM_IRQ_SEC_SGI_1 9
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#define ARM_IRQ_SEC_SGI_2 10
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#define ARM_IRQ_SEC_SGI_3 11
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#define ARM_IRQ_SEC_SGI_4 12
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#define ARM_IRQ_SEC_SGI_5 13
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#define ARM_IRQ_SEC_SGI_6 14
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#define ARM_IRQ_SEC_SGI_7 15
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/*
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* Define properties of Group 1 Secure and Group 0 interrupts as per GICv3
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* terminology. On a GICv2 system or mode, the lists will be merged and treated
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* as Group 0 interrupts.
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*/
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#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
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INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE)
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#define PLAT_ARM_G0_IRQ_PROPS(grp) \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE)
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#define K3_GTC_BASE 0x00A90000
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/* We just need 20 byte offset, but simpler to just remap the 64K page in */
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#define K3_GTC_SIZE 0x10000
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#define K3_GTC_CNTCR_OFFSET 0x00
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#define K3_GTC_CNTCR_EN_MASK 0x01
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#define K3_GTC_CNTCR_HDBG_MASK 0x02
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#define K3_GTC_CNTFID0_OFFSET 0x20
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#define K3_GIC_BASE 0x01800000
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#define K3_GIC_SIZE 0x200000
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#if !K3_SEC_PROXY_LITE
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#define SEC_PROXY_DATA_BASE 0x32C00000
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#define SEC_PROXY_DATA_SIZE 0x80000
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#define SEC_PROXY_SCFG_BASE 0x32800000
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#define SEC_PROXY_SCFG_SIZE 0x80000
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#define SEC_PROXY_RT_BASE 0x32400000
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#define SEC_PROXY_RT_SIZE 0x80000
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#else
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#define SEC_PROXY_DATA_BASE 0x4D000000
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#define SEC_PROXY_DATA_SIZE 0x80000
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#define SEC_PROXY_SCFG_BASE 0x4A400000
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#define SEC_PROXY_SCFG_SIZE 0x80000
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#define SEC_PROXY_RT_BASE 0x4A600000
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#define SEC_PROXY_RT_SIZE 0x80000
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#endif /* K3_SEC_PROXY_LITE */
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#define SEC_PROXY_TIMEOUT_US 1000000
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#define SEC_PROXY_MAX_MESSAGE_SIZE 56
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#define TI_SCI_HOST_ID 10
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#define TI_SCI_MAX_MESSAGE_SIZE 52
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#endif /* PLATFORM_DEF_H */
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