475 lines
10 KiB
C
475 lines
10 KiB
C
/*
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* Copyright (C) 2016 Fuzhou Electronics Co.Ltd
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* Authors:
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* Yakir Yang <ykk@rock-chips.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#ifndef _RGA_REG_H_
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#define _RGA_REG_H_
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#define MODE_CTRL 0x0100
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#define SRC_INFO 0x0104
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#define SRC_Y_RGB_BASE_ADDR 0x0108
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#define SRC_CB_BASE_ADDR 0x010c
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#define SRC_CR_BASE_ADDR 0x0110
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#define SRC1_RGB_BASE_ADDR 0x0114
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#define SRC_VIR_INFO 0x0118
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#define SRC_ACT_INFO 0x011c
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#define SRC_X_FACTOR 0x0120
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#define SRC_Y_FACTOR 0x0124
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#define SRC_BG_COLOR 0x0128
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#define SRC_FG_COLOR 0x012c
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#define SRC_TR_COLOR0 0x0130
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#define SRC_TR_COLOR1 0x0134
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#define DST_INFO 0x0138
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#define DST_Y_RGB_BASE_ADDR 0x013c
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#define DST_CB_BASE_ADDR 0x0140
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#define DST_CR_BASE_ADDR 0x0144
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#define DST_VIR_INFO 0x0148
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#define DST_ACT_INFO 0x014c
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#define ALPHA_CTRL0 0x0150
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#define ALPHA_CTRL1 0x0154
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#define FADING_CTRL 0x0158
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#define PAT_CON 0x015c
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#define ROP_CON0 0x0160
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#define ROP_CON1 0x0164
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#define MASK_BASE 0x0168
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#define MMU_CTRL1 0x016c
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#define MMU_SRC_BASE 0x0170
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#define MMU_SRC1_BASE 0x0174
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#define MMU_DST_BASE 0x0178
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#define MMU_ELS_BASE 0x017c
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enum e_rga_render_mode {
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RGA_MODE_RENDER_BITBLT = 0,
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RGA_MODE_RENDER_COLOR_PALETTE = 1,
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RGA_MODE_RENDER_RECTANGLE_FILL = 2,
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RGA_MODE_RENDER_UPDATE_PALETTE_LUT_RAM = 3,
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};
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enum e_rga_bitblt_mode {
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RGA_MODE_BITBLT_MODE_SRC_TO_DST = 0,
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RGA_MODE_BITBLT_MODE_SRC_SRC1_TO_DST = 1,
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};
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enum e_rga_cf_rop4_pat {
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RGA_MODE_CF_ROP4_SOLID = 0,
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RGA_MODE_CF_ROP4_PATTERN = 1,
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};
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enum e_rga_src_color_format {
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RGA_SRC_COLOR_FMT_ABGR8888 = 0,
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RGA_SRC_COLOR_FMT_XBGR8888 = 1,
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RGA_SRC_COLOR_FMT_RGB888 = 2,
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RGA_SRC_COLOR_FMT_RGB565 = 4,
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RGA_SRC_COLOR_FMT_ARGB1555 = 5,
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RGA_SRC_COLOR_FMT_ARGB4444 = 6,
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RGA_SRC_COLOR_FMT_YUV422SP = 8,
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RGA_SRC_COLOR_FMT_YUV422P = 9,
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RGA_SRC_COLOR_FMT_YUV420SP = 10,
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RGA_SRC_COLOR_FMT_YUV420P = 11,
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/* SRC_COLOR Palette */
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RGA_SRC_COLOR_FMT_CP_1BPP = 12,
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RGA_SRC_COLOR_FMT_CP_2BPP = 13,
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RGA_SRC_COLOR_FMT_CP_4BPP = 14,
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RGA_SRC_COLOR_FMT_CP_8BPP = 15,
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RGA_SRC_COLOR_FMT_MASK = 15,
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};
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enum e_rga_src_color_swap {
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RGA_SRC_COLOR_RB_SWAP = 1,
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RGA_SRC_COLOR_ALPHA_SWAP = 2,
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RGA_SRC_COLOR_UV_SWAP = 4,
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};
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enum e_rga_src_csc_mode {
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RGA_SRC_CSC_MODE_BT601_R0 = 0,
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RGA_SRC_CSC_MODE_BT601_R1 = 1,
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RGA_SRC_CSC_MODE_BT709_R0 = 2,
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RGA_SRC_CSC_MODE_BT709_R1 = 3,
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/*
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RGA_SRC_CSC_MODE_BYPASS = 0,
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RGA_SRC_CSC_MODE_BT601_R0 = 1,
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RGA_SRC_CSC_MODE_BT601_R1 = 2,
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RGA_SRC_CSC_MODE_BT709_R0 = 3,
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*/
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};
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enum e_rga_src_rot_mode {
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RGA_SRC_ROT_MODE_0_DEGREE = 0,
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RGA_SRC_ROT_MODE_90_DEGREE = 1,
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RGA_SRC_ROT_MODE_180_DEGREE = 2,
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RGA_SRC_ROT_MODE_270_DEGREE = 3,
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};
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enum e_rga_src_mirr_mode {
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RGA_SRC_MIRR_MODE_NO = 0,
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RGA_SRC_MIRR_MODE_X = 1,
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RGA_SRC_MIRR_MODE_Y = 2,
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RGA_SRC_MIRR_MODE_X_Y = 3,
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};
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enum e_rga_src_hscl_mode {
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RGA_SRC_HSCL_MODE_NO = 0,
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RGA_SRC_HSCL_MODE_DOWN = 1,
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RGA_SRC_HSCL_MODE_UP = 2,
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};
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enum e_rga_src_vscl_mode {
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RGA_SRC_VSCL_MODE_NO = 0,
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RGA_SRC_VSCL_MODE_DOWN = 1,
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RGA_SRC_VSCL_MODE_UP = 2,
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};
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enum e_rga_src_trans_enable {
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RGA_SRC_TRANS_ENABLE_R = 1,
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RGA_SRC_TRANS_ENABLE_G = 2,
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RGA_SRC_TRANS_ENABLE_B = 4,
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RGA_SRC_TRANS_ENABLE_A = 8,
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};
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enum e_rga_src_bic_coe_select {
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RGA_SRC_BIC_COE_SELEC_CATROM = 0,
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RGA_SRC_BIC_COE_SELEC_MITCHELL = 1,
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RGA_SRC_BIC_COE_SELEC_HERMITE = 2,
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RGA_SRC_BIC_COE_SELEC_BSPLINE = 3,
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};
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enum e_rga_src_yuv_ten_enable {
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RGA_SRC_YUV_TEN_DISABLE = 0,
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RGA_SRC_YUV_TEN_ENABLE = 1,
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};
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enum e_rga_src_yuv_ten_round_enable {
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RGA_SRC_YUV_TEN_ROUND_DISABLE = 0,
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RGA_SRC_YUV_TEN_ROUND_ENABLE = 1,
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};
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enum e_rga_dst_color_format {
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RGA_DST_COLOR_FMT_ABGR888 = 0,
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RGA_DST_COLOR_FMT_XBGR888 = 1,
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RGA_DST_COLOR_FMT_RGB888 = 2,
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RGA_DST_COLOR_FMT_RGB565 = 4,
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RGA_DST_COLOR_FMT_ARGB1555 = 5,
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RGA_DST_COLOR_FMT_ARGB4444 = 6,
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RGA_DST_COLOR_FMT_YUV422SP = 8,
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RGA_DST_COLOR_FMT_YUV422P = 9,
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RGA_DST_COLOR_FMT_YUV420SP = 10,
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RGA_DST_COLOR_FMT_YUV420P = 11,
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RGA_DST_COLOR_FMT_MASK = 11,
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};
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enum e_rga_dst_color_swap {
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RGA_DST_COLOR_RB_SWAP = 1,
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RGA_DST_COLOR_ALPHA_SWAP = 2,
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RGA_DST_COLOR_UV_SWAP = 4,
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};
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enum e_rga_src1_color_format {
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RGA_SRC1_COLOR_FMT_ABGR888 = 0,
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RGA_SRC1_COLOR_FMT_XBGR888 = 1,
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RGA_SRC1_COLOR_FMT_RGB888 = 2,
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RGA_SRC1_COLOR_FMT_RGB565 = 4,
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RGA_SRC1_COLOR_FMT_ARGB1555 = 5,
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RGA_SRC1_COLOR_FMT_ARGB4444 = 6,
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RGA_SRC1_COLOR_FMT_MASK = 6,
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};
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enum e_rga_src1_color_swap {
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RGA_SRC1_COLOR_RB_SWAP = 1,
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RGA_SRC1_COLOR_ALPHA_SWAP = 2,
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};
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enum e_rga_dst_dither_down_mode {
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RGA_DST_DITHER_MODE_888_TO_666 = 0,
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RGA_DST_DITHER_MODE_888_TO_565 = 1,
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RGA_DST_DITHER_MODE_888_TO_555 = 2,
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RGA_DST_DITHER_MODE_888_TO_444 = 3,
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};
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enum e_rga_dst_csc_mode {
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RGA_DST_CSC_MODE_BYPASS = 0,
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RGA_DST_CSC_MODE_BT601_R0 = 1,
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RGA_DST_CSC_MODE_BT601_R1 = 2,
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RGA_DST_CSC_MODE_BT709_R0 = 3,
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};
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enum e_rga_alpha_rop_mode {
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RGA_ALPHA_ROP_MODE_2 = 0,
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RGA_ALPHA_ROP_MODE_3 = 1,
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RGA_ALPHA_ROP_MODE_4 = 2,
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};
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enum e_rga_alpha_rop_select {
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RGA_ALPHA_SELECT_ALPHA = 0,
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RGA_ALPHA_SELECT_ROP = 1,
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};
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union rga_mode_ctrl {
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unsigned int val;
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struct {
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/* [0:2] */
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enum e_rga_render_mode render:3;
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/* [3:6] */
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enum e_rga_bitblt_mode bitblt:1;
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enum e_rga_cf_rop4_pat cf_rop4_pat:1;
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unsigned int alpha_zero_key:1;
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unsigned int gradient_sat:1;
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/* [7:31] */
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unsigned int reserved:25;
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} data;
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};
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union rga_src_info {
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unsigned int val;
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struct {
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/* [0:3] */
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enum e_rga_src_color_format format:4;
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/* [4:7] */
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enum e_rga_src_color_swap swap:3;
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unsigned int cp_endian:1;
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/* [8:17] */
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enum e_rga_src_csc_mode csc_mode:2;
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enum e_rga_src_rot_mode rot_mode:2;
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enum e_rga_src_mirr_mode mir_mode:2;
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enum e_rga_src_hscl_mode hscl_mode:2;
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enum e_rga_src_vscl_mode vscl_mode:2;
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/* [18:22] */
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unsigned int trans_mode:1;
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enum e_rga_src_trans_enable trans_enable:4;
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/* [23:25] */
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unsigned int dither_up_en:1;
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enum e_rga_src_bic_coe_select bic_coe_sel:2;
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/* [26] */
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unsigned int reserved:1;
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/* [27:28] */
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enum e_rga_src_yuv_ten_enable yuv_ten_en:1;
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enum e_rga_src_yuv_ten_round_enable yuv_ten_round_en:1;
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/* [29:31]*/
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unsigned int reserved1:3;
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} data;
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};
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union rga_src_vir_info {
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unsigned int val;
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struct {
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/* [0:15] */
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unsigned int vir_width:15;
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unsigned int reserved:1;
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/* [16:25] */
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unsigned int vir_stride:10;
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/* [26:31] */
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unsigned int reserved1:6;
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} data;
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};
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union rga_src_act_info {
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unsigned int val;
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struct {
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/* [0:15] */
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unsigned int act_width:13;
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unsigned int reserved:3;
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/* [16:31] */
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unsigned int act_height:13;
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unsigned int reserved1:3;
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} data;
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};
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union rga_src_x_factor {
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unsigned int val;
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struct {
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/* [0:15] */
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unsigned int down_scale_factor:16;
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/* [16:31] */
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unsigned int up_scale_factor:16;
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} data;
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};
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union rga_src_y_factor {
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unsigned int val;
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struct {
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/* [0:15] */
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unsigned int down_scale_factor:16;
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/* [16:31] */
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unsigned int up_scale_factor:16;
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} data;
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};
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/* Alpha / Red / Green / Blue */
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union rga_src_cp_gr_color {
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unsigned int val;
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struct {
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/* [0:15] */
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unsigned int gradient_x:16;
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/* [16:31] */
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unsigned int gradient_y:16;
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} data;
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};
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union rga_src_transparency_color0 {
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unsigned int val;
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struct {
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/* [0:7] */
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unsigned int trans_rmin:8;
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/* [8:15] */
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unsigned int trans_gmin:8;
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/* [16:23] */
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unsigned int trans_bmin:8;
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/* [24:31] */
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unsigned int trans_amin:8;
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} data;
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};
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union rga_src_transparency_color1 {
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unsigned int val;
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struct {
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/* [0:7] */
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unsigned int trans_rmax:8;
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/* [8:15] */
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unsigned int trans_gmax:8;
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/* [16:23] */
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unsigned int trans_bmax:8;
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/* [24:31] */
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unsigned int trans_amax:8;
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} data;
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};
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union rga_dst_info {
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unsigned int val;
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struct {
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/* [0:3] */
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enum e_rga_dst_color_format format:4;
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/* [4:6] */
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enum e_rga_dst_color_swap swap:3;
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/* [7:9] */
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enum e_rga_src1_color_format src1_format:3;
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/* [10:11] */
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enum e_rga_src1_color_swap src1_swap:2;
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/* [12:15] */
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unsigned int dither_up_en:1;
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unsigned int dither_down_en:1;
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enum e_rga_dst_dither_down_mode dither_down_mode:2;
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/* [16:18] */
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enum e_rga_dst_csc_mode csc_mode:2;
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unsigned int csc_clip:1;
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/* [19:31] */
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unsigned int reserved:13;
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} data;
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};
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union rga_dst_vir_info {
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unsigned int val;
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struct {
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/* [0:15] */
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unsigned int vir_stride:15;
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unsigned int reserved:1;
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/* [16:31] */
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unsigned int src1_vir_stride:15;
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unsigned int reserved1:1;
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} data;
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};
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union rga_dst_act_info {
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unsigned int val;
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struct {
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/* [0:15] */
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unsigned int act_width:12;
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unsigned int reserved:4;
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/* [16:31] */
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unsigned int act_height:12;
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unsigned int reserved1:4;
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} data;
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};
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union rga_alpha_ctrl0 {
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unsigned int val;
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struct {
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/* [0:3] */
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unsigned int rop_en:1;
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enum e_rga_alpha_rop_select rop_select:1;
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enum e_rga_alpha_rop_mode rop_mode:2;
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/* [4:11] */
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unsigned int src_fading_val:8;
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/* [12:20] */
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unsigned int dst_fading_val:8;
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unsigned int mask_endian:1;
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/* [21:31] */
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unsigned int reserved:11;
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} data;
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};
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union rga_alpha_ctrl1 {
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unsigned int val;
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struct {
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/* [0:1] */
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unsigned int dst_color_m0:1;
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unsigned int src_color_m0:1;
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/* [2:7] */
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unsigned int dst_factor_m0:3;
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unsigned int src_factor_m0:3;
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/* [8:9] */
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unsigned int dst_alpha_cal_m0:1;
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unsigned int src_alpha_cal_m0:1;
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/* [10:13] */
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unsigned int dst_blend_m0:2;
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unsigned int src_blend_m0:2;
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/* [14:15] */
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unsigned int dst_alpha_m0:1;
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unsigned int src_alpha_m0:1;
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/* [16:21] */
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unsigned int dst_factor_m1:3;
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unsigned int src_factor_m1:3;
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/* [22:23] */
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unsigned int dst_alpha_cal_m1:1;
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unsigned int src_alpha_cal_m1:1;
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/* [24:27] */
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unsigned int dst_blend_m1:2;
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unsigned int src_blend_m1:2;
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/* [28:29] */
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unsigned int dst_alpha_m1:1;
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unsigned int src_alpha_m1:1;
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/* [30:31] */
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unsigned int reserved:2;
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} data;
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};
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union rga_fading_ctrl {
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unsigned int val;
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struct {
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/* [0:7] */
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unsigned int fading_offset_r:8;
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/* [8:15] */
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unsigned int fading_offset_g:8;
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/* [16:23] */
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unsigned int fading_offset_b:8;
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/* [24:31] */
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unsigned int fading_en:1;
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unsigned int reserved:7;
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} data;
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};
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union rga_pat_con {
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unsigned int val;
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struct {
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/* [0:7] */
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unsigned int width:8;
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/* [8:15] */
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unsigned int height:8;
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/* [16:23] */
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unsigned int offset_x:8;
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/* [24:31] */
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unsigned int offset_y:8;
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} data;
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};
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#endif
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