463 lines
10 KiB
C++
463 lines
10 KiB
C++
//=====-- AMDGPUSubtarget.h - Define Subtarget for AMDGPU ------*- C++ -*-====//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//==-----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief AMDGPU specific subclass of TargetSubtarget.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H
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#define LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H
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#include "AMDGPU.h"
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#include "R600InstrInfo.h"
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#include "R600ISelLowering.h"
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#include "R600FrameLowering.h"
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#include "SIInstrInfo.h"
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#include "SIISelLowering.h"
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#include "SIFrameLowering.h"
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#include "Utils/AMDGPUBaseInfo.h"
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#include "llvm/CodeGen/GlobalISel/GISelAccessor.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#define GET_SUBTARGETINFO_HEADER
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#include "AMDGPUGenSubtargetInfo.inc"
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namespace llvm {
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class SIMachineFunctionInfo;
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class StringRef;
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class AMDGPUSubtarget : public AMDGPUGenSubtargetInfo {
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public:
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enum Generation {
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R600 = 0,
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R700,
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EVERGREEN,
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NORTHERN_ISLANDS,
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SOUTHERN_ISLANDS,
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SEA_ISLANDS,
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VOLCANIC_ISLANDS,
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};
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enum {
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ISAVersion0_0_0,
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ISAVersion7_0_0,
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ISAVersion7_0_1,
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ISAVersion8_0_0,
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ISAVersion8_0_1,
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ISAVersion8_0_3
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};
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protected:
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// Basic subtarget description.
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Triple TargetTriple;
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Generation Gen;
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unsigned IsaVersion;
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unsigned WavefrontSize;
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int LocalMemorySize;
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int LDSBankCount;
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unsigned MaxPrivateElementSize;
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// Possibly statically set by tablegen, but may want to be overridden.
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bool FastFMAF32;
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bool HalfRate64Ops;
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// Dynamially set bits that enable features.
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bool FP32Denormals;
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bool FP64Denormals;
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bool FPExceptions;
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bool FlatForGlobal;
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bool UnalignedBufferAccess;
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bool EnableXNACK;
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bool DebuggerInsertNops;
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bool DebuggerReserveRegs;
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bool DebuggerEmitPrologue;
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// Used as options.
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bool EnableVGPRSpilling;
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bool EnablePromoteAlloca;
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bool EnableLoadStoreOpt;
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bool EnableUnsafeDSOffsetFolding;
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bool EnableSIScheduler;
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bool DumpCode;
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// Subtarget statically properties set by tablegen
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bool FP64;
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bool IsGCN;
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bool GCN1Encoding;
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bool GCN3Encoding;
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bool CIInsts;
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bool SGPRInitBug;
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bool HasSMemRealTime;
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bool Has16BitInsts;
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bool FlatAddressSpace;
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bool R600ALUInst;
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bool CaymanISA;
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bool CFALUBug;
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bool HasVertexCache;
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short TexVTXClauseSize;
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// Dummy feature to use for assembler in tablegen.
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bool FeatureDisable;
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InstrItineraryData InstrItins;
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public:
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AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
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const TargetMachine &TM);
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virtual ~AMDGPUSubtarget();
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AMDGPUSubtarget &initializeSubtargetDependencies(const Triple &TT,
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StringRef GPU, StringRef FS);
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const AMDGPUInstrInfo *getInstrInfo() const override;
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const AMDGPUFrameLowering *getFrameLowering() const override;
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const AMDGPUTargetLowering *getTargetLowering() const override;
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const AMDGPURegisterInfo *getRegisterInfo() const override;
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const InstrItineraryData *getInstrItineraryData() const override {
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return &InstrItins;
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}
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void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
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bool isAmdHsaOS() const {
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return TargetTriple.getOS() == Triple::AMDHSA;
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}
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Generation getGeneration() const {
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return Gen;
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}
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unsigned getWavefrontSize() const {
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return WavefrontSize;
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}
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int getLocalMemorySize() const {
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return LocalMemorySize;
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}
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int getLDSBankCount() const {
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return LDSBankCount;
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}
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unsigned getMaxPrivateElementSize() const {
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return MaxPrivateElementSize;
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}
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bool hasHWFP64() const {
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return FP64;
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}
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bool hasFastFMAF32() const {
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return FastFMAF32;
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}
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bool hasHalfRate64Ops() const {
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return HalfRate64Ops;
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}
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bool hasAddr64() const {
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return (getGeneration() < VOLCANIC_ISLANDS);
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}
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bool hasBFE() const {
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return (getGeneration() >= EVERGREEN);
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}
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bool hasBFI() const {
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return (getGeneration() >= EVERGREEN);
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}
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bool hasBFM() const {
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return hasBFE();
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}
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bool hasBCNT(unsigned Size) const {
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if (Size == 32)
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return (getGeneration() >= EVERGREEN);
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if (Size == 64)
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return (getGeneration() >= SOUTHERN_ISLANDS);
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return false;
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}
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bool hasMulU24() const {
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return (getGeneration() >= EVERGREEN);
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}
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bool hasMulI24() const {
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return (getGeneration() >= SOUTHERN_ISLANDS ||
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hasCaymanISA());
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}
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bool hasFFBL() const {
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return (getGeneration() >= EVERGREEN);
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}
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bool hasFFBH() const {
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return (getGeneration() >= EVERGREEN);
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}
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bool hasCARRY() const {
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return (getGeneration() >= EVERGREEN);
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}
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bool hasBORROW() const {
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return (getGeneration() >= EVERGREEN);
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}
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bool hasCaymanISA() const {
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return CaymanISA;
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}
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bool isPromoteAllocaEnabled() const {
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return EnablePromoteAlloca;
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}
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bool unsafeDSOffsetFoldingEnabled() const {
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return EnableUnsafeDSOffsetFolding;
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}
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bool dumpCode() const {
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return DumpCode;
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}
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/// Return the amount of LDS that can be used that will not restrict the
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/// occupancy lower than WaveCount.
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unsigned getMaxLocalMemSizeWithWaveCount(unsigned WaveCount) const;
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/// Inverse of getMaxLocalMemWithWaveCount. Return the maximum wavecount if
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/// the given LDS memory size is the only constraint.
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unsigned getOccupancyWithLocalMemSize(uint32_t Bytes) const;
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bool hasFP32Denormals() const {
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return FP32Denormals;
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}
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bool hasFP64Denormals() const {
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return FP64Denormals;
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}
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bool hasFPExceptions() const {
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return FPExceptions;
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}
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bool useFlatForGlobal() const {
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return FlatForGlobal;
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}
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bool hasUnalignedBufferAccess() const {
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return UnalignedBufferAccess;
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}
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bool isXNACKEnabled() const {
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return EnableXNACK;
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}
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unsigned getMaxWavesPerCU() const {
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if (getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
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return 10;
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// FIXME: Not sure what this is for other subtagets.
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return 8;
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}
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/// \brief Returns the offset in bytes from the start of the input buffer
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/// of the first explicit kernel argument.
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unsigned getExplicitKernelArgOffset() const {
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return isAmdHsaOS() ? 0 : 36;
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}
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unsigned getStackAlignment() const {
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// Scratch is allocated in 256 dword per wave blocks.
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return 4 * 256 / getWavefrontSize();
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}
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bool enableMachineScheduler() const override {
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return true;
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}
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bool enableSubRegLiveness() const override {
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return true;
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}
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};
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class R600Subtarget final : public AMDGPUSubtarget {
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private:
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R600InstrInfo InstrInfo;
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R600FrameLowering FrameLowering;
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R600TargetLowering TLInfo;
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public:
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R600Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
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const TargetMachine &TM);
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const R600InstrInfo *getInstrInfo() const override {
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return &InstrInfo;
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}
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const R600FrameLowering *getFrameLowering() const override {
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return &FrameLowering;
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}
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const R600TargetLowering *getTargetLowering() const override {
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return &TLInfo;
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}
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const R600RegisterInfo *getRegisterInfo() const override {
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return &InstrInfo.getRegisterInfo();
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}
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bool hasCFAluBug() const {
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return CFALUBug;
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}
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bool hasVertexCache() const {
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return HasVertexCache;
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}
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short getTexVTXClauseSize() const {
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return TexVTXClauseSize;
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}
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unsigned getStackEntrySize() const;
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};
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class SISubtarget final : public AMDGPUSubtarget {
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public:
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enum {
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FIXED_SGPR_COUNT_FOR_INIT_BUG = 80
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};
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private:
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SIInstrInfo InstrInfo;
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SIFrameLowering FrameLowering;
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SITargetLowering TLInfo;
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std::unique_ptr<GISelAccessor> GISel;
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public:
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SISubtarget(const Triple &TT, StringRef CPU, StringRef FS,
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const TargetMachine &TM);
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const SIInstrInfo *getInstrInfo() const override {
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return &InstrInfo;
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}
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const SIFrameLowering *getFrameLowering() const override {
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return &FrameLowering;
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}
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const SITargetLowering *getTargetLowering() const override {
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return &TLInfo;
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}
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const CallLowering *getCallLowering() const override {
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assert(GISel && "Access to GlobalISel APIs not set");
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return GISel->getCallLowering();
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}
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const SIRegisterInfo *getRegisterInfo() const override {
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return &InstrInfo.getRegisterInfo();
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}
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void setGISelAccessor(GISelAccessor &GISel) {
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this->GISel.reset(&GISel);
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}
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void overrideSchedPolicy(MachineSchedPolicy &Policy,
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unsigned NumRegionInstrs) const override;
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bool isVGPRSpillingEnabled(const Function& F) const;
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unsigned getAmdKernelCodeChipID() const;
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AMDGPU::IsaVersion getIsaVersion() const;
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unsigned getMaxNumUserSGPRs() const {
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return 16;
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}
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bool hasFlatAddressSpace() const {
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return FlatAddressSpace;
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}
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bool hasSMemRealTime() const {
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return HasSMemRealTime;
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}
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bool has16BitInsts() const {
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return Has16BitInsts;
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}
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bool enableSIScheduler() const {
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return EnableSIScheduler;
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}
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bool debuggerSupported() const {
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return debuggerInsertNops() && debuggerReserveRegs() &&
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debuggerEmitPrologue();
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}
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bool debuggerInsertNops() const {
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return DebuggerInsertNops;
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}
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bool debuggerReserveRegs() const {
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return DebuggerReserveRegs;
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}
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bool debuggerEmitPrologue() const {
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return DebuggerEmitPrologue;
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}
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bool loadStoreOptEnabled() const {
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return EnableLoadStoreOpt;
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}
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bool hasSGPRInitBug() const {
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return SGPRInitBug;
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}
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};
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inline const AMDGPUInstrInfo *AMDGPUSubtarget::getInstrInfo() const {
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if (getGeneration() >= SOUTHERN_ISLANDS)
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return static_cast<const SISubtarget *>(this)->getInstrInfo();
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return static_cast<const R600Subtarget *>(this)->getInstrInfo();
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}
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inline const AMDGPUFrameLowering *AMDGPUSubtarget::getFrameLowering() const {
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if (getGeneration() >= SOUTHERN_ISLANDS)
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return static_cast<const SISubtarget *>(this)->getFrameLowering();
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return static_cast<const R600Subtarget *>(this)->getFrameLowering();
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}
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inline const AMDGPUTargetLowering *AMDGPUSubtarget::getTargetLowering() const {
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if (getGeneration() >= SOUTHERN_ISLANDS)
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return static_cast<const SISubtarget *>(this)->getTargetLowering();
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return static_cast<const R600Subtarget *>(this)->getTargetLowering();
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}
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inline const AMDGPURegisterInfo *AMDGPUSubtarget::getRegisterInfo() const {
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if (getGeneration() >= SOUTHERN_ISLANDS)
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return static_cast<const SISubtarget *>(this)->getRegisterInfo();
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return static_cast<const R600Subtarget *>(this)->getRegisterInfo();
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}
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} // End namespace llvm
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#endif
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