600 lines
19 KiB
C++
600 lines
19 KiB
C++
//===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the X86 specific subclass of TargetSubtargetInfo.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_X86_X86SUBTARGET_H
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#define LLVM_LIB_TARGET_X86_X86SUBTARGET_H
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#include "X86FrameLowering.h"
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#include "X86ISelLowering.h"
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#include "X86InstrInfo.h"
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#include "X86SelectionDAGInfo.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#include <string>
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#define GET_SUBTARGETINFO_HEADER
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#include "X86GenSubtargetInfo.inc"
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namespace llvm {
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class GlobalValue;
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class StringRef;
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class TargetMachine;
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/// The X86 backend supports a number of different styles of PIC.
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///
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namespace PICStyles {
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enum Style {
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StubPIC, // Used on i386-darwin in pic mode.
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GOT, // Used on 32 bit elf on when in pic mode.
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RIPRel, // Used on X86-64 when in pic mode.
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None // Set when not in pic mode.
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};
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}
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class X86Subtarget final : public X86GenSubtargetInfo {
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protected:
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enum X86SSEEnum {
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NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
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};
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enum X863DNowEnum {
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NoThreeDNow, MMX, ThreeDNow, ThreeDNowA
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};
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enum X86ProcFamilyEnum {
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Others, IntelAtom, IntelSLM
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};
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/// X86 processor family: Intel Atom, and others
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X86ProcFamilyEnum X86ProcFamily;
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/// Which PIC style to use
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PICStyles::Style PICStyle;
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const TargetMachine &TM;
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/// SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
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X86SSEEnum X86SSELevel;
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/// MMX, 3DNow, 3DNow Athlon, or none supported.
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X863DNowEnum X863DNowLevel;
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/// True if the processor supports X87 instructions.
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bool HasX87;
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/// True if this processor has conditional move instructions
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/// (generally pentium pro+).
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bool HasCMov;
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/// True if the processor supports X86-64 instructions.
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bool HasX86_64;
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/// True if the processor supports POPCNT.
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bool HasPOPCNT;
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/// True if the processor supports SSE4A instructions.
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bool HasSSE4A;
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/// Target has AES instructions
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bool HasAES;
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/// Target has FXSAVE/FXRESTOR instructions
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bool HasFXSR;
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/// Target has XSAVE instructions
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bool HasXSAVE;
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/// Target has XSAVEOPT instructions
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bool HasXSAVEOPT;
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/// Target has XSAVEC instructions
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bool HasXSAVEC;
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/// Target has XSAVES instructions
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bool HasXSAVES;
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/// Target has carry-less multiplication
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bool HasPCLMUL;
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/// Target has 3-operand fused multiply-add
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bool HasFMA;
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/// Target has 4-operand fused multiply-add
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bool HasFMA4;
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/// Target has XOP instructions
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bool HasXOP;
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/// Target has TBM instructions.
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bool HasTBM;
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/// True if the processor has the MOVBE instruction.
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bool HasMOVBE;
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/// True if the processor has the RDRAND instruction.
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bool HasRDRAND;
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/// Processor has 16-bit floating point conversion instructions.
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bool HasF16C;
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/// Processor has FS/GS base insturctions.
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bool HasFSGSBase;
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/// Processor has LZCNT instruction.
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bool HasLZCNT;
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/// Processor has BMI1 instructions.
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bool HasBMI;
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/// Processor has BMI2 instructions.
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bool HasBMI2;
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/// Processor has VBMI instructions.
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bool HasVBMI;
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/// Processor has Integer Fused Multiply Add
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bool HasIFMA;
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/// Processor has RTM instructions.
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bool HasRTM;
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/// Processor has HLE.
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bool HasHLE;
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/// Processor has ADX instructions.
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bool HasADX;
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/// Processor has SHA instructions.
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bool HasSHA;
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/// Processor has PRFCHW instructions.
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bool HasPRFCHW;
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/// Processor has RDSEED instructions.
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bool HasRDSEED;
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/// Processor has LAHF/SAHF instructions.
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bool HasLAHFSAHF;
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/// Processor has MONITORX/MWAITX instructions.
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bool HasMWAITX;
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/// Processor has Prefetch with intent to Write instruction
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bool HasPFPREFETCHWT1;
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/// True if BT (bit test) of memory instructions are slow.
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bool IsBTMemSlow;
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/// True if SHLD instructions are slow.
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bool IsSHLDSlow;
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/// True if unaligned memory accesses of 16-bytes are slow.
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bool IsUAMem16Slow;
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/// True if unaligned memory accesses of 32-bytes are slow.
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bool IsUAMem32Slow;
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/// True if SSE operations can have unaligned memory operands.
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/// This may require setting a configuration bit in the processor.
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bool HasSSEUnalignedMem;
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/// True if this processor has the CMPXCHG16B instruction;
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/// this is true for most x86-64 chips, but not the first AMD chips.
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bool HasCmpxchg16b;
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/// True if the LEA instruction should be used for adjusting
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/// the stack pointer. This is an optimization for Intel Atom processors.
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bool UseLeaForSP;
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/// True if there is no performance penalty to writing only the lower parts
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/// of a YMM register without clearing the upper part.
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bool HasFastPartialYMMWrite;
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/// True if 8-bit divisions are significantly faster than
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/// 32-bit divisions and should be used when possible.
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bool HasSlowDivide32;
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/// True if 16-bit divides are significantly faster than
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/// 64-bit divisions and should be used when possible.
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bool HasSlowDivide64;
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/// True if the short functions should be padded to prevent
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/// a stall when returning too early.
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bool PadShortFunctions;
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/// True if the Calls with memory reference should be converted
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/// to a register-based indirect call.
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bool CallRegIndirect;
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/// True if the LEA instruction inputs have to be ready at address generation
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/// (AG) time.
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bool LEAUsesAG;
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/// True if the LEA instruction with certain arguments is slow
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bool SlowLEA;
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/// True if INC and DEC instructions are slow when writing to flags
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bool SlowIncDec;
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/// Processor has AVX-512 PreFetch Instructions
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bool HasPFI;
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/// Processor has AVX-512 Exponential and Reciprocal Instructions
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bool HasERI;
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/// Processor has AVX-512 Conflict Detection Instructions
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bool HasCDI;
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/// Processor has AVX-512 Doubleword and Quadword instructions
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bool HasDQI;
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/// Processor has AVX-512 Byte and Word instructions
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bool HasBWI;
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/// Processor has AVX-512 Vector Length eXtenstions
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bool HasVLX;
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/// Processor has PKU extenstions
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bool HasPKU;
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/// Processor supports MPX - Memory Protection Extensions
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bool HasMPX;
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/// Processor supports Invalidate Process-Context Identifier
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bool HasInvPCId;
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/// Processor has VM Functions
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bool HasVMFUNC;
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/// Processor has Supervisor Mode Access Protection
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bool HasSMAP;
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/// Processor has Software Guard Extensions
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bool HasSGX;
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/// Processor supports Flush Cache Line instruction
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bool HasCLFLUSHOPT;
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/// Processor has Persistent Commit feature
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bool HasPCOMMIT;
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/// Processor supports Cache Line Write Back instruction
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bool HasCLWB;
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/// Use software floating point for code generation.
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bool UseSoftFloat;
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/// The minimum alignment known to hold of the stack frame on
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/// entry to the function and which must be maintained by every function.
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unsigned stackAlignment;
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/// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
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///
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unsigned MaxInlineSizeThreshold;
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/// What processor and OS we're targeting.
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Triple TargetTriple;
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/// Instruction itineraries for scheduling
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InstrItineraryData InstrItins;
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private:
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/// Override the stack alignment.
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unsigned StackAlignOverride;
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/// True if compiling for 64-bit, false for 16-bit or 32-bit.
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bool In64BitMode;
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/// True if compiling for 32-bit, false for 16-bit or 64-bit.
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bool In32BitMode;
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/// True if compiling for 16-bit, false for 32-bit or 64-bit.
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bool In16BitMode;
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X86SelectionDAGInfo TSInfo;
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// Ordering here is important. X86InstrInfo initializes X86RegisterInfo which
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// X86TargetLowering needs.
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X86InstrInfo InstrInfo;
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X86TargetLowering TLInfo;
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X86FrameLowering FrameLowering;
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public:
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/// This constructor initializes the data members to match that
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/// of the specified triple.
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///
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X86Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
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const X86TargetMachine &TM, unsigned StackAlignOverride);
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const X86TargetLowering *getTargetLowering() const override {
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return &TLInfo;
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}
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const X86InstrInfo *getInstrInfo() const override { return &InstrInfo; }
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const X86FrameLowering *getFrameLowering() const override {
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return &FrameLowering;
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}
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const X86SelectionDAGInfo *getSelectionDAGInfo() const override {
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return &TSInfo;
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}
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const X86RegisterInfo *getRegisterInfo() const override {
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return &getInstrInfo()->getRegisterInfo();
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}
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/// Returns the minimum alignment known to hold of the
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/// stack frame on entry to the function and which must be maintained by every
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/// function for this subtarget.
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unsigned getStackAlignment() const { return stackAlignment; }
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/// Returns the maximum memset / memcpy size
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/// that still makes it profitable to inline the call.
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unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
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/// ParseSubtargetFeatures - Parses features string setting specified
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/// subtarget options. Definition of function is auto generated by tblgen.
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void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
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private:
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/// Initialize the full set of dependencies so we can use an initializer
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/// list for X86Subtarget.
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X86Subtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
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void initializeEnvironment();
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void initSubtargetFeatures(StringRef CPU, StringRef FS);
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public:
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/// Is this x86_64? (disregarding specific ABI / programming model)
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bool is64Bit() const {
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return In64BitMode;
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}
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bool is32Bit() const {
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return In32BitMode;
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}
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bool is16Bit() const {
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return In16BitMode;
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}
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/// Is this x86_64 with the ILP32 programming model (x32 ABI)?
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bool isTarget64BitILP32() const {
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return In64BitMode && (TargetTriple.getEnvironment() == Triple::GNUX32 ||
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TargetTriple.isOSNaCl());
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}
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/// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
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bool isTarget64BitLP64() const {
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return In64BitMode && (TargetTriple.getEnvironment() != Triple::GNUX32 &&
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!TargetTriple.isOSNaCl());
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}
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PICStyles::Style getPICStyle() const { return PICStyle; }
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void setPICStyle(PICStyles::Style Style) { PICStyle = Style; }
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bool hasX87() const { return HasX87; }
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bool hasCMov() const { return HasCMov; }
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bool hasSSE1() const { return X86SSELevel >= SSE1; }
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bool hasSSE2() const { return X86SSELevel >= SSE2; }
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bool hasSSE3() const { return X86SSELevel >= SSE3; }
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bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
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bool hasSSE41() const { return X86SSELevel >= SSE41; }
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bool hasSSE42() const { return X86SSELevel >= SSE42; }
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bool hasAVX() const { return X86SSELevel >= AVX; }
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bool hasAVX2() const { return X86SSELevel >= AVX2; }
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bool hasAVX512() const { return X86SSELevel >= AVX512F; }
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bool hasFp256() const { return hasAVX(); }
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bool hasInt256() const { return hasAVX2(); }
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bool hasSSE4A() const { return HasSSE4A; }
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bool hasMMX() const { return X863DNowLevel >= MMX; }
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bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
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bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
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bool hasPOPCNT() const { return HasPOPCNT; }
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bool hasAES() const { return HasAES; }
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bool hasFXSR() const { return HasFXSR; }
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bool hasXSAVE() const { return HasXSAVE; }
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bool hasXSAVEOPT() const { return HasXSAVEOPT; }
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bool hasXSAVEC() const { return HasXSAVEC; }
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bool hasXSAVES() const { return HasXSAVES; }
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bool hasPCLMUL() const { return HasPCLMUL; }
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// Prefer FMA4 to FMA - its better for commutation/memory folding and
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// has equal or better performance on all supported targets.
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bool hasFMA() const { return HasFMA && !HasFMA4; }
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bool hasFMA4() const { return HasFMA4; }
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bool hasAnyFMA() const { return hasFMA() || hasFMA4() || hasAVX512(); }
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bool hasXOP() const { return HasXOP; }
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bool hasTBM() const { return HasTBM; }
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bool hasMOVBE() const { return HasMOVBE; }
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bool hasRDRAND() const { return HasRDRAND; }
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bool hasF16C() const { return HasF16C; }
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bool hasFSGSBase() const { return HasFSGSBase; }
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bool hasLZCNT() const { return HasLZCNT; }
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bool hasBMI() const { return HasBMI; }
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bool hasBMI2() const { return HasBMI2; }
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bool hasVBMI() const { return HasVBMI; }
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bool hasIFMA() const { return HasIFMA; }
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bool hasRTM() const { return HasRTM; }
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bool hasHLE() const { return HasHLE; }
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bool hasADX() const { return HasADX; }
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bool hasSHA() const { return HasSHA; }
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bool hasPRFCHW() const { return HasPRFCHW; }
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bool hasRDSEED() const { return HasRDSEED; }
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bool hasLAHFSAHF() const { return HasLAHFSAHF; }
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bool hasMWAITX() const { return HasMWAITX; }
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bool isBTMemSlow() const { return IsBTMemSlow; }
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bool isSHLDSlow() const { return IsSHLDSlow; }
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bool isUnalignedMem16Slow() const { return IsUAMem16Slow; }
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bool isUnalignedMem32Slow() const { return IsUAMem32Slow; }
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bool hasSSEUnalignedMem() const { return HasSSEUnalignedMem; }
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bool hasCmpxchg16b() const { return HasCmpxchg16b; }
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bool useLeaForSP() const { return UseLeaForSP; }
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bool hasFastPartialYMMWrite() const { return HasFastPartialYMMWrite; }
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bool hasSlowDivide32() const { return HasSlowDivide32; }
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bool hasSlowDivide64() const { return HasSlowDivide64; }
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bool padShortFunctions() const { return PadShortFunctions; }
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bool callRegIndirect() const { return CallRegIndirect; }
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bool LEAusesAG() const { return LEAUsesAG; }
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bool slowLEA() const { return SlowLEA; }
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bool slowIncDec() const { return SlowIncDec; }
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bool hasCDI() const { return HasCDI; }
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bool hasPFI() const { return HasPFI; }
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bool hasERI() const { return HasERI; }
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bool hasDQI() const { return HasDQI; }
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bool hasBWI() const { return HasBWI; }
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bool hasVLX() const { return HasVLX; }
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bool hasPKU() const { return HasPKU; }
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bool hasMPX() const { return HasMPX; }
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bool isAtom() const { return X86ProcFamily == IntelAtom; }
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bool isSLM() const { return X86ProcFamily == IntelSLM; }
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bool useSoftFloat() const { return UseSoftFloat; }
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/// Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
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/// no-sse2). There isn't any reason to disable it if the target processor
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/// supports it.
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bool hasMFence() const { return hasSSE2() || is64Bit(); }
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const Triple &getTargetTriple() const { return TargetTriple; }
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bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
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bool isTargetFreeBSD() const { return TargetTriple.isOSFreeBSD(); }
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bool isTargetDragonFly() const { return TargetTriple.isOSDragonFly(); }
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bool isTargetSolaris() const { return TargetTriple.isOSSolaris(); }
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bool isTargetPS4() const { return TargetTriple.isPS4(); }
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bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
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bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
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bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
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bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
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bool isTargetKFreeBSD() const { return TargetTriple.isOSKFreeBSD(); }
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bool isTargetGlibc() const { return TargetTriple.isOSGlibc(); }
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bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
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bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
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bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
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bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
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bool isTargetMCU() const { return TargetTriple.isOSIAMCU(); }
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bool isTargetWindowsMSVC() const {
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return TargetTriple.isWindowsMSVCEnvironment();
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}
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bool isTargetKnownWindowsMSVC() const {
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return TargetTriple.isKnownWindowsMSVCEnvironment();
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}
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bool isTargetWindowsCoreCLR() const {
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return TargetTriple.isWindowsCoreCLREnvironment();
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}
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bool isTargetWindowsCygwin() const {
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return TargetTriple.isWindowsCygwinEnvironment();
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}
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bool isTargetWindowsGNU() const {
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return TargetTriple.isWindowsGNUEnvironment();
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}
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bool isTargetWindowsItanium() const {
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return TargetTriple.isWindowsItaniumEnvironment();
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}
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bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
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bool isOSWindows() const { return TargetTriple.isOSWindows(); }
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bool isTargetWin64() const {
|
|
return In64BitMode && TargetTriple.isOSWindows();
|
|
}
|
|
|
|
bool isTargetWin32() const {
|
|
return !In64BitMode && (isTargetCygMing() || isTargetKnownWindowsMSVC());
|
|
}
|
|
|
|
bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; }
|
|
bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; }
|
|
|
|
bool isPICStyleStubPIC() const {
|
|
return PICStyle == PICStyles::StubPIC;
|
|
}
|
|
|
|
bool isPositionIndependent() const { return TM.isPositionIndependent(); }
|
|
|
|
bool isCallingConvWin64(CallingConv::ID CC) const {
|
|
switch (CC) {
|
|
// On Win64, all these conventions just use the default convention.
|
|
case CallingConv::C:
|
|
case CallingConv::Fast:
|
|
case CallingConv::X86_FastCall:
|
|
case CallingConv::X86_StdCall:
|
|
case CallingConv::X86_ThisCall:
|
|
case CallingConv::X86_VectorCall:
|
|
case CallingConv::Intel_OCL_BI:
|
|
return isTargetWin64();
|
|
// This convention allows using the Win64 convention on other targets.
|
|
case CallingConv::X86_64_Win64:
|
|
return true;
|
|
// This convention allows using the SysV convention on Windows targets.
|
|
case CallingConv::X86_64_SysV:
|
|
return false;
|
|
// Otherwise, who knows what this is.
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
/// Classify a global variable reference for the current subtarget according
|
|
/// to how we should reference it in a non-pcrel context.
|
|
unsigned char classifyLocalReference(const GlobalValue *GV) const;
|
|
|
|
unsigned char classifyGlobalReference(const GlobalValue *GV,
|
|
const Module &M) const;
|
|
unsigned char classifyGlobalReference(const GlobalValue *GV) const;
|
|
|
|
/// Classify a global function reference for the current subtarget.
|
|
unsigned char classifyGlobalFunctionReference(const GlobalValue *GV,
|
|
const Module &M) const;
|
|
unsigned char classifyGlobalFunctionReference(const GlobalValue *GV) const;
|
|
|
|
/// Classify a blockaddress reference for the current subtarget according to
|
|
/// how we should reference it in a non-pcrel context.
|
|
unsigned char classifyBlockAddressReference() const;
|
|
|
|
/// Return true if the subtarget allows calls to immediate address.
|
|
bool isLegalToCallImmediateAddr() const;
|
|
|
|
/// This function returns the name of a function which has an interface
|
|
/// like the non-standard bzero function, if such a function exists on
|
|
/// the current subtarget and it is considered prefereable over
|
|
/// memset with zero passed as the second argument. Otherwise it
|
|
/// returns null.
|
|
const char *getBZeroEntry() const;
|
|
|
|
/// This function returns true if the target has sincos() routine in its
|
|
/// compiler runtime or math libraries.
|
|
bool hasSinCos() const;
|
|
|
|
/// Enable the MachineScheduler pass for all X86 subtargets.
|
|
bool enableMachineScheduler() const override { return true; }
|
|
|
|
bool enableEarlyIfConversion() const override;
|
|
|
|
/// Return the instruction itineraries based on the subtarget selection.
|
|
const InstrItineraryData *getInstrItineraryData() const override {
|
|
return &InstrItins;
|
|
}
|
|
|
|
AntiDepBreakMode getAntiDepBreakMode() const override {
|
|
return TargetSubtargetInfo::ANTIDEP_CRITICAL;
|
|
}
|
|
};
|
|
|
|
} // End llvm namespace
|
|
|
|
#endif
|