492 lines
18 KiB
ArmAsm
492 lines
18 KiB
ArmAsm
; RUN: not llvm-mc -triple arm64-apple-darwin -show-encoding < %s 2> %t | FileCheck %s
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; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
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foo:
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; The first should encode as an expression. The second should error expecting
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; a register.
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ldr x3, (foo + 4)
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ldr x3, [foo + 4]
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; CHECK: ldr x3, foo+4 ; encoding: [0bAAA00011,A,A,0x58]
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; CHECK: ; fixup A - offset: 0, value: foo+4, kind: fixup_aarch64_ldr_pcrel_imm19
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; CHECK-ERRORS: error: invalid operand for instruction
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; The last argument should be flagged as an error. rdar://9576009
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ld4.8b {v0, v1, v2, v3}, [x0], #33
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; CHECK-ERRORS: error: invalid operand for instruction
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; CHECK-ERRORS: ld4.8b {v0, v1, v2, v3}, [x0], #33
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ldr x0, [x0, #804]
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ldr w0, [x0, #802]
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ldr x0, [x0, #804]!
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ldr w0, [w0, #301]!
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ldr x0, [x0], #804
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ldr w0, [w0], #301
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ldp w3, w4, [x5, #11]!
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ldp x3, x4, [x5, #12]!
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ldp q3, q4, [x5, #12]!
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ldp w3, w4, [x5], #11
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ldp x3, x4, [x5], #12
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ldp q3, q4, [x5], #12
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ldur x0, [x1, #-257]
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; CHECK-ERRORS: error: index must be an integer in range [-256, 255].
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; CHECK-ERRORS: ldr x0, [x0, #804]
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: index must be an integer in range [-256, 255].
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; CHECK-ERRORS: ldr w0, [x0, #802]
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: index must be an integer in range [-256, 255].
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; CHECK-ERRORS: ldr x0, [x0, #804]!
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: invalid operand for instruction
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; CHECK-ERRORS: ldr w0, [w0, #301]!
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: index must be an integer in range [-256, 255].
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; CHECK-ERRORS: ldr x0, [x0], #804
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: invalid operand for instruction
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; CHECK-ERRORS: ldr w0, [w0], #301
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: index must be a multiple of 4 in range [-256, 252].
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; CHECK-ERRORS: ldp w3, w4, [x5, #11]!
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: index must be a multiple of 8 in range [-512, 504].
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; CHECK-ERRORS: ldp x3, x4, [x5, #12]!
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: index must be a multiple of 16 in range [-1024, 1008].
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; CHECK-ERRORS: ldp q3, q4, [x5, #12]!
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: index must be a multiple of 4 in range [-256, 252].
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; CHECK-ERRORS: ldp w3, w4, [x5], #11
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: index must be a multiple of 8 in range [-512, 504].
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; CHECK-ERRORS: ldp x3, x4, [x5], #12
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: index must be a multiple of 16 in range [-1024, 1008].
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; CHECK-ERRORS: ldp q3, q4, [x5], #12
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: index must be an integer in range [-256, 255].
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; CHECK-ERRORS: ldur x0, [x1, #-257]
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; CHECK-ERRORS: ^
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ldrb w1, [x3, w3, sxtw #4]
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ldrh w1, [x3, w3, sxtw #4]
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ldr w1, [x3, w3, sxtw #4]
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ldr x1, [x3, w3, sxtw #4]
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ldr b1, [x3, w3, sxtw #4]
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ldr h1, [x3, w3, sxtw #4]
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ldr s1, [x3, w3, sxtw #4]
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ldr d1, [x3, w3, sxtw #4]
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ldr q1, [x3, w3, sxtw #1]
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; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0
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; CHECK-ERRORS:ldrb w1, [x3, w3, sxtw #4]
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #1
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; CHECK-ERRORS:ldrh w1, [x3, w3, sxtw #4]
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #2
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; CHECK-ERRORS:ldr w1, [x3, w3, sxtw #4]
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #3
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; CHECK-ERRORS:ldr x1, [x3, w3, sxtw #4]
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0
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; CHECK-ERRORS:ldr b1, [x3, w3, sxtw #4]
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #1
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; CHECK-ERRORS:ldr h1, [x3, w3, sxtw #4]
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #2
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; CHECK-ERRORS:ldr s1, [x3, w3, sxtw #4]
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #3
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; CHECK-ERRORS:ldr d1, [x3, w3, sxtw #4]
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #4
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; CHECK-ERRORS:ldr q1, [x3, w3, sxtw #1]
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; CHECK-ERRORS: ^
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; Check that register offset addressing modes only accept 32-bit offset
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; registers when using uxtw/sxtw extends. Everything else requires a 64-bit
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; register.
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str d1, [x3, w3, sxtx #3]
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ldr s1, [x3, d3, sxtx #2]
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; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #3
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; CHECK-ERRORS: str d1, [x3, w3, sxtx #3]
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: index must be an integer in range [-256, 255].
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; CHECK-ERRORS: ldr s1, [x3, d3, sxtx #2]
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; CHECK-ERRORS: ^
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; Shift immediates range checking.
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sqrshrn b4, h9, #10
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rshrn v9.8b, v11.8h, #17
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sqrshrn v7.4h, v8.4s, #39
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uqshrn2 v4.4s, v5.2d, #67
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; CHECK-ERRORS: error: immediate must be an integer in range [1, 8].
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; CHECK-ERRORS: sqrshrn b4, h9, #10
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: immediate must be an integer in range [1, 8].
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; CHECK-ERRORS: rshrn v9.8b, v11.8h, #17
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: immediate must be an integer in range [1, 16].
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; CHECK-ERRORS: sqrshrn v7.4h, v8.4s, #39
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: immediate must be an integer in range [1, 32].
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; CHECK-ERRORS: uqshrn2 v4.4s, v5.2d, #67
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; CHECK-ERRORS: ^
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st1.s4 {v14, v15}, [x2], #32
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; CHECK-ERRORS: error: invalid type suffix for instruction
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; CHECK-ERRORS: st1.s4 {v14, v15}, [x2], #32
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; CHECK-ERRORS: ^
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; Load pair instructions where Rt==Rt2 and writeback load/store instructions
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; where Rt==Rn or Rt2==Rn are unpredicatable.
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ldp x1, x2, [x2], #16
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ldp x2, x2, [x2], #16
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ldp w1, w2, [x2], #16
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ldp w2, w2, [x2], #16
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ldp x1, x1, [x2]
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ldp s1, s1, [x1], #8
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ldp s1, s1, [x1, #8]!
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ldp s1, s1, [x1, #8]
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ldp d1, d1, [x1], #16
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ldp d1, d1, [x1, #16]!
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ldp d1, d1, [x1, #16]
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ldp q1, q1, [x1], #32
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ldp q1, q1, [x1, #32]!
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ldp q1, q1, [x1, #32]
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ldr x2, [x2], #8
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ldr x2, [x2, #8]!
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ldr w2, [x2], #8
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ldr w2, [x2, #8]!
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str x2, [x2], #8
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str x2, [x2, #8]!
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str w2, [x2], #8
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str w2, [x2, #8]!
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; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination
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; CHECK-ERRORS: ldp x1, x2, [x2], #16
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination
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; CHECK-ERRORS: ldp x2, x2, [x2], #16
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination
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; CHECK-ERRORS: ldp w1, w2, [x2], #16
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination
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; CHECK-ERRORS: ldp w2, w2, [x2], #16
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
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; CHECK-ERRORS: ldp x1, x1, [x2]
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
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; CHECK-ERRORS: ldp s1, s1, [x1], #8
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
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; CHECK-ERRORS: ldp s1, s1, [x1, #8]!
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
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; CHECK-ERRORS: ldp s1, s1, [x1, #8]
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
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; CHECK-ERRORS: ldp d1, d1, [x1], #16
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
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; CHECK-ERRORS: ldp d1, d1, [x1, #16]!
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
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; CHECK-ERRORS: ldp d1, d1, [x1, #16]
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
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; CHECK-ERRORS: ldp q1, q1, [x1], #32
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
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; CHECK-ERRORS: ldp q1, q1, [x1, #32]!
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
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; CHECK-ERRORS: ldp q1, q1, [x1, #32]
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source
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; CHECK-ERRORS: ldr x2, [x2], #8
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source
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; CHECK-ERRORS: ldr x2, [x2, #8]!
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source
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; CHECK-ERRORS: ldr w2, [x2], #8
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source
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; CHECK-ERRORS: ldr w2, [x2, #8]!
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: unpredictable STR instruction, writeback base is also a source
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; CHECK-ERRORS: str x2, [x2], #8
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: unpredictable STR instruction, writeback base is also a source
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; CHECK-ERRORS: str x2, [x2, #8]!
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: unpredictable STR instruction, writeback base is also a source
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; CHECK-ERRORS: str w2, [x2], #8
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: unpredictable STR instruction, writeback base is also a source
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; CHECK-ERRORS: str w2, [x2, #8]!
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; CHECK-ERRORS: ^
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; The validity checking for shifted-immediate operands. rdar://13174476
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; Where the immediate is out of range.
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add w1, w2, w3, lsr #75
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; CHECK-ERRORS: error: expected 'sxtx' 'uxtx' or 'lsl' with optional integer in range [0, 4]
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; CHECK-ERRORS: add w1, w2, w3, lsr #75
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; CHECK-ERRORS: ^
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; logical instructions on 32-bit regs with shift > 31 is not legal
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orr w0, w0, w0, lsl #32
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; CHECK-ERRORS: error: expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 31]
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; CHECK-ERRORS: orr w0, w0, w0, lsl #32
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; CHECK-ERRORS: ^
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eor w0, w0, w0, lsl #32
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; CHECK-ERRORS: error: expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 31]
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; CHECK-ERRORS: eor w0, w0, w0, lsl #32
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; CHECK-ERRORS: ^
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and w0, w0, w0, lsl #32
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; CHECK-ERRORS: error: expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 31]
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; CHECK-ERRORS: and w0, w0, w0, lsl #32
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; CHECK-ERRORS: ^
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ands w0, w0, w0, lsl #32
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; CHECK-ERRORS: error: expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 31]
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; CHECK-ERRORS: ands w0, w0, w0, lsl #32
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; CHECK-ERRORS: ^
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; Relocated expressions should not be accepted for 32-bit adds or sub (imm)
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add w3, w5, sym@PAGEOFF
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; CHECK-ERRORS: error: invalid immediate expression
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; CHECK-ERRORS: add w3, w5, sym@PAGEOFF
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; CHECK-ERRORS: ^
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adds w3, w5, sym@PAGEOFF
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adds x9, x12, sym@PAGEOFF
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; CHECK-ERRORS: error: invalid immediate expression
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; CHECK-ERRORS: adds w3, w5, sym@PAGEOFF
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: invalid immediate expression
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; CHECK-ERRORS: adds x9, x12, sym@PAGEOFF
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; CHECK-ERRORS: ^
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sub x3, x5, sym@PAGEOFF
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sub w20, w30, sym@PAGEOFF
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; CHECK-ERRORS: error: invalid immediate expression
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; CHECK-ERRORS: sub x3, x5, sym@PAGEOFF
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: invalid immediate expression
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; CHECK-ERRORS: sub w20, w30, sym@PAGEOFF
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; CHECK-ERRORS: ^
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subs w9, w10, sym@PAGEOFF
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subs x20, x30, sym@PAGEOFF
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; CHECK-ERRORS: error: invalid immediate expression
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; CHECK-ERRORS: subs w9, w10, sym@PAGEOFF
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: invalid immediate expression
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; CHECK-ERRORS: subs x20, x30, sym@PAGEOFF
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; CHECK-ERRORS: ^
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tbl v0.8b, { v1 }, v0.8b
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tbl v0.16b, { v1.8b, v2.8b, v3.8b }, v0.16b
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tbx v3.16b, { v12.8b, v13.8b, v14.8b }, v6.8b
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tbx v2.8b, { v0 }, v6.8b
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; CHECK-ERRORS: error: invalid operand for instruction
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; CHECK-ERRORS: tbl v0.8b, { v1 }, v0.8b
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: invalid operand for instruction
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; CHECK-ERRORS: tbl v0.16b, { v1.8b, v2.8b, v3.8b }, v0.16b
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: invalid operand for instruction
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; CHECK-ERRORS: tbx v3.16b, { v12.8b, v13.8b, v14.8b }, v6.8b
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; CHECK-ERRORS: ^
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; CHECK-ERRORS: error: invalid operand for instruction
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; CHECK-ERRORS: tbx v2.8b, { v0 }, v6.8b
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; CHECK-ERRORS: ^
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b.c #0x4
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; CHECK-ERRORS: error: invalid condition code
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; CHECK-ERRORS: b.c #0x4
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; CHECK-ERRORS: ^
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ic ialluis, x0
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; CHECK-ERRORS: error: specified ic op does not use a register
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ic iallu, x0
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; CHECK-ERRORS: error: specified ic op does not use a register
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ic ivau
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; CHECK-ERRORS: error: specified ic op requires a register
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dc zva
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; CHECK-ERRORS: error: specified dc op requires a register
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dc ivac
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; CHECK-ERRORS: error: specified dc op requires a register
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dc isw
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; CHECK-ERRORS: error: specified dc op requires a register
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dc cvac
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; CHECK-ERRORS: error: specified dc op requires a register
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dc csw
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; CHECK-ERRORS: error: specified dc op requires a register
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dc cvau
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; CHECK-ERRORS: error: specified dc op requires a register
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dc civac
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; CHECK-ERRORS: error: specified dc op requires a register
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dc cisw
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; CHECK-ERRORS: error: specified dc op requires a register
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at s1e1r
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; CHECK-ERRORS: error: specified at op requires a register
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at s1e2r
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; CHECK-ERRORS: error: specified at op requires a register
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at s1e3r
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; CHECK-ERRORS: error: specified at op requires a register
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at s1e1w
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; CHECK-ERRORS: error: specified at op requires a register
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at s1e2w
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; CHECK-ERRORS: error: specified at op requires a register
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at s1e3w
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; CHECK-ERRORS: error: specified at op requires a register
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at s1e0r
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; CHECK-ERRORS: error: specified at op requires a register
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at s1e0w
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; CHECK-ERRORS: error: specified at op requires a register
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at s12e1r
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; CHECK-ERRORS: error: specified at op requires a register
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at s12e1w
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; CHECK-ERRORS: error: specified at op requires a register
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at s12e0r
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; CHECK-ERRORS: error: specified at op requires a register
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at s12e0w
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; CHECK-ERRORS: error: specified at op requires a register
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tlbi vmalle1is, x0
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; CHECK-ERRORS: error: specified tlbi op does not use a register
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tlbi vmalle1, x0
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; CHECK-ERRORS: error: specified tlbi op does not use a register
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tlbi alle1is, x0
|
|
; CHECK-ERRORS: error: specified tlbi op does not use a register
|
|
tlbi alle2is, x0
|
|
; CHECK-ERRORS: error: specified tlbi op does not use a register
|
|
tlbi alle3is, x0
|
|
; CHECK-ERRORS: error: specified tlbi op does not use a register
|
|
tlbi alle1, x0
|
|
; CHECK-ERRORS: error: specified tlbi op does not use a register
|
|
tlbi alle2, x0
|
|
; CHECK-ERRORS: error: specified tlbi op does not use a register
|
|
tlbi alle3, x0
|
|
; CHECK-ERRORS: error: specified tlbi op does not use a register
|
|
tlbi vae1is
|
|
; CHECK-ERRORS: error: specified tlbi op requires a register
|
|
tlbi vae2is
|
|
; CHECK-ERRORS: error: specified tlbi op requires a register
|
|
tlbi vae3is
|
|
; CHECK-ERRORS: error: specified tlbi op requires a register
|
|
tlbi aside1is
|
|
; CHECK-ERRORS: error: specified tlbi op requires a register
|
|
tlbi vaae1is
|
|
; CHECK-ERRORS: error: specified tlbi op requires a register
|
|
tlbi vale1is
|
|
; CHECK-ERRORS: error: specified tlbi op requires a register
|
|
tlbi vaale1is
|
|
; CHECK-ERRORS: error: specified tlbi op requires a register
|
|
tlbi vale2is
|
|
; CHECK-ERRORS: error: specified tlbi op requires a register
|
|
tlbi vale3is
|
|
; CHECK-ERRORS: error: specified tlbi op requires a register
|
|
tlbi vae1
|
|
; CHECK-ERRORS: error: specified tlbi op requires a register
|
|
tlbi vae2
|
|
; CHECK-ERRORS: error: specified tlbi op requires a register
|
|
tlbi vae3
|
|
; CHECK-ERRORS: error: specified tlbi op requires a register
|
|
tlbi aside1
|
|
; CHECK-ERRORS: error: specified tlbi op requires a register
|
|
tlbi vaae1
|
|
; CHECK-ERRORS: error: specified tlbi op requires a register
|
|
tlbi vale1
|
|
; CHECK-ERRORS: error: specified tlbi op requires a register
|
|
tlbi vale2
|
|
; CHECK-ERRORS: error: specified tlbi op requires a register
|
|
tlbi vale3
|
|
; CHECK-ERRORS: error: specified tlbi op requires a register
|
|
|
|
|
|
; Check that we give the proper "too few operands" diagnostic even when
|
|
; using short-form NEON.
|
|
|
|
add.16b v0, v1, v2, v3
|
|
add.8b v0, v1
|
|
sub.8h v0, v1
|
|
fadd.4s v0
|
|
fmul.2s
|
|
|
|
; CHECK-ERRORS: error: invalid operand for instruction
|
|
; CHECK-ERRORS: add.16b v0, v1, v2, v3
|
|
; CHECK-ERRORS: ^
|
|
; CHECK-ERRORS: error: too few operands for instruction
|
|
; CHECK-ERRORS: add.8b v0, v1
|
|
; CHECK-ERRORS: ^
|
|
; CHECK-ERRORS: error: too few operands for instruction
|
|
; CHECK-ERRORS: sub.8h v0, v1
|
|
; CHECK-ERRORS: ^
|
|
; CHECK-ERRORS: error: too few operands for instruction
|
|
; CHECK-ERRORS: fadd.4s v0
|
|
; CHECK-ERRORS: ^
|
|
; CHECK-ERRORS: error: too few operands for instruction
|
|
; CHECK-ERRORS: fmul.2s
|
|
; CHECK-ERRORS: ^
|
|
|
|
; Also for 2-operand instructions.
|
|
|
|
frsqrte.4s v0, v1, v2
|
|
frsqrte.2s v0
|
|
frecpe.2d
|
|
|
|
; CHECK-ERRORS: error: invalid operand for instruction
|
|
; CHECK-ERRORS: frsqrte.4s v0, v1, v2
|
|
; CHECK-ERRORS: ^
|
|
; CHECK-ERRORS: error: too few operands for instruction
|
|
; CHECK-ERRORS: frsqrte.2s v0
|
|
; CHECK-ERRORS: ^
|
|
; CHECK-ERRORS: error: too few operands for instruction
|
|
; CHECK-ERRORS: frecpe.2d
|
|
; CHECK-ERRORS: ^
|
|
|
|
; And check that we do the same for non-NEON instructions.
|
|
|
|
b.ne
|
|
b.eq 0, 0
|
|
|
|
; CHECK-ERRORS: error: too few operands for instruction
|
|
; CHECK-ERRORS: b.ne
|
|
; CHECK-ERRORS: ^
|
|
; CHECK-ERRORS: error: invalid operand for instruction
|
|
; CHECK-ERRORS: b.eq 0, 0
|
|
; CHECK-ERRORS: ^
|
|
|
|
; Check that we give the proper "too few operands" diagnostic instead of
|
|
; asserting.
|
|
|
|
ldr
|
|
|
|
; CHECK-ERRORS: error: too few operands for instruction
|
|
; CHECK-ERRORS: ldr
|
|
; CHECK-ERRORS: ^
|