137 lines
5.8 KiB
ArmAsm
137 lines
5.8 KiB
ArmAsm
// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.1a -show-encoding < %s 2> %t | FileCheck %s
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// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s
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.text
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//AdvSIMD RDMA vector
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sqrdmlah v0.4h, v1.4h, v2.4h
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sqrdmlsh v0.4h, v1.4h, v2.4h
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sqrdmlah v0.2s, v1.2s, v2.2s
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sqrdmlsh v0.2s, v1.2s, v2.2s
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sqrdmlah v0.4s, v1.4s, v2.4s
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sqrdmlsh v0.4s, v1.4s, v2.4s
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sqrdmlah v0.8h, v1.8h, v2.8h
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sqrdmlsh v0.8h, v1.8h, v2.8h
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// CHECK: sqrdmlah v0.4h, v1.4h, v2.4h // encoding: [0x20,0x84,0x42,0x2e]
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// CHECK: sqrdmlsh v0.4h, v1.4h, v2.4h // encoding: [0x20,0x8c,0x42,0x2e]
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// CHECK: sqrdmlah v0.2s, v1.2s, v2.2s // encoding: [0x20,0x84,0x82,0x2e]
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// CHECK: sqrdmlsh v0.2s, v1.2s, v2.2s // encoding: [0x20,0x8c,0x82,0x2e]
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// CHECK: sqrdmlah v0.4s, v1.4s, v2.4s // encoding: [0x20,0x84,0x82,0x6e]
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// CHECK: sqrdmlsh v0.4s, v1.4s, v2.4s // encoding: [0x20,0x8c,0x82,0x6e]
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// CHECK: sqrdmlah v0.8h, v1.8h, v2.8h // encoding: [0x20,0x84,0x42,0x6e]
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// CHECK: sqrdmlsh v0.8h, v1.8h, v2.8h // encoding: [0x20,0x8c,0x42,0x6e]
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sqrdmlah v0.2h, v1.2h, v2.2h
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sqrdmlsh v0.2h, v1.2h, v2.2h
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sqrdmlah v0.8s, v1.8s, v2.8s
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sqrdmlsh v0.8s, v1.8s, v2.8s
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sqrdmlah v0.2s, v1.4h, v2.8h
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sqrdmlsh v0.4s, v1.8h, v2.2s
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: sqrdmlah v0.2h, v1.2h, v2.2h
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: sqrdmlsh v0.2h, v1.2h, v2.2h
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: invalid vector kind qualifier
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// CHECK-ERROR: sqrdmlah v0.8s, v1.8s, v2.8s
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: invalid vector kind qualifier
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// CHECK-ERROR: sqrdmlah v0.8s, v1.8s, v2.8s
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: invalid vector kind qualifier
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// CHECK-ERROR: sqrdmlah v0.8s, v1.8s, v2.8s
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: sqrdmlah v0.8s, v1.8s, v2.8s
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: invalid vector kind qualifier
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// CHECK-ERROR: sqrdmlsh v0.8s, v1.8s, v2.8s
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: invalid vector kind qualifier
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// CHECK-ERROR: sqrdmlsh v0.8s, v1.8s, v2.8s
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: invalid vector kind qualifier
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// CHECK-ERROR: sqrdmlsh v0.8s, v1.8s, v2.8s
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: sqrdmlsh v0.8s, v1.8s, v2.8s
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: sqrdmlah v0.2s, v1.4h, v2.8h
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: sqrdmlsh v0.4s, v1.8h, v2.2s
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// CHECK-ERROR: ^
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//AdvSIMD RDMA scalar
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sqrdmlah h0, h1, h2
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sqrdmlsh h0, h1, h2
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sqrdmlah s0, s1, s2
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sqrdmlsh s0, s1, s2
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// CHECK: sqrdmlah h0, h1, h2 // encoding: [0x20,0x84,0x42,0x7e]
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// CHECK: sqrdmlsh h0, h1, h2 // encoding: [0x20,0x8c,0x42,0x7e]
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// CHECK: sqrdmlah s0, s1, s2 // encoding: [0x20,0x84,0x82,0x7e]
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// CHECK: sqrdmlsh s0, s1, s2 // encoding: [0x20,0x8c,0x82,0x7e]
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//AdvSIMD RDMA vector by-element
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sqrdmlah v0.4h, v1.4h, v2.h[3]
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sqrdmlsh v0.4h, v1.4h, v2.h[3]
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sqrdmlah v0.2s, v1.2s, v2.s[1]
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sqrdmlsh v0.2s, v1.2s, v2.s[1]
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sqrdmlah v0.8h, v1.8h, v2.h[3]
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sqrdmlsh v0.8h, v1.8h, v2.h[3]
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sqrdmlah v0.4s, v1.4s, v2.s[3]
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sqrdmlsh v0.4s, v1.4s, v2.s[3]
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// CHECK: sqrdmlah v0.4h, v1.4h, v2.h[3] // encoding: [0x20,0xd0,0x72,0x2f]
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// CHECK: sqrdmlsh v0.4h, v1.4h, v2.h[3] // encoding: [0x20,0xf0,0x72,0x2f]
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// CHECK: sqrdmlah v0.2s, v1.2s, v2.s[1] // encoding: [0x20,0xd0,0xa2,0x2f]
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// CHECK: sqrdmlsh v0.2s, v1.2s, v2.s[1] // encoding: [0x20,0xf0,0xa2,0x2f]
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// CHECK: sqrdmlah v0.8h, v1.8h, v2.h[3] // encoding: [0x20,0xd0,0x72,0x6f]
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// CHECK: sqrdmlsh v0.8h, v1.8h, v2.h[3] // encoding: [0x20,0xf0,0x72,0x6f]
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// CHECK: sqrdmlah v0.4s, v1.4s, v2.s[3] // encoding: [0x20,0xd8,0xa2,0x6f]
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// CHECK: sqrdmlsh v0.4s, v1.4s, v2.s[3] // encoding: [0x20,0xf8,0xa2,0x6f]
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sqrdmlah v0.4s, v1.2s, v2.s[1]
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sqrdmlsh v0.2s, v1.2d, v2.s[1]
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sqrdmlah v0.8h, v1.8h, v2.s[3]
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sqrdmlsh v0.8h, v1.8h, v2.h[8]
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: sqrdmlah v0.4s, v1.2s, v2.s[1]
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: sqrdmlsh v0.2s, v1.2d, v2.s[1]
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: sqrdmlah v0.8h, v1.8h, v2.s[3]
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: vector lane must be an integer in range [0, 7].
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// CHECK-ERROR: sqrdmlsh v0.8h, v1.8h, v2.h[8]
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// CHECK-ERROR: ^
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//AdvSIMD RDMA scalar by-element
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sqrdmlah h0, h1, v2.h[3]
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sqrdmlsh h0, h1, v2.h[3]
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sqrdmlah s0, s1, v2.s[3]
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sqrdmlsh s0, s1, v2.s[3]
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// CHECK: sqrdmlah h0, h1, v2.h[3] // encoding: [0x20,0xd0,0x72,0x7f]
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// CHECK: sqrdmlsh h0, h1, v2.h[3] // encoding: [0x20,0xf0,0x72,0x7f]
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// CHECK: sqrdmlah s0, s1, v2.s[3] // encoding: [0x20,0xd8,0xa2,0x7f]
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// CHECK: sqrdmlsh s0, s1, v2.s[3] // encoding: [0x20,0xf8,0xa2,0x7f]
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sqrdmlah b0, h1, v2.h[3]
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sqrdmlah s0, d1, v2.s[3]
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sqrdmlsh h0, h1, v2.s[3]
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sqrdmlsh s0, s1, v2.s[4]
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: sqrdmlah b0, h1, v2.h[3]
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: sqrdmlah s0, d1, v2.s[3]
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: sqrdmlsh h0, h1, v2.s[3]
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: vector lane must be an integer in range [0, 3].
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// CHECK-ERROR: sqrdmlsh s0, s1, v2.s[4]
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// CHECK-ERROR: ^
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