54 lines
2.3 KiB
ArmAsm
54 lines
2.3 KiB
ArmAsm
@ RUN: llvm-mc -triple=thumbv7em -show-encoding < %s | FileCheck %s
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@ RUN: not llvm-mc -triple=thumbv7m -show-encoding 2>&1 < %s | FileCheck --check-prefix=CHECK-V7M %s
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.syntax unified
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@ Check that the assembler can handle the documented syntax from the ARM ARM.
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@ These tests test instruction encodings specific to ARMv7E-M.
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@------------------------------------------------------------------------------
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@ MSR
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@------------------------------------------------------------------------------
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msr apsr_g, r0
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msr apsr_nzcvqg, r0
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msr iapsr_g, r0
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msr iapsr_nzcvqg, r0
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msr eapsr_g, r0
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msr eapsr_nzcvqg, r0
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msr xpsr_g, r0
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msr xpsr_nzcvqg, r0
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@ CHECK: msr apsr_g, r0 @ encoding: [0x80,0xf3,0x00,0x84]
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@ CHECK: msr apsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x00,0x8c]
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@ CHECK: msr iapsr_g, r0 @ encoding: [0x80,0xf3,0x01,0x84]
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@ CHECK: msr iapsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x01,0x8c]
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@ CHECK: msr eapsr_g, r0 @ encoding: [0x80,0xf3,0x02,0x84]
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@ CHECK: msr eapsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x02,0x8c]
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@ CHECK: msr xpsr_g, r0 @ encoding: [0x80,0xf3,0x03,0x84]
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@ CHECK: msr xpsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x03,0x8c]
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@ CHECK-V7M: error: invalid operand for instruction
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@ CHECK-V7M-NEXT: msr apsr_g, r0
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@ CHECK-V7M-NEXT: ^
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@ CHECK-V7M: error: invalid operand for instruction
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@ CHECK-V7M-NEXT: msr apsr_nzcvqg, r0
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@ CHECK-V7M-NEXT: ^
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@ CHECK-V7M: error: invalid operand for instruction
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@ CHECK-V7M-NEXT: msr iapsr_g, r0
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@ CHECK-V7M-NEXT: ^
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@ CHECK-V7M: error: invalid operand for instruction
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@ CHECK-V7M-NEXT: msr iapsr_nzcvqg, r0
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@ CHECK-V7M-NEXT: ^
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@ CHECK-V7M: error: invalid operand for instruction
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@ CHECK-V7M-NEXT: msr eapsr_g, r0
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@ CHECK-V7M-NEXT: ^
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@ CHECK-V7M: error: invalid operand for instruction
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@ CHECK-V7M-NEXT: msr eapsr_nzcvqg, r0
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@ CHECK-V7M-NEXT: ^
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@ CHECK-V7M: error: invalid operand for instruction
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@ CHECK-V7M-NEXT: msr xpsr_g, r0
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@ CHECK-V7M-NEXT: ^
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@ CHECK-V7M: error: invalid operand for instruction
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@ CHECK-V7M-NEXT: msr xpsr_nzcvqg, r0
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@ CHECK-V7M-NEXT: ^
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