426 lines
13 KiB
C
426 lines
13 KiB
C
/*
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* Copyright 2004, 2011 Freescale Semiconductor.
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* (C) Copyright 2002,2003 Motorola,Inc.
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* Xianghua Xiao <X.Xiao@motorola.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* mpc8560ads board configuration file
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*
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* Please refer to doc/README.mpc85xx for more info.
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*
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* Make sure you change the MAC address and other network params first,
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* search for CONFIG_SERVERIP, etc. in this file.
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* High Level Configuration Options */
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#define CONFIG_CPM2 1 /* has CPM2 */
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/*
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* default CCARBAR is at 0xff700000
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* assume U-Boot is less than 0.5MB
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*/
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#define CONFIG_SYS_TEXT_BASE 0xfff80000
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#define CONFIG_PCI_INDIRECT_BRIDGE
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#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
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/*
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* sysclk for MPC85xx
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*
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* Two valid values are:
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* 33000000
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* 66000000
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*
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* Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
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* is likely the desired value here, so that is now the default.
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* The board, however, can run at 66MHz. In any event, this value
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* must match the settings of some switches. Details can be found
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* in the README.mpc85xxads.
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*/
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#ifndef CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_CLK_FREQ 33000000
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#endif
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/*
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* These can be toggled for performance analysis, otherwise use default.
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*/
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#define CONFIG_L2_CACHE /* toggle L2 cache */
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#define CONFIG_BTB /* toggle branch predition */
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#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
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#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
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#define CONFIG_SYS_MEMTEST_END 0x00400000
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#define CONFIG_SYS_CCSRBAR 0xe0000000
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#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
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/* DDR Setup */
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#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
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#define CONFIG_DDR_SPD
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#undef CONFIG_FSL_DDR_INTERACTIVE
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#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_DIMM_SLOTS_PER_CTLR 1
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#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
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/* I2C addresses of SPD EEPROMs */
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#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
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/* These are used when DDR doesn't use SPD. */
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#define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */
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#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
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#define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002
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#define CONFIG_SYS_DDR_TIMING_1 0x37344321
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#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
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#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
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#define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
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#define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
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/*
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* SDRAM on the Local Bus
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*/
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#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
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#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
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#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
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#define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
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#define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
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#undef CONFIG_SYS_FLASH_CHECKSUM
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#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
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#define CONFIG_SYS_RAMBOOT
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#else
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#undef CONFIG_SYS_RAMBOOT
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#endif
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#undef CONFIG_CLOCKS_IN_MHZ
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/*
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* Local Bus Definitions
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*/
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/*
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* Base Register 2 and Option Register 2 configure SDRAM.
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* The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
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*
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* For BR2, need:
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* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
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* port-size = 32-bits = BR2[19:20] = 11
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* no parity checking = BR2[21:22] = 00
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* SDRAM for MSEL = BR2[24:26] = 011
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* Valid = BR[31] = 1
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*
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* 0 4 8 12 16 20 24 28
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* 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
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*
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* FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
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* FIXME: the top 17 bits of BR2.
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*/
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#define CONFIG_SYS_BR2_PRELIM 0xf0001861
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/*
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* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
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*
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* For OR2, need:
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* 64MB mask for AM, OR2[0:7] = 1111 1100
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* XAM, OR2[17:18] = 11
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* 9 columns OR2[19-21] = 010
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* 13 rows OR2[23-25] = 100
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* EAD set for extra time OR[31] = 1
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*
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* 0 4 8 12 16 20 24 28
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* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
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*/
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#define CONFIG_SYS_OR2_PRELIM 0xfc006901
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#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
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#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
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#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
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#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
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#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \
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| LSDMR_RFCR5 \
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| LSDMR_PRETOACT3 \
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| LSDMR_ACTTORW3 \
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| LSDMR_BL8 \
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| LSDMR_WRC2 \
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| LSDMR_CL3 \
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| LSDMR_RFEN \
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)
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/*
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* SDRAM Controller configuration sequence.
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*/
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#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
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#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
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#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
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#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
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#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
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/*
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* 32KB, 8-bit wide for ADS config reg
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*/
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#define CONFIG_SYS_BR4_PRELIM 0xf8000801
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#define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
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#define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
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#define CONFIG_SYS_INIT_RAM_LOCK 1
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#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
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#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
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/* Serial Port */
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#define CONFIG_CONS_ON_SCC /* define if console on SCC */
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#undef CONFIG_CONS_NONE /* define if console on something else */
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#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
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/*
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* I2C
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*/
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 400000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
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#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
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/* RapidIO MMU */
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#define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */
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#define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */
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#define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
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#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
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/*
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* General PCI
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* Memory space is mapped 1-1, but I/O space must start from 0.
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*/
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#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
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#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
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#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
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#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
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#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
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#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
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#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
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#if defined(CONFIG_PCI)
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#undef CONFIG_EEPRO100
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#undef CONFIG_TULIP
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#if !defined(CONFIG_PCI_PNP)
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#define PCI_ENET0_IOADDR 0xe0000000
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#define PCI_ENET0_MEMADDR 0xe0000000
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#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
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#endif
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#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
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#endif /* CONFIG_PCI */
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#ifdef CONFIG_TSEC_ENET
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#ifndef CONFIG_MII
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#define CONFIG_MII 1 /* MII PHY management */
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#endif
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#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1_NAME "TSEC0"
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#define CONFIG_TSEC2 1
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#define CONFIG_TSEC2_NAME "TSEC1"
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#define TSEC1_PHY_ADDR 0
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#define TSEC2_PHY_ADDR 1
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#define TSEC1_PHYIDX 0
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#define TSEC2_PHYIDX 0
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#define TSEC1_FLAGS TSEC_GIGABIT
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#define TSEC2_FLAGS TSEC_GIGABIT
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/* Options are: TSEC[0-1] */
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#define CONFIG_ETHPRIME "TSEC0"
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#endif /* CONFIG_TSEC_ENET */
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#ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */
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#undef CONFIG_ETHER_NONE /* define if ether on something else */
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#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
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#if (CONFIG_ETHER_INDEX == 2)
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/*
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* - Rx-CLK is CLK13
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* - Tx-CLK is CLK14
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* - Select bus for bd/buffers
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* - Full duplex
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*/
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#define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
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#define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
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#define CONFIG_SYS_CPMFCR_RAMTYPE 0
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#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
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#define FETH2_RST 0x01
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#elif (CONFIG_ETHER_INDEX == 3)
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/* need more definitions here for FE3 */
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#define FETH3_RST 0x80
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#endif /* CONFIG_ETHER_INDEX */
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#ifndef CONFIG_MII
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#define CONFIG_MII 1 /* MII PHY management */
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#endif
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#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
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/*
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* GPIO pins used for bit-banged MII communications
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*/
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#define MDIO_PORT 2 /* Port C */
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#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
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(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
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#define MDC_DECLARE MDIO_DECLARE
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#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
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#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
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#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
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#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
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else iop->pdat &= ~0x00400000
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#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
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else iop->pdat &= ~0x00200000
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#define MIIDELAY udelay(1)
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#endif
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/*
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* Environment
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*/
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#ifndef CONFIG_SYS_RAMBOOT
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
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#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
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#define CONFIG_ENV_SIZE 0x2000
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#else
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
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#define CONFIG_ENV_SIZE 0x2000
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#endif
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_CMDLINE_EDITING /* Command-line editing */
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#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
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#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 64 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
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#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#endif
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/*
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* Environment Configuration
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*/
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#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
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#define CONFIG_HAS_ETH0
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#define CONFIG_HAS_ETH1
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#define CONFIG_HAS_ETH2
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#define CONFIG_HAS_ETH3
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#endif
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#define CONFIG_IPADDR 192.168.1.253
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#define CONFIG_HOSTNAME unknown
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#define CONFIG_ROOTPATH "/nfsroot"
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#define CONFIG_BOOTFILE "your.uImage"
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#define CONFIG_SERVERIP 192.168.1.1
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#define CONFIG_GATEWAYIP 192.168.1.1
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#define CONFIG_NETMASK 255.255.255.0
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#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"consoledev=ttyCPM\0" \
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"ramdiskaddr=1000000\0" \
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"ramdiskfile=your.ramdisk.u-boot\0" \
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"fdtaddr=400000\0" \
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"fdtfile=mpc8560ads.dtb\0"
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#define CONFIG_NFSBOOTCOMMAND \
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"setenv bootargs root=/dev/nfs rw " \
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"nfsroot=$serverip:$rootpath " \
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"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
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"console=$consoledev,$baudrate $othbootargs;" \
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"tftp $loadaddr $bootfile;" \
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"tftp $fdtaddr $fdtfile;" \
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"bootm $loadaddr - $fdtaddr"
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#define CONFIG_RAMBOOTCOMMAND \
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"setenv bootargs root=/dev/ram rw " \
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"console=$consoledev,$baudrate $othbootargs;" \
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"tftp $ramdiskaddr $ramdiskfile;" \
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"tftp $loadaddr $bootfile;" \
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"tftp $fdtaddr $fdtfile;" \
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"bootm $loadaddr $ramdiskaddr $fdtaddr"
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#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
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#endif /* __CONFIG_H */
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