349 lines
10 KiB
C
349 lines
10 KiB
C
/*
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* Copyright (C) 2015 Freescale Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __LS1043A_COMMON_H
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#define __LS1043A_COMMON_H
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/* SPL build */
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#ifdef CONFIG_SPL_BUILD
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#define SPL_NO_FMAN
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#define SPL_NO_DSPI
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#define SPL_NO_PCIE
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#define SPL_NO_ENV
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#define SPL_NO_MISC
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#define SPL_NO_USB
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#define SPL_NO_SATA
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#define SPL_NO_QE
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#define SPL_NO_EEPROM
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#endif
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#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
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#define SPL_NO_MMC
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#endif
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#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT))
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#define SPL_NO_IFC
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#endif
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#define CONFIG_REMAKE_ELF
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#define CONFIG_FSL_LAYERSCAPE
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#define CONFIG_MP
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#define CONFIG_GICV2
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#include <asm/arch/stream_id_lsch2.h>
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#include <asm/arch/config.h>
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/* Link Definitions */
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
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#define CONFIG_SUPPORT_RAW_INITRD
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_VERY_BIG_RAM
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
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#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
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#define CPU_RELEASE_ADDR secondary_boot_func
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/* Generic Timer Definitions */
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#define COUNTER_FREQUENCY 25000000 /* 25MHz */
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
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/* Serial Port */
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/* SD boot SPL */
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#ifdef CONFIG_SD_BOOT
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_SPL_TEXT_BASE 0x10000000
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#define CONFIG_SPL_MAX_SIZE 0x17000
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#define CONFIG_SPL_STACK 0x1001e000
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#define CONFIG_SPL_PAD_TO 0x1d000
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#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
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CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
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#define CONFIG_SPL_BSS_START_ADDR 0x80100000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
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#ifdef CONFIG_SECURE_BOOT
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#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
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/*
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* HDR would be appended at end of image and copied to DDR along
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* with U-Boot image. Here u-boot max. size is 512K. So if binary
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* size increases then increase this size in case of secure boot as
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* it uses raw u-boot image instead of fit image.
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*/
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#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
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#else
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#define CONFIG_SYS_MONITOR_LEN 0x100000
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#endif /* ifdef CONFIG_SECURE_BOOT */
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#endif
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/* NAND SPL */
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#ifdef CONFIG_NAND_BOOT
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#define CONFIG_SPL_PBL_PAD
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_SPL_TEXT_BASE 0x10000000
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#define CONFIG_SPL_MAX_SIZE 0x1a000
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#define CONFIG_SPL_STACK 0x1001d000
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#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
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#define CONFIG_SPL_BSS_START_ADDR 0x80100000
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
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#ifdef CONFIG_SECURE_BOOT
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#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
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#endif /* ifdef CONFIG_SECURE_BOOT */
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#ifdef CONFIG_U_BOOT_HDR_SIZE
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/*
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* HDR would be appended at end of image and copied to DDR along
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* with U-Boot image. Here u-boot max. size is 512K. So if binary
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* size increases then increase this size in case of secure boot as
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* it uses raw u-boot image instead of fit image.
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*/
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#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
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#else
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#define CONFIG_SYS_MONITOR_LEN 0x100000
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#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
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#endif
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/* IFC */
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#ifndef SPL_NO_IFC
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#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
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#define CONFIG_FSL_IFC
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/*
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* CONFIG_SYS_FLASH_BASE has the final address (core view)
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* CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
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* CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
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* CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
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*/
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#define CONFIG_SYS_FLASH_BASE 0x60000000
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#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
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#ifdef CONFIG_MTD_NOR_FLASH
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
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#define CONFIG_SYS_FLASH_QUIET_TEST
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#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
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#endif
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#endif
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#endif
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_MXC
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#define CONFIG_SYS_I2C_MXC_I2C1
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#define CONFIG_SYS_I2C_MXC_I2C2
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#define CONFIG_SYS_I2C_MXC_I2C3
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#define CONFIG_SYS_I2C_MXC_I2C4
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/* PCIe */
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#ifndef SPL_NO_PCIE
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#define CONFIG_PCIE1 /* PCIE controller 1 */
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#define CONFIG_PCIE2 /* PCIE controller 2 */
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#define CONFIG_PCIE3 /* PCIE controller 3 */
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#ifdef CONFIG_PCI
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#define CONFIG_NET_MULTI
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#define CONFIG_PCI_SCAN_SHOW
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#endif
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#endif
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/* Command line configuration */
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/* MMC */
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#ifndef SPL_NO_MMC
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#ifdef CONFIG_MMC
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#define CONFIG_FSL_ESDHC
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#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
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#endif
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#endif
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/* DSPI */
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#ifndef SPL_NO_DSPI
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#define CONFIG_FSL_DSPI
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#ifdef CONFIG_FSL_DSPI
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#define CONFIG_DM_SPI_FLASH
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#define CONFIG_SPI_FLASH_STMICRO /* cs0 */
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#define CONFIG_SPI_FLASH_SST /* cs1 */
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#define CONFIG_SPI_FLASH_EON /* cs2 */
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#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
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#define CONFIG_SF_DEFAULT_BUS 1
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#define CONFIG_SF_DEFAULT_CS 0
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#endif
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#endif
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#endif
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/* FMan ucode */
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#ifndef SPL_NO_FMAN
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#define CONFIG_SYS_DPAA_FMAN
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#ifdef CONFIG_SYS_DPAA_FMAN
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#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
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#ifdef CONFIG_NAND_BOOT
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/* Store Fman ucode at offeset 0x900000(72 blocks). */
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#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
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#define CONFIG_SYS_FMAN_FW_ADDR (72 * CONFIG_SYS_NAND_BLOCK_SIZE)
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#elif defined(CONFIG_SD_BOOT)
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/*
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* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
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* about 1MB (2040 blocks), Env is stored after the image, and the env size is
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* 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 18432(0x4800).
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*/
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#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
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#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800)
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#define CONFIG_SYS_QE_FW_ADDR (512 * 0x4a08)
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#elif defined(CONFIG_QSPI_BOOT)
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#define CONFIG_SYS_QE_FW_IN_SPIFLASH
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#define CONFIG_SYS_FMAN_FW_ADDR 0x40900000
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#define CONFIG_ENV_SPI_BUS 0
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#define CONFIG_ENV_SPI_CS 0
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#define CONFIG_ENV_SPI_MAX_HZ 1000000
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#define CONFIG_ENV_SPI_MODE 0x03
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#else
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#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
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/* FMan fireware Pre-load address */
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#define CONFIG_SYS_FMAN_FW_ADDR 0x60900000
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#define CONFIG_SYS_QE_FW_ADDR 0x60940000
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#endif
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#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
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#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
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#endif
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#endif
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/* Miscellaneous configurable options */
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
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#define CONFIG_HWCONFIG
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#define HWCONFIG_BUFFER_SIZE 128
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#ifndef SPL_NO_MISC
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#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
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#define MTDPARTS_DEFAULT "mtdparts=spi0.0:1m(uboot)," \
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"5m(kernel),1m(dtb),9m(file_system)"
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#else
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#define MTDPARTS_DEFAULT "mtdparts=60000000.nor:" \
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"2m@0x100000(nor_bank0_uboot),"\
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"40m@0x1100000(nor_bank0_fit)," \
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"7m(nor_bank0_user)," \
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"2m@0x4100000(nor_bank4_uboot)," \
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"40m@0x5100000(nor_bank4_fit),"\
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"-(nor_bank4_user);" \
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"7e800000.flash:" \
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"1m(nand_uboot),1m(nand_uboot_env)," \
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"20m(nand_fit);spi0.0:1m(uboot)," \
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"5m(kernel),1m(dtb),9m(file_system)"
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#endif
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#include <config_distro_defaults.h>
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#ifndef CONFIG_SPL_BUILD
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#define BOOT_TARGET_DEVICES(func) \
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func(MMC, mmc, 0) \
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func(USB, usb, 0)
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#include <config_distro_bootcmd.h>
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#endif
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/* Initial environment variables */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"hwconfig=fsl_ddr:bank_intlv=auto\0" \
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"fdt_high=0xffffffffffffffff\0" \
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"initrd_high=0xffffffffffffffff\0" \
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"fdt_addr=0x64f00000\0" \
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"kernel_addr=0x65000000\0" \
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"scriptaddr=0x80000000\0" \
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"scripthdraddr=0x80080000\0" \
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"fdtheader_addr_r=0x80100000\0" \
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"kernelheader_addr_r=0x80200000\0" \
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"kernel_addr_r=0x81000000\0" \
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"fdt_addr_r=0x90000000\0" \
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"load_addr=0xa0000000\0" \
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"kernel_size=0x2800000\0" \
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"console=ttyS0,115200\0" \
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"mtdparts=" MTDPARTS_DEFAULT "\0" \
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BOOTENV \
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"boot_scripts=ls1043ardb_boot.scr\0" \
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"boot_script_hdr=hdr_ls1043ardb_bs.out\0" \
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"scan_dev_for_boot_part=" \
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"part list ${devtype} ${devnum} devplist; " \
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"env exists devplist || setenv devplist 1; " \
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"for distro_bootpart in ${devplist}; do " \
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"if fstype ${devtype} " \
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"${devnum}:${distro_bootpart} " \
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"bootfstype; then " \
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"run scan_dev_for_boot; " \
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"fi; " \
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"done\0" \
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"scan_dev_for_boot=" \
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"echo Scanning ${devtype} " \
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"${devnum}:${distro_bootpart}...; " \
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"for prefix in ${boot_prefixes}; do " \
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"run scan_dev_for_scripts; " \
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"done;\0" \
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"boot_a_script=" \
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"load ${devtype} ${devnum}:${distro_bootpart} " \
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"${scriptaddr} ${prefix}${script}; " \
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"env exists secureboot && load ${devtype} " \
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"${devnum}:${distro_bootpart} " \
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"${scripthdraddr} ${prefix}${boot_script_hdr} " \
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"&& esbc_validate ${scripthdraddr};" \
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"source ${scriptaddr}\0" \
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"installer=load mmc 0:2 $load_addr " \
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"/flex_installer_arm64.itb; " \
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"bootm $load_addr#ls1043ardb\0" \
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"qspi_bootcmd=echo Trying load from qspi..;" \
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"sf probe && sf read $load_addr " \
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"$kernel_addr $kernel_size && bootm $load_addr#$board\0" \
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"nor_bootcmd=echo Trying load from nor..;" \
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"cp.b $kernel_addr $load_addr " \
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"$kernel_size && bootm $load_addr#$board\0"
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#undef CONFIG_BOOTCOMMAND
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#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
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#define CONFIG_BOOTCOMMAND "run distro_bootcmd; env exists secureboot" \
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"&& esbc_halt; run qspi_bootcmd;"
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#else
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#define CONFIG_BOOTCOMMAND "run distro_bootcmd; env exists secureboot" \
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"&& esbc_halt; run nor_bootcmd;"
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#endif
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#endif
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/* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
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#define CONFIG_SYS_LONGHELP
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#ifndef SPL_NO_MISC
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#ifndef CONFIG_CMDLINE_EDITING
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#define CONFIG_CMDLINE_EDITING 1
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#endif
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#endif
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#define CONFIG_AUTO_COMPLETE
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#define CONFIG_SYS_MAXARGS 64 /* max command args */
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#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
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#include <asm/arch/soc.h>
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#endif /* __LS1043A_COMMON_H */
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