162 lines
		
	
	
		
			4.3 KiB
		
	
	
	
		
			C
		
	
	
	
			
		
		
	
	
			162 lines
		
	
	
		
			4.3 KiB
		
	
	
	
		
			C
		
	
	
	
| /*
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|  * Copyright (C) 2013 Marek Vasut <marex@denx.de>
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|  *
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|  * This program is free software; you can redistribute it and/or
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|  * modify it under the terms of the GNU General Public License as
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|  * published by the Free Software Foundation; either version 2 of
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|  * the License, or (at your option) any later version.
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|  *
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|  * This program is distributed in the hope that it will be useful,
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|  * but WITHOUT ANY WARRANTY; without even the implied warranty of
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|  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
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|  * GNU General Public License for more details.
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|  *
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|  * You should have received a copy of the GNU General Public License
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|  * along with this program; if not, write to the Free Software
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|  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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|  * MA 02111-1307 USA
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|  */
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| #ifndef __CONFIGS_MXS_H__
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| #define __CONFIGS_MXS_H__
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| 
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| /*
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|  * Includes
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|  */
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| 
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| #if defined(CONFIG_MX23) && defined(CONFIG_MX28)
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| #error Select either CONFIG_MX23 or CONFIG_MX28 , never both!
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| #elif !defined(CONFIG_MX23) && !defined(CONFIG_MX28)
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| #error Select one of CONFIG_MX23 or CONFIG_MX28 !
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| #endif
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| 
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| #include <asm/arch/regs-base.h>
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| 
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| #if defined(CONFIG_MX23)
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| #include <asm/arch/iomux-mx23.h>
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| #elif defined(CONFIG_MX28)
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| #include <asm/arch/iomux-mx28.h>
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| #endif
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| 
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| /*
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|  * CPU specifics
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|  */
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| 
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| /* Startup hooks */
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| 
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| /* SPL */
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| #define CONFIG_SPL_NO_CPU_SUPPORT_CODE
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| #define CONFIG_SPL_START_S_PATH	"arch/arm/cpu/arm926ejs/mxs"
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| 
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| /* Memory sizes */
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| #define CONFIG_SYS_MALLOC_LEN		0x00400000	/* 4 MB for malloc */
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| #define CONFIG_SYS_MEMTEST_START	0x40000000	/* Memtest start adr */
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| #define CONFIG_SYS_MEMTEST_END		0x40400000	/* 4 MB RAM test */
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| 
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| /* OCRAM at 0x0 ; 32kB on MX23 ; 128kB on MX28 */
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| #define CONFIG_SYS_INIT_RAM_ADDR	0x00000000
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| #if defined(CONFIG_MX23)
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| #define CONFIG_SYS_INIT_RAM_SIZE	(32 * 1024)
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| #elif defined(CONFIG_MX28)
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| #define CONFIG_SYS_INIT_RAM_SIZE	(128 * 1024)
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| #endif
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| 
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| /* Point initial SP in SRAM so SPL can use it too. */
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| #define CONFIG_SYS_INIT_SP_OFFSET \
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| 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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| #define CONFIG_SYS_INIT_SP_ADDR \
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| 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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| 
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| /*
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|  * We need to sacrifice first 4 bytes of RAM here to avoid triggering some
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|  * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot
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|  * binary. In case there was more of this mess, 0x100 bytes are skipped.
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|  *
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|  * In case of a HAB boot, we cannot for some weird reason use the first 4KiB
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|  * of DRAM when loading. Moreover, we use the first 4 KiB for IVT and CST
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|  * blocks, thus U-Boot starts at offset +8 KiB of DRAM start.
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|  *
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|  * As for the SPL, we must avoid the first 4 KiB as well, but we load the
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|  * IVT and CST to 0x8000, so we don't need to waste the subsequent 4 KiB.
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|  */
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| #define CONFIG_SYS_TEXT_BASE		0x40002000
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| #define CONFIG_SPL_TEXT_BASE		0x00001000
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| 
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| /* U-Boot general configuration */
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| #define CONFIG_SYS_LONGHELP
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| #define CONFIG_SYS_CBSIZE	1024		/* Console I/O buffer size */
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| #define CONFIG_SYS_MAXARGS	32		/* Max number of command args */
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| #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
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| 						/* Boot argument buffer size */
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| #define CONFIG_AUTO_COMPLETE			/* Command auto complete */
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| #define CONFIG_CMDLINE_EDITING			/* Command history etc */
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| 
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| /* Booting Linux */
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| #define CONFIG_CMDLINE_TAG
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| #define CONFIG_SETUP_MEMORY_TAGS
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| 
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| /*
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|  * Drivers
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|  */
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| 
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| /* APBH DMA */
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| 
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| /* GPIO */
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| #define CONFIG_MXS_GPIO
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| 
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| /*
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|  * DUART Serial Driver.
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|  * Conflicts with AUART driver which can be set by board.
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|  */
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| #define CONFIG_PL011_SERIAL
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| #define CONFIG_PL011_CLOCK		24000000
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| #define CONFIG_PL01x_PORTS		{ (void *)MXS_UARTDBG_BASE }
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| #define CONFIG_CONS_INDEX		0
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| /* Default baudrate can be overridden by board! */
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| 
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| /* FEC Ethernet on SoC */
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| #ifdef CONFIG_FEC_MXC
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| #define CONFIG_MII
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| #ifndef CONFIG_ETHPRIME
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| #define CONFIG_ETHPRIME			"FEC0"
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| #endif
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| #ifndef CONFIG_FEC_XCV_TYPE
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| #define CONFIG_FEC_XCV_TYPE		RMII
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| #endif
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| #endif
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| 
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| /* LCD */
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| #ifdef CONFIG_VIDEO
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| #define CONFIG_VIDEO_MXS
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| #endif
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| 
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| /* MMC */
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| #ifdef CONFIG_CMD_MMC
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| #define CONFIG_BOUNCE_BUFFER
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| #endif
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| 
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| /* NAND */
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| #ifdef CONFIG_CMD_NAND
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| #define CONFIG_SYS_MAX_NAND_DEVICE	1
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| #define CONFIG_SYS_NAND_BASE		0x60000000
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| #define CONFIG_SYS_NAND_5_ADDR_CYCLE
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| #endif
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| 
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| /* OCOTP */
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| #ifdef CONFIG_CMD_FUSE
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| #define CONFIG_MXS_OCOTP
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| #endif
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| 
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| /* SPI */
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| #ifdef CONFIG_CMD_SPI
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| #define CONFIG_HARD_SPI
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| #define CONFIG_SPI_HALF_DUPLEX
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| #endif
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| 
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| /* USB */
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| #ifdef CONFIG_CMD_USB
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| #define CONFIG_USB_EHCI_MXS
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| #define CONFIG_EHCI_IS_TDI
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| #endif
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| 
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| #endif	/* __CONFIGS_MXS_H__ */
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